I'm trying to configure a Virtex-5 FPGA on a custom board and I'm using Xil= inx iMPACT in order to program the FPGA using a JTAG interface. But...

I'm trying to configure a Virtex-5 FPGA on a custom board and I'm using Xil= inx iMPACT in order to program the FPGA using a JTAG interface. But iMPACT = has trouble detecting the FPGA and gives an error about not being able to d= etect the FPGA even though it is powered on. I tried to program a similar b= oard and I was able to do so without any issues. The board designed is a cu= stom board...

I was poking around looking for FPGA chips in packages that work optimally for me and I found a couple of new companies that are making CPUs with...

I was poking around looking for FPGA chips in packages that work optimally for me and I found a couple of new companies that are making CPUs with FPGA fabric that aren't monsters like the Zync from Xilinx in huge BGA packages. I had found the Lattice XO3D which is now available in a 72QFN with enough I/Os to get the job done, but it's a bit pricey at over $10. There are so

I am going to use the 10MHz output of the Rubbitin frequency reference to make 50.000000000 MHz for my FPGA board. The plot is a bit...

I am going to use the 10MHz output of the Rubbitin frequency reference to make 50.000000000 MHz for my FPGA board. The plot is a bit complicated, and is planned like this: 25 MHz crystal > - FPGA board Spartan2 -> x2 DLL (delay locked loop that is a build in thing in the Spartan2 FPGA) -> 50 MHz -> divide by 5 in FPGA -> 10 MHz -> xor with 10MHz from Rubbitinn unit -> low pass -> 25MHz xta

We're into this signal processing project, using a microZed/ZYNQ thing as the compute engine. After a week or so of work by an FPGA guy...

We're into this signal processing project, using a microZed/ZYNQ thing as the compute engine. After a week or so of work by an FPGA guy and a programmer, we can now actually read and write an FPGA register from a C program, and wiggle a bit on a connector pin. Amazingly, the uZed eval kit does not include a demo of this, and the default boot image does not configure the FPGA! We're u...

I got a call from a really nice guy who has a tiny company in the Bahamas. Our gear is too expensive for his application, but it could be...

I got a call from a really nice guy who has a tiny company in the Bahamas. Our gear is too expensive for his application, but it could be done with a PCIe PC-plugin board that has an FPGA and a fast DAC. It would need analog bandwidth in the 30 MHz range, maybe 100M samples/sec or so. He would need help to program the FPGA, since the signal set that he needs to generate is kind of weird, ...

The discussion has got me to wonder, what is the lowest cost and/or the smallest CPU in an FPGA. Can a CPU with reasonable code space fit...

The discussion has got me to wonder, what is the lowest cost and/or the smallest CPU in an FPGA. Can a CPU with reasonable code space fit into a 44 pin FPGA ? Are there any 44 pin FPGAs ? hamilton

We're experimenting with heat sinking an Altera Cyclone 3 FPGA. To measure actual die temperature, we built a 19-stage ring...

We're experimenting with heat sinking an Altera Cyclone 3 FPGA. To measure actual die temperature, we built a 19-stage ring oscillator, followed by a divide-by-16 ripple counter, and brought that out. The heat source is the FPGA itself: we just clocked every available flop on the chip at 250 MHz. We stuck a thinfilm thermocouple on the top of the BGA package, and here's what we got: ...

i need to interface to an fpga input, i have a 100k pull down there that gets tied to 3.3V for my logic high signal. it's been working fine, is a...

i need to interface to an fpga input, i have a 100k pull down there that gets tied to 3.3V for my logic high signal. it's been working fine, is a 100k pull down a pretty reasonable thing to do at an fpga input?

I found this pretty impressive. I wonder if this is why Intel bought Altera or if they are not working together on this? Ulpp! Seak and yea...

I found this pretty impressive. I wonder if this is why Intel bought Altera or if they are not working together on this? Ulpp! Seak and yea shall find.... "Microsoft is using so many FPGA the company has a direct influence over the global FPGA supply and demand. Intel executive vice president, Diane Bryant, has already stated that Microsoft is the main reason behind Intel's decisio...

We're planning a new universal boot loader for a family of ST processors. The uP would host the loader in a bit of local flash and read an...

We're planning a new universal boot loader for a family of ST processors. The uP would host the loader in a bit of local flash and read an outboard serial flash to get the specific application code and one or more FPGA configurations. So, how many config bits might there be for a modern mid-range FPGA doing a moderately complex application? I think we could enable compression too. ...

How to re/program thousands fpga at once in a short time?

How to re/program thousands fpga at once in a short time?

Hi, i've worked wit 8bit/32bit microcontrollers for 5 years and now i want to explore new fields, so i'm interested in these two solutions:...

Hi, i've worked wit 8bit/32bit microcontrollers for 5 years and now i want to explore new fields, so i'm interested in these two solutions: PSoC and FPGA. I'm totally new (i don't know neither VHDL nor Verilog) and i don't understand the differences between these programmable devices. For hobby, what do you think is more useful to study? Can you suggest a low cost DevKit? Any getting starte...

This is layout iteration 18 of a new PCB layout, almost done. It's a VME module, 48 channels of isolated digital input with front-end...

This is layout iteration 18 of a new PCB layout, almost done. It's a VME module, 48 channels of isolated digital input with front-end BIST. https://dl.dropboxusercontent.com/u/53724080/PCBs/V280_18.jpg There's no uP, just some state machines in the FPGA. I like the way the FPGA looks like a crab, with claws reaching out to the circuits to the left. After The Brat had it all done, we ...

Hi guys. The last time I put ddr2 on an fpga was with virtex 4 and I was able to terminate ras/cas etc internally. I want to do the same with an...

Hi guys. The last time I put ddr2 on an fpga was with virtex 4 and I was able to terminate ras/cas etc internally. I want to do the same with an artix device and I can't find any documentation except the mig user guide which says that I can't do it. Does anyone have any experience with this, it will be a single ddr so I don't need to "stub series terminate" the signals with externa

Why I ordered a raspberry PI Things are complicatiatetered But I need to jtag FPGA board from my laptop.. This FPGA JTAG cable is for a...

Why I ordered a raspberry PI Things are complicatiatetered But I need to jtag FPGA board from my laptop.. This FPGA JTAG cable is for a parport. But raspberry PI has an IO header.. Also speed.. and via network, webpack is on yet on other PC here. The second plan: being able to record IQ signals for almost any frequency band you can think of, especially tried GPS, I was wondering if ...

We have an ST ARM trying to talk to a Xininx FPGA with a parallel bus memory interface. It doesn't work. The software person suspects an FPGA...

We have an ST ARM trying to talk to a Xininx FPGA with a parallel bus memory interface. It doesn't work. The software person suspects an FPGA bug, and vice versa. I'm going to scope things and see. And no matter how many test points you design into a board, they are seldom the right ones. https://www.dropbox.com/s/emt9wgihe5i8apy/P900_TPs_1.jpg?raw=1 -- John Larkin Highla...

I finally got a test case for my FPGA async one-shot idea, hacked into a build for something else. I got 17 different one-shots, with various...

I finally got a test case for my FPGA async one-shot idea, hacked into a build for something else. I got 17 different one-shots, with various pin locations and speed/drive strength settings. https://www.dropbox.com/s/4hxena27mpbpg54/FPGA_OS_1.JPG?raw=1 Most of the outputs look like this, with remarkably consistent timing, edges within a few hundred ps. This is typical: https://ww...

http://www.theregister.co.uk/2014/06/18/intel_fpga_custom_chip/ It sort of sounds like two chips, CPU and FPGA in a package, which doesn't...

http://www.theregister.co.uk/2014/06/18/intel_fpga_custom_chip/ It sort of sounds like two chips, CPU and FPGA in a package, which doesn't make much sense to me. https://communities.intel.com/community/itpeernetwork/datastack/blog/2014/06/18/disrupting-the-d ata-center-to-create-the-digital-services-economy Still not clear if it's one chip or two. -- John Larkin Highl

Hello, I need a moderate amount of non-volatile memory (for FPGA configuration purposes and the like), but can't tolerate configuration...

Hello, I need a moderate amount of non-volatile memory (for FPGA configuration purposes and the like), but can't tolerate configuration errors due to charge leaks, cosmic radiation or just the malfunction of the chip. I thought that something like RAID5 imposed on memory chips/SD cards would be fine. It would be extremely simple in an FPGA, but it creates a chicken and egg problem: how ca...

I'm still playing with delta-sigma A/D conversion in LT Spice. I'll be using the ADUM7703 isolated 2nd order converter, clocked at 20...

I'm still playing with delta-sigma A/D conversion in LT Spice. I'll be using the ADUM7703 isolated 2nd order converter, clocked at 20 MHz, and we're thinking now about decimation filters in an FPGA. Win was considering using a d-s encoder and an analog recovery filter. My filter will be digital, and it will be inside a high-power control loop. The FPGA will drive a bunch of DACs at 50...