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PSoC or FPGA?

Started by fasf in sci.electronics.design13 years ago 390 replies

Hi, i've worked wit 8bit/32bit microcontrollers for 5 years and now i want to explore new fields, so i'm interested in these two solutions:...

Hi, i've worked wit 8bit/32bit microcontrollers for 5 years and now i want to explore new fields, so i'm interested in these two solutions: PSoC and FPGA. I'm totally new (i don't know neither VHDL nor Verilog) and i don't understand the differences between these programmable devices. For hobby, what do you think is more useful to study? Can you suggest a low cost DevKit? Any getting starte...


ddr2 on artix fpga's

Started by rj dee in sci.electronics.design3 years ago 13 replies

Hi guys. The last time I put ddr2 on an fpga was with virtex 4 and I was able to terminate ras/cas etc internally. I want to do the same with an...

Hi guys. The last time I put ddr2 on an fpga was with virtex 4 and I was able to terminate ras/cas etc internally. I want to do the same with an artix device and I can't find any documentation except the mig user guide which says that I can't do it. Does anyone have any experience with this, it will be a single ddr so I don't need to "stub series terminate" the signals with externa


FPGA I2C sanity check

Started by Phil Hobbs in sci.electronics.design11 months ago 12 replies

So we're doing this high speed lidar camera that I've been talking about. It has a Cyclone V system-on-module, which seems pretty nice,...

So we're doing this high speed lidar camera that I've been talking about. It has a Cyclone V system-on-module, which seems pretty nice, although I haven't gone into it very deeply. For various control and monitoring things, we need to run an I2C I/O expander using a built-in I2C PHY connected to a hard core. Because we don't have fine-grained control over the I/O voltage of the FPGA...


Blowing up Chips

Started by Ricky in sci.electronics.design2 years ago 3 replies

A test fixture uses an FPGA to stimulate a board under test and analyzed the results for testing. Once in a while, maybe after testing 300 units,...

A test fixture uses an FPGA to stimulate a board under test and analyzed the results for testing. Once in a while, maybe after testing 300 units, the FPGA gets fried. The symptom is a near short from Vcc (3.3V) to ground, often with a similar short on an I/O pin. I can't find anything that would cause this. The entire circuit is 3.3V other than a pair of RS-422 chips which ha


soft-start blunder

Started by John Larkin in sci.electronics.design1 year ago 53 replies

This is a 200 watt isolating dc/dc converter: https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 Some idiot who shall not...

This is a 200 watt isolating dc/dc converter: https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 Some idiot who shall not be named figured that we could start it up by ramping up the drive pulse widths from the FPGA, starting very small and eventually making square waves. But even small pulses pull hundreds of amps and have side effects like deconfiguring the FPGA. The...


decimating a delta-sigma ADC

Started by John Larkin in sci.electronics.design8 months ago 2 replies

There are some dynamite isolated d-s ADCs around. You give them a 20 MHz clock and they output a single clocked logic level whose duty cycle...

There are some dynamite isolated d-s ADCs around. You give them a 20 MHz clock and they output a single clocked logic level whose duty cycle expresses the analog input. The data bit is "decimated", really averaged, to give an integer analog value. That is usually done in an FPGA, with a sinc3 filter or something. I'm wondering of such an ADC can be used without an FPGA. I guess an ana...


Input protection for 3.3V FPGA in a TTL world...

Started by John Robertson in sci.electronics.design3 years ago 37 replies

I am still working with a friend on a TTL level replacement for some chips on a pinball board and we have a nice FPGA (MAX 10 based) but it...

I am still working with a friend on a TTL level replacement for some chips on a pinball board and we have a nice FPGA (MAX 10 based) but it wants (of course) 3.3V I/O. I was thinking that SN74CBT16211C (24 x IO level shifter) and a TVS arrays like the D3V3X8U9LP3810-7 with a low Ohm (1 - 10R) Flame-Proof 1/8W or less resistor on the outside world interface would do for protection. ...


FPGA sensitivities

Started by John Larkin in sci.electronics.design4 years ago 22 replies

I have a time-critical thing where the signal passes through an XC7A15 FPGA and does a fair lot of stuff inside. I measured delay vs...

I have a time-critical thing where the signal passes through an XC7A15 FPGA and does a fair lot of stuff inside. I measured delay vs some voltages: 1.8 aux no measurable DC effect 3.3 vccio no measurable DC effect 2.5 vccio ditto (key io's are LVDS in this bank) +1 core -10 ps per millivolt! If I vary the trigger frequency, I can see the delay heterodyning against the 1....


What's Your Favorite Processor on an FPGA?

Started by rickman in sci.electronics.design11 years ago 82 replies

I have been working on designs of processors for FPGAs for quite a while. I have looked at the uBlaze, the picoBlaze, the NIOS, two from...

I have been working on designs of processors for FPGAs for quite a while. I have looked at the uBlaze, the picoBlaze, the NIOS, two from Lattice and any number of open source processors. Many of the open source designs were stack processors since they tend to be small and efficient in an FPGA. J1 is one I had pretty much missed until lately. It is fast and small and looks like it wa...


any raspberry pi people here?

Started by John Larkin in sci.electronics.design2 years ago 60 replies

The pi doesn't seem to have any general counter/timer hardware, like ARMs usually do. I've seen vague references to using the GPU to...

The pi doesn't seem to have any general counter/timer hardware, like ARMs usually do. I've seen vague references to using the GPU to do timings. I'd like to measure frequencies and timestamp some edges, in the 1 us sort of domain, several channels. I guess we could hang a small FPGA off to the side if pi can't do it. Do pi's have crystal oscillators? I guess we could add one too. ...


MicroZED

Started by John Larkin in sci.electronics.design11 years ago 119 replies

Has anybody used the MicroZED? It looks like a good subassembly to use on a controller board. The documentation, especially on...

Has anybody used the MicroZED? It looks like a good subassembly to use on a controller board. The documentation, especially on mechanicals, is spotty. We have an upcoming project that needs a uP, FPGA, Ethernet, DRAM, all that stuff. It's tempting to buy a little board that has all that done and working, running Linux out of the box. -- John Larkin Highland Technology...


Freescale fractional clock divider paper

Started by bitrex in sci.electronics.design6 years ago 24 replies

This looks interesting but I'm having trouble deciphering how it's actually supposed to work due to poor tech writing/diagramming on the part...

This looks interesting but I'm having trouble deciphering how it's actually supposed to work due to poor tech writing/diagramming on the part of the authors. Can anyone explain how this system is actually supposed to work or what a real-world FPGA implementation might look like?


PRBS in LT Spice

Started by John Larkin in sci.electronics.design12 years ago 25 replies

We are considering sending data over CAT6 twisted-pairs, from one FPGA to another at some 10s of meters distance. It might be prudent...

We are considering sending data over CAT6 twisted-pairs, from one FPGA to another at some 10s of meters distance. It might be prudent to transformer-couple the data, to avoid ground-loop common-mode hazards, and the obvious choice would be to use RJ45 connectors with built-in Ethernet magnetics. These seem to have inductance in the 400 uH range, which gives a low-end frequency response in t...


Looking for SMD level shifters to TTL

Started by John Robertson in sci.electronics.design3 years ago 25 replies

Working on a FPGA project and we need perhaps 30 level shifter gates. Anyone work with 3.6 to 5.0 volt interfaces that can recommend any...

Working on a FPGA project and we need perhaps 30 level shifter gates. Anyone work with 3.6 to 5.0 volt interfaces that can recommend any single part over the rest before I spend a few hours digging through Digi/Mouser/Newark's inventory? In some cases we can get away with resistors, but there is a bit of TTL level drivers needed. Thanks! John :-#)# -- (Please post followups or...


Kanerva on "Computing with 10,000-Bit Words"

Started by Joe Gwinn in sci.electronics.design3 years ago 5 replies

This article from 2014 is Kanerva's 7-page summary of the then current state of Sparse Distributed Memory, Spatter Codes, and related...

This article from 2014 is Kanerva's 7-page summary of the then current state of Sparse Distributed Memory, Spatter Codes, and related areas, with an extensive reference list. The computational engine Kanerva describes here is something that the denizens of S.E.D. could implement in a small FPGA, should it be useful to do so. A likely use would be content-addressed memory that can tolera...


Electronic components supplier.

Started by Raymond Chen in sci.electronics.design2 years ago

Hello everyone, my name is Raymond Chen. I am from Shenzhen, China. I am an electronic component supplier. Our main brands are Altera,...

Hello everyone, my name is Raymond Chen. I am from Shenzhen, China. I am an electronic component supplier. Our main brands are Altera, Xilinx, STMicroelectronics, Texas Instruments, Silicon Labs, Microchip, Analog Devices, NXP, Atmel, ON Semiconductor. We have all kinds of MCU, FPGA, capacitance resistance, and sensors. Please contact me with any purchasing needs. whatsapp:+8617318034...


Hardware Based IP Protection

Started by Ricky in sci.electronics.design2 years ago 43 replies

A customer wants me to redesign a board to eliminate the production bottlenecks. They also want all IP so they can make the boards themselves if...

A customer wants me to redesign a board to eliminate the production bottlenecks. They also want all IP so they can make the boards themselves if my company is unable to. I'm fine with that, but I'd like to have some means of assurance they won't make boards without my royalty being respected. The board has an FPGA which contains the "magic", an analog path, and a digital path


really slow PLL

Started by John Larkin in sci.electronics.design2 years ago 172 replies

Suppose I have several rackmount boxes and each has a BNC connector on the back. Each of them has an open-drain mosfet, a weak pullup, and...

Suppose I have several rackmount boxes and each has a BNC connector on the back. Each of them has an open-drain mosfet, a weak pullup, and a lowpass filtered schmitt gate back into our FPGA. I can daisy-chain several boxes with BNC cables and tees. Each box has a 40 MHz VCXO and I want to phase-lock them, or at least time-align them to always be the same within a few microseconds, l...


High speed pulse generator to test oscilloscope

Started by Anonymous in sci.electronics.design10 years ago 12 replies

Greetings I have a Tek TDS694C I will be selling, and I'd like to demo it's high speed performance by showing it detecting a rise time - I'm...

Greetings I have a Tek TDS694C I will be selling, and I'd like to demo it's high speed performance by showing it detecting a rise time - I'm trying to remember exactly what that is - somewhere in picosecnd range? Is there a chip which will show a fast rise time? I believe they use some kind of high speed fpga? thanks in advance jb


Sigma-Delta vs. Ramp

Started by Ricketty C in sci.electronics.design4 years ago 3 replies

I need to sample a number of analog signals in an FPGA. I don't want to use a BGA so the I/O count is rather limited as well as the variety of...

I need to sample a number of analog signals in an FPGA. I don't want to use a BGA so the I/O count is rather limited as well as the variety of FPGAs. Lattice makes some nice 4kLUT parts in a 48QFN, but the I/O count tops at 39 and that has to include the JTAG/configuration signals. If I use sigma delta ADCs each one is three pins, the two pin LVDS inputs and the signal output.