What is necessary for implemented a basic working FPGA circuit? For a microchip pic one just needs a stable power supply. I have not found any...

What is necessary for implemented a basic working FPGA circuit? For a microchip pic one just needs a stable power supply. I have not found any basic FPGA circuit's nor how to program them. There is mention in the manuals about programming but very little. I've bought some FPGA's but unsure about how to use them. Are they basically similar to pics in setting up the support circuitry?

I'm trying to configure a Virtex-5 FPGA on a custom board and I'm using Xil= inx iMPACT in order to program the FPGA using a JTAG interface. But...

I'm trying to configure a Virtex-5 FPGA on a custom board and I'm using Xil= inx iMPACT in order to program the FPGA using a JTAG interface. But iMPACT = has trouble detecting the FPGA and gives an error about not being able to d= etect the FPGA even though it is powered on. I tried to program a similar b= oard and I was able to do so without any issues. The board designed is a cu= stom board...

Dear All: I am thinking about my system, the picture is here: http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ I want to...

Dear All: I am thinking about my system, the picture is here: http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ I want to transfer the raw/processed image sensor data to USB 2.0 or dpram. Two choices: 1. ADC -> DSP, this means parallel ADC, then DSP processed data -> USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA- > DPRAM 2. ADC -> FPGA, this m

Dear All: I am thinking about my system, the picture is here: http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ I want to...

Dear All: I am thinking about my system, the picture is here: http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/ I want to transfer the raw/processed image sensor data to USB 2.0 or dpram. Two choices: 1. ADC -> DSP, this means parallel ADC, then DSP processed data -> USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA- > DPRAM 2. ADC -> FPGA, this mea

I don't know so much about FPGA, so: what are tha cons of use it?When fpga is avoided and an asic is used? thanks

I don't know so much about FPGA, so: what are tha cons of use it?When fpga is avoided and an asic is used? thanks

I am going to use the 10MHz output of the Rubbitin frequency reference to make 50.000000000 MHz for my FPGA board. The plot is a bit...

I am going to use the 10MHz output of the Rubbitin frequency reference to make 50.000000000 MHz for my FPGA board. The plot is a bit complicated, and is planned like this: 25 MHz crystal > - FPGA board Spartan2 -> x2 DLL (delay locked loop that is a build in thing in the Spartan2 FPGA) -> 50 MHz -> divide by 5 in FPGA -> 10 MHz -> xor with 10MHz from Rubbitinn unit -> low pass -> 25MHz xta

I am going to use the 10MHz output of the Rubbitin frequency reference to make 50.000000000 MHz for my FPGA board. The plot is a bit...

I am going to use the 10MHz output of the Rubbitin frequency reference to make 50.000000000 MHz for my FPGA board. The plot is a bit complicated, and is planned like this: 25 MHz crystal > - FPGA board Spartan2 -> x2 DLL (delay locked loop that is a build in thing in the Spartan2 FPGA) -> 50 MHz -> divide by 5 in FPGA -> 10 MHz -> xor with 10MHz from Rubbitinn unit -> low pass -> 25MHz xta

Hi: Over on comp.arch.fpga, god help you if you mention feeding a clock other than The One True Clock into an FPGA, in case you need to...

Hi: Over on comp.arch.fpga, god help you if you mention feeding a clock other than The One True Clock into an FPGA, in case you need to divide it, or make pulses out of it etc. No, you must *always* under all circumstances, re-synchronize all inputs to The One True Clock. Granted, this is a good first guideline to follow. However, it just doesn't work if the operations performed on t...

Is there a development suite that is good but can target multiple fpga manufactures? I don't really want to install a bunch of 1GB+ light...

Is there a development suite that is good but can target multiple fpga manufactures? I don't really want to install a bunch of 1GB+ light versions for each manufacture just to see which one is best. In fact I can't even get libero to run because it crashes on startup. Also, know of any links for DIY fpga programmers? How hard is it to program? I figured that one just has to feed a bitstrea...

We're into this signal processing project, using a microZed/ZYNQ thing as the compute engine. After a week or so of work by an FPGA guy...

We're into this signal processing project, using a microZed/ZYNQ thing as the compute engine. After a week or so of work by an FPGA guy and a programmer, we can now actually read and write an FPGA register from a C program, and wiggle a bit on a connector pin. Amazingly, the uZed eval kit does not include a demo of this, and the default boot image does not configure the FPGA! We're u...

I got a call from a really nice guy who has a tiny company in the Bahamas. Our gear is too expensive for his application, but it could be...

I got a call from a really nice guy who has a tiny company in the Bahamas. Our gear is too expensive for his application, but it could be done with a PCIe PC-plugin board that has an FPGA and a fast DAC. It would need analog bandwidth in the 30 MHz range, maybe 100M samples/sec or so. He would need help to program the FPGA, since the signal set that he needs to generate is kind of weird, ...

The discussion has got me to wonder, what is the lowest cost and/or the smallest CPU in an FPGA. Can a CPU with reasonable code space fit...

The discussion has got me to wonder, what is the lowest cost and/or the smallest CPU in an FPGA. Can a CPU with reasonable code space fit into a 44 pin FPGA ? Are there any 44 pin FPGAs ? hamilton

We're experimenting with heat sinking an Altera Cyclone 3 FPGA. To measure actual die temperature, we built a 19-stage ring...

We're experimenting with heat sinking an Altera Cyclone 3 FPGA. To measure actual die temperature, we built a 19-stage ring oscillator, followed by a divide-by-16 ripple counter, and brought that out. The heat source is the FPGA itself: we just clocked every available flop on the chip at 250 MHz. We stuck a thinfilm thermocouple on the top of the BGA package, and here's what we got: ...

i need to interface to an fpga input, i have a 100k pull down there that gets tied to 3.3V for my logic high signal. it's been working fine, is a...

i need to interface to an fpga input, i have a 100k pull down there that gets tied to 3.3V for my logic high signal. it's been working fine, is a 100k pull down a pretty reasonable thing to do at an fpga input?

I found this pretty impressive. I wonder if this is why Intel bought Altera or if they are not working together on this? Ulpp! Seak and yea...

I found this pretty impressive. I wonder if this is why Intel bought Altera or if they are not working together on this? Ulpp! Seak and yea shall find.... "Microsoft is using so many FPGA the company has a direct influence over the global FPGA supply and demand. Intel executive vice president, Diane Bryant, has already stated that Microsoft is the main reason behind Intel's decisio...

Some food fo thought: I'm working on a new design in which I need to bring 64 LVDS (250Mbps each/ 125MHz fmax) lines into a Spartan3 FPGA. The...

Some food fo thought: I'm working on a new design in which I need to bring 64 LVDS (250Mbps each/ 125MHz fmax) lines into a Spartan3 FPGA. The distance between the source and the FPGA is less than 2" / 5cm. Ofcourse there is a solid ground plane underneath the signals (the board will have at least 4 layers). I'm wondering if I can save a lot of pins if I feed the LVDS signals single end...

Hello=20 This is Indira from United Software Group. I hope you are doing great. We h= ave an urgent requirement with one of our direct clients...

Hello=20 This is Indira from United Software Group. I hope you are doing great. We h= ave an urgent requirement with one of our direct clients in chicago For the= position of an FPGA Designer. Please review the requirements of the posit= ion and if qualified and interested respond as soon as possible with an upd= ated copy of your resume.=20 Need FPGA Design Engineer @8months-1year in Ai...

Hello, I am trying to interface my FPGA board to the DAC board. The DAC needs four lines from the FPGA to work properly . I optocially...

Hello, I am trying to interface my FPGA board to the DAC board. The DAC needs four lines from the FPGA to work properly . I optocially isolated the four lines using four HCPL 2400. I powered up the FPGA board and DAC board separately using two different DC Lead acid battery (+5volts) inorder to preserve isolation. Now, I probed the power pins of the DAC and the optocoupler with oscillos...

Dear All, As an assignment I have to design a CCD Sensor based FPGA digital Camera. However, the Camera will be exposed to XRAY (It will be...

Dear All, As an assignment I have to design a CCD Sensor based FPGA digital Camera. However, the Camera will be exposed to XRAY (It will be placed behind an Imaging Intensifier). Does anybody know how XRAY affects the electronic circuits (The CCD Sensor and the FPGA ). What type of noise should I expect and what should I do to prevent it. Thanks in advance

In German: http://www.heise.de/newsticker/meldung/Atom-Prozessor-mit-Altera-FPGA-1140503.html Intel announces Atom CPu with Altera FPGA in...

In German: http://www.heise.de/newsticker/meldung/Atom-Prozessor-mit-Altera-FPGA-1140503.html Intel announces Atom CPu with Altera FPGA in one housing. That would be an Atom E600 with an ArriaII. 60000 logica lelements, DDR2-800 controller, 3.125 GHz transceivers, etc.