So we're doing this high speed lidar camera that I've been talking about. It has a Cyclone V system-on-module, which seems pretty nice, although I haven't gone into it very deeply. For various control and monitoring things, we need to run an I2C I/O expander using a built-in I2C PHY connected to a hard core. Because we don't have fine-grained control over the I/O voltage of the FPGA outputs, most of the I/O has to run at 2.5V, maybe including the I2C PHY. That's okay for some stuff, such as the I2C E2PROM. However, our magic sensor chip uses a single 3.3V rail for everything, so the I/O expander (currently a PCA9674A) needs to run off a +3.3V rail too. A worst-case logic high on the 2.5V side isn't guaranteed to be a HIGH on the 3.3V side, so we want to pull the I2C up to 3.3V. The Cyclone V book says that its inputs will survive 3.6V, so that's okay as long as the protection network doesn't start conducting too much below 3.3. (I2C pullups are pretty wimpy, so it doesn't take much to drag them down a bit, and I'm not immediately finding a spec on that.) For a normal chip, I'd expect it to pull up to at least +3 even if there were plain vanilla ESD diodes on the I2C pins, which would meet the logic-HIGH spec easily. FPGAs are strange beasts in some ways, though, leading to doubts. So my question is: Is it sane and reasonable to drag a 2.5V I2C on a Cyclone V up to 3.3V? Thanks Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
FPGA I2C sanity check
Started by ●June 28, 2023
Reply by ●June 28, 20232023-06-28
On Wednesday, June 28, 2023 at 1:56:17 PM UTC-4, Phil Hobbs wrote:> So we're doing this high speed lidar camera that I've been talking > about. It has a Cyclone V system-on-module, which seems pretty nice, > although I haven't gone into it very deeply. > > For various control and monitoring things, we need to run an I2C I/O > expander using a built-in I2C PHY connected to a hard core. > > Because we don't have fine-grained control over the I/O voltage of the > FPGA outputs, most of the I/O has to run at 2.5V, maybe including the > I2C PHY. That's okay for some stuff, such as the I2C E2PROM. > > However, our magic sensor chip uses a single 3.3V rail for everything, > so the I/O expander (currently a PCA9674A) needs to run off a +3.3V rail > too. > > A worst-case logic high on the 2.5V side isn't guaranteed to be a HIGH > on the 3.3V side, so we want to pull the I2C up to 3.3V. > > The Cyclone V book says that its inputs will survive 3.6V, so that's > okay as long as the protection network doesn't start conducting too much > below 3.3. (I2C pullups are pretty wimpy, so it doesn't take much to > drag them down a bit, and I'm not immediately finding a spec on that.) > > For a normal chip, I'd expect it to pull up to at least +3 even if there > were plain vanilla ESD diodes on the I2C pins, which would meet the > logic-HIGH spec easily. > > FPGAs are strange beasts in some ways, though, leading to doubts. > > So my question is: Is it sane and reasonable to drag a 2.5V I2C on a > Cyclone V up to 3.3V?Don't know, but I've never found a workable solution like this. The last Xilinx part I looked at using was the Spartans and Xilinx absolutely freaked out if you talked to them about using the I/Os remotely outside the specified range. Maybe they're a bit tougher now, but I doubt it. They make I2C level shifters. Why can you use one of those? There are also switch chips specifically designed to level shift. I used to use one of those for 3.3 to 5 volt conversion. You say, you "don't have fine-grained control over the I/O voltage of the FPGA outputs", but they do support 3.3V I/Os, right? I believe this is done on a bank basis. Why can't you dedicate an I/O bank to 3.3V? I remember with the Spartan parts, the Xilinx people would talk about how 3.3V was going to disappear from FPGAs. No one else seems to have done that. I guess Xilinx chickened out. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
Reply by ●June 28, 20232023-06-28
On Wed, 28 Jun 2023 13:56:03 -0400, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>So we're doing this high speed lidar camera that I've been talking >about. It has a Cyclone V system-on-module, which seems pretty nice, >although I haven't gone into it very deeply. > >For various control and monitoring things, we need to run an I2C I/O >expander using a built-in I2C PHY connected to a hard core. > >Because we don't have fine-grained control over the I/O voltage of the >FPGA outputs, most of the I/O has to run at 2.5V, maybe including the >I2C PHY. That's okay for some stuff, such as the I2C E2PROM. > >However, our magic sensor chip uses a single 3.3V rail for everything, >so the I/O expander (currently a PCA9674A) needs to run off a +3.3V rail >too. > >A worst-case logic high on the 2.5V side isn't guaranteed to be a HIGH >on the 3.3V side, so we want to pull the I2C up to 3.3V. > >The Cyclone V book says that its inputs will survive 3.6V, so that's >okay as long as the protection network doesn't start conducting too much >below 3.3. (I2C pullups are pretty wimpy, so it doesn't take much to >drag them down a bit, and I'm not immediately finding a spec on that.) > >For a normal chip, I'd expect it to pull up to at least +3 even if there >were plain vanilla ESD diodes on the I2C pins, which would meet the >logic-HIGH spec easily. > >FPGAs are strange beasts in some ways, though, leading to doubts. > >So my question is: Is it sane and reasonable to drag a 2.5V I2C on a >Cyclone V up to 3.3V? > >Thanks > >Phil HobbsAn open-drain with a pullup should be fine. Even if the ESD diode goes to 2.5, it will still get over +3, enough for the I2C target.
Reply by ●June 28, 20232023-06-28
On Wed, 28 Jun 2023 13:56:03 -0400, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>So we're doing this high speed lidar camera that I've been talking >about. It has a Cyclone V system-on-module, which seems pretty nice, >although I haven't gone into it very deeply. > >For various control and monitoring things, we need to run an I2C I/O >expander using a built-in I2C PHY connected to a hard core. > >Because we don't have fine-grained control over the I/O voltage of the >FPGA outputs, most of the I/O has to run at 2.5V, maybe including the >I2C PHY. That's okay for some stuff, such as the I2C E2PROM. > >However, our magic sensor chip uses a single 3.3V rail for everything, >so the I/O expander (currently a PCA9674A) needs to run off a +3.3V rail >too. > >A worst-case logic high on the 2.5V side isn't guaranteed to be a HIGH >on the 3.3V side, so we want to pull the I2C up to 3.3V. > >The Cyclone V book says that its inputs will survive 3.6V, so that's >okay as long as the protection network doesn't start conducting too much >below 3.3. (I2C pullups are pretty wimpy, so it doesn't take much to >drag them down a bit, and I'm not immediately finding a spec on that.) > >For a normal chip, I'd expect it to pull up to at least +3 even if there >were plain vanilla ESD diodes on the I2C pins, which would meet the >logic-HIGH spec easily. > >FPGAs are strange beasts in some ways, though, leading to doubts. > >So my question is: Is it sane and reasonable to drag a 2.5V I2C on a >Cyclone V up to 3.3V? > >Thanks > >Phil HobbsIn one case, I added diode drops to some 3.3v FPGA outputs to drive a few beastly 5-volt output buffers. +0.7 to +4 worked fine. The chips fried if Vhigh was 3.3. Three NL37WZ16's in parellel per line, makes nice sub-ns pulses into 50 ohms.
Reply by ●June 28, 20232023-06-28
onsdag den 28. juni 2023 kl. 22.03.19 UTC+2 skrev John Larkin:> On Wed, 28 Jun 2023 13:56:03 -0400, Phil Hobbs > <pcdhSpamM...@electrooptical.net> wrote: > > >So we're doing this high speed lidar camera that I've been talking > >about. It has a Cyclone V system-on-module, which seems pretty nice, > >although I haven't gone into it very deeply. > > > >For various control and monitoring things, we need to run an I2C I/O > >expander using a built-in I2C PHY connected to a hard core. > > > >Because we don't have fine-grained control over the I/O voltage of the > >FPGA outputs, most of the I/O has to run at 2.5V, maybe including the > >I2C PHY. That's okay for some stuff, such as the I2C E2PROM. > > > >However, our magic sensor chip uses a single 3.3V rail for everything, > >so the I/O expander (currently a PCA9674A) needs to run off a +3.3V rail > >too. > > > >A worst-case logic high on the 2.5V side isn't guaranteed to be a HIGH > >on the 3.3V side, so we want to pull the I2C up to 3.3V. > > > >The Cyclone V book says that its inputs will survive 3.6V, so that's > >okay as long as the protection network doesn't start conducting too much > >below 3.3. (I2C pullups are pretty wimpy, so it doesn't take much to > >drag them down a bit, and I'm not immediately finding a spec on that.) > > > >For a normal chip, I'd expect it to pull up to at least +3 even if there > >were plain vanilla ESD diodes on the I2C pins, which would meet the > >logic-HIGH spec easily. > > > >FPGAs are strange beasts in some ways, though, leading to doubts. > > > >So my question is: Is it sane and reasonable to drag a 2.5V I2C on a > >Cyclone V up to 3.3V? > > > >Thanks > > > >Phil Hobbs > An open-drain with a pullup should be fine. Even if the ESD diode goes > to 2.5, it will still get over +3, enough for the I2C target.looking at the datasheet it doesn't look like it has diodes to Vccio configured 2.5V,3.0V, or 3.3V IO it list 3.6V as max for single ended input with 2.5V,3.0V, or 3.3V Vccio
Reply by ●June 28, 20232023-06-28
On Wed, 28 Jun 2023 14:38:07 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>onsdag den 28. juni 2023 kl. 22.03.19 UTC+2 skrev John Larkin: >> On Wed, 28 Jun 2023 13:56:03 -0400, Phil Hobbs >> <pcdhSpamM...@electrooptical.net> wrote: >> >> >So we're doing this high speed lidar camera that I've been talking >> >about. It has a Cyclone V system-on-module, which seems pretty nice, >> >although I haven't gone into it very deeply. >> > >> >For various control and monitoring things, we need to run an I2C I/O >> >expander using a built-in I2C PHY connected to a hard core. >> > >> >Because we don't have fine-grained control over the I/O voltage of the >> >FPGA outputs, most of the I/O has to run at 2.5V, maybe including the >> >I2C PHY. That's okay for some stuff, such as the I2C E2PROM. >> > >> >However, our magic sensor chip uses a single 3.3V rail for everything, >> >so the I/O expander (currently a PCA9674A) needs to run off a +3.3V rail >> >too. >> > >> >A worst-case logic high on the 2.5V side isn't guaranteed to be a HIGH >> >on the 3.3V side, so we want to pull the I2C up to 3.3V. >> > >> >The Cyclone V book says that its inputs will survive 3.6V, so that's >> >okay as long as the protection network doesn't start conducting too much >> >below 3.3. (I2C pullups are pretty wimpy, so it doesn't take much to >> >drag them down a bit, and I'm not immediately finding a spec on that.) >> > >> >For a normal chip, I'd expect it to pull up to at least +3 even if there >> >were plain vanilla ESD diodes on the I2C pins, which would meet the >> >logic-HIGH spec easily. >> > >> >FPGAs are strange beasts in some ways, though, leading to doubts. >> > >> >So my question is: Is it sane and reasonable to drag a 2.5V I2C on a >> >Cyclone V up to 3.3V? >> > >> >Thanks >> > >> >Phil Hobbs >> An open-drain with a pullup should be fine. Even if the ESD diode goes >> to 2.5, it will still get over +3, enough for the I2C target. > >looking at the datasheet it doesn't look like it has diodes to Vccio configured 2.5V,3.0V, or 3.3V IO >it list 3.6V as max for single ended input with 2.5V,3.0V, or 3.3V Vccio > >They probably clamp to ground and 3.3v.> >We tried using FPGA pins with a few resistors as cheapie DACs, or one pin as a PWM or delta-sigma DAC, but the high and low levels are neither DC accurate nor quiet, so we ran them through external cmos buffers with solid grounds and power supply. We phase-lock VCXOs that way, with the phase-frequency comparator in the FPGA and a 1-bit output to the VCO input. Most LVDS inputs are actually OK rrio comparators, a bit more jitter than one might like.
Reply by ●June 28, 20232023-06-28
On 6/28/2023 20:56, Phil Hobbs wrote:> So we're doing this high speed lidar camera that I've been talking > about. It has a Cyclone V system-on-module, which seems pretty nice, > although I haven't gone into it very deeply. > > For various control and monitoring things, we need to run an I2C I/O > expander using a built-in I2C PHY connected to a hard core. > > Because we don't have fine-grained control over the I/O voltage of the > FPGA outputs, most of the I/O has to run at 2.5V, maybe including the > I2C PHY. That's okay for some stuff, such as the I2C E2PROM. > > However, our magic sensor chip uses a single 3.3V rail for everything, > so the I/O expander (currently a PCA9674A) needs to run off a +3.3V rail > too. > > A worst-case logic high on the 2.5V side isn't guaranteed to be a HIGH > on the 3.3V side, so we want to pull the I2C up to 3.3V. > > The Cyclone V book says that its inputs will survive 3.6V, so that's > okay as long as the protection network doesn't start conducting too much > below 3.3. (I2C pullups are pretty wimpy, so it doesn't take much to > drag them down a bit, and I'm not immediately finding a spec on that.) > > For a normal chip, I'd expect it to pull up to at least +3 even if there > were plain vanilla ESD diodes on the I2C pins, which would meet the > logic-HIGH spec easily. > > FPGAs are strange beasts in some ways, though, leading to doubts. > > So my question is: Is it sane and reasonable to drag a 2.5V I2C on a > Cyclone V up to 3.3V? > > Thanks > > Phil Hobbs >I'd be very cautious about that. If the FPGA output is just open drain you should be fine. However this is unlikely to be the case, open drain is just emulated with the upper transistor staying off all the time. Except perhaps during transients, like power up/down etc.... Then you'd have 3.3.V -> 2.5V rail. Given that the I2C will be pulled up by no less than 1K I guess this should be survivable, provided the 2.5V rail can stay 2.5 during such events. ====================================================== Dimiter Popoff, TGI http://www.tgi-sci.com ====================================================== http://www.flickr.com/photos/didi_tgi/
Reply by ●June 28, 20232023-06-28
onsdag den 28. juni 2023 kl. 23.49.46 UTC+2 skrev John Larkin:> On Wed, 28 Jun 2023 14:38:07 -0700 (PDT), Lasse Langwadt Christensen > <lang...@fonz.dk> wrote: > > >onsdag den 28. juni 2023 kl. 22.03.19 UTC+2 skrev John Larkin: > >> On Wed, 28 Jun 2023 13:56:03 -0400, Phil Hobbs > >> <pcdhSpamM...@electrooptical.net> wrote: > >> > >> >So we're doing this high speed lidar camera that I've been talking > >> >about. It has a Cyclone V system-on-module, which seems pretty nice, > >> >although I haven't gone into it very deeply. > >> > > >> >For various control and monitoring things, we need to run an I2C I/O > >> >expander using a built-in I2C PHY connected to a hard core. > >> > > >> >Because we don't have fine-grained control over the I/O voltage of the > >> >FPGA outputs, most of the I/O has to run at 2.5V, maybe including the > >> >I2C PHY. That's okay for some stuff, such as the I2C E2PROM. > >> > > >> >However, our magic sensor chip uses a single 3.3V rail for everything, > >> >so the I/O expander (currently a PCA9674A) needs to run off a +3.3V rail > >> >too. > >> > > >> >A worst-case logic high on the 2.5V side isn't guaranteed to be a HIGH > >> >on the 3.3V side, so we want to pull the I2C up to 3.3V. > >> > > >> >The Cyclone V book says that its inputs will survive 3.6V, so that's > >> >okay as long as the protection network doesn't start conducting too much > >> >below 3.3. (I2C pullups are pretty wimpy, so it doesn't take much to > >> >drag them down a bit, and I'm not immediately finding a spec on that.) > >> > > >> >For a normal chip, I'd expect it to pull up to at least +3 even if there > >> >were plain vanilla ESD diodes on the I2C pins, which would meet the > >> >logic-HIGH spec easily. > >> > > >> >FPGAs are strange beasts in some ways, though, leading to doubts. > >> > > >> >So my question is: Is it sane and reasonable to drag a 2.5V I2C on a > >> >Cyclone V up to 3.3V? > >> > > >> >Thanks > >> > > >> >Phil Hobbs > >> An open-drain with a pullup should be fine. Even if the ESD diode goes > >> to 2.5, it will still get over +3, enough for the I2C target. > > > >looking at the datasheet it doesn't look like it has diodes to Vccio configured 2.5V,3.0V, or 3.3V IO > >it list 3.6V as max for single ended input with 2.5V,3.0V, or 3.3V Vccio > > > > > They probably clamp to ground and 3.3v.I don't think so, if the IO is powered with 2.5V there is no 3.3V to clamp to Seems like quite few fpgas and mcus have started to use a zener clamp instead of a diode to supply
Reply by ●June 28, 20232023-06-28
On Wednesday, June 28, 2023 at 1:56:17 PM UTC-4, Phil Hobbs wrote:> So we're doing this high speed lidar camera that I've been talking > about. It has a Cyclone V system-on-module, which seems pretty nice, > although I haven't gone into it very deeply. > > For various control and monitoring things, we need to run an I2C I/O > expander using a built-in I2C PHY connected to a hard core. > > Because we don't have fine-grained control over the I/O voltage of the > FPGA outputs, most of the I/O has to run at 2.5V, maybe including the > I2C PHY. That's okay for some stuff, such as the I2C E2PROM. > > However, our magic sensor chip uses a single 3.3V rail for everything, > so the I/O expander (currently a PCA9674A) needs to run off a +3.3V rail > too. > > A worst-case logic high on the 2.5V side isn't guaranteed to be a HIGH > on the 3.3V side, so we want to pull the I2C up to 3.3V. > > The Cyclone V book says that its inputs will survive 3.6V, so that's > okay as long as the protection network doesn't start conducting too much > below 3.3. (I2C pullups are pretty wimpy, so it doesn't take much to > drag them down a bit, and I'm not immediately finding a spec on that.) > > For a normal chip, I'd expect it to pull up to at least +3 even if there > were plain vanilla ESD diodes on the I2C pins, which would meet the > logic-HIGH spec easily. > > FPGAs are strange beasts in some ways, though, leading to doubts. > > So my question is: Is it sane and reasonable to drag a 2.5V I2C on a > Cyclone V up to 3.3V?How much trouble is it to insert one of these*, or something similar, between the expander and sensor? Power the expander with the 2.5V. https://www.ti.com/lit/ds/symlink/txb0108.pdf * just an example, I have no idea of this product line, by function even.> > Thanks > > Phil Hobbs > > -- > Dr Philip C D Hobbs > Principal Consultant > ElectroOptical Innovations LLC / Hobbs ElectroOptics > Optics, Electro-optics, Photonics, Analog Electronics > Briarcliff Manor NY 10510 > > http://electrooptical.net > http://hobbs-eo.com
Reply by ●June 28, 20232023-06-28
On Wednesday, June 28, 2023 at 1:56:17 PM UTC-4, Phil Hobbs wrote:> So we're doing this high speed lidar camera that I've been talking > about. It has a Cyclone V system-on-module, which seems pretty nice, > although I haven't gone into it very deeply. > > For various control and monitoring things, we need to run an I2C I/O > expander using a built-in I2C PHY connected to a hard core. > > Because we don't have fine-grained control over the I/O voltage of the > FPGA outputs, most of the I/O has to run at 2.5V, maybe including the > I2C PHY. That's okay for some stuff, such as the I2C E2PROM. > > However, our magic sensor chip uses a single 3.3V rail for everything, > so the I/O expander (currently a PCA9674A) needs to run off a +3.3V rail > too. > > A worst-case logic high on the 2.5V side isn't guaranteed to be a HIGH > on the 3.3V side, so we want to pull the I2C up to 3.3V. > > The Cyclone V book says that its inputs will survive 3.6V, so that's > okay as long as the protection network doesn't start conducting too much > below 3.3. (I2C pullups are pretty wimpy, so it doesn't take much to > drag them down a bit, and I'm not immediately finding a spec on that.) > > For a normal chip, I'd expect it to pull up to at least +3 even if there > were plain vanilla ESD diodes on the I2C pins, which would meet the > logic-HIGH spec easily. > > FPGAs are strange beasts in some ways, though, leading to doubts. > > So my question is: Is it sane and reasonable to drag a 2.5V I2C on a > Cyclone V up to 3.3V?Or maybe better insert the tbx0108 between the Cyclops and the 3.3V powered expander.> > Thanks > > Phil Hobbs > > -- > Dr Philip C D Hobbs > Principal Consultant > ElectroOptical Innovations LLC / Hobbs ElectroOptics > Optics, Electro-optics, Photonics, Analog Electronics > Briarcliff Manor NY 10510 > > http://electrooptical.net > http://hobbs-eo.com
