cmos 74hc debounce pull up resistors

Started by usao in sci.electronics.design10 years ago 22 replies

I am looking to use a SPDT switch (center GND) with the NO and NC contacts wired to the inputs of a 74HC00 CMOS NAND gates. Is it necessary to...

I am looking to use a SPDT switch (center GND) with the NO and NC contacts wired to the inputs of a 74HC00 CMOS NAND gates. Is it necessary to tie both (NO and NC) inputs to power through a pull- up resistor? I have seen this done on TTL circuits, but I thought that the inputs on the CMOS had such high resistance that it would not be necessary. Yet, I also read in many places that the inputs ...


CMOS opamp 18V+, RR in and DIP-14?

Started by Joerg in sci.electronics.design3 years ago 26 replies

Gentlemen, Got an EMI (susceptibility) situation, existing design from a vendor, no major changes possible at this point other than 1:1...

Gentlemen, Got an EMI (susceptibility) situation, existing design from a vendor, no major changes possible at this point other than 1:1 component swaps. It's a quad DIP-14 in standard pinout. Bipolar right now which is EMI-prone so it has to be CMOS. JFET amps are out because we need the input range down to the negative rail and they can't do that. CMOS for 18V and higher is slim pic...


Error message on GPIB program, Help

Started by amdx in sci.electronics.design3 years ago 33 replies

Hi all, Recap- I had the low Cmos Clock Lithium Battery in a computer. I received a Cmos Clock Lithium Battery from China, had some question...

Hi all, Recap- I had the low Cmos Clock Lithium Battery in a computer. I received a Cmos Clock Lithium Battery from China, had some question about the date code. I installed the Cmos Clock Lithium Battery and had the same message low CMOS battery. I order a new one from Mouser and the computer now works properly. Now I'm onto making the computer control some HP equipment via GPIB, whi...


CMOS process at lower voltage?

Started by o pere o in sci.electronics.design6 years ago 9 replies

This is a basic question on CMOS processes. Given a fabrication process that is labellled as "1.8V process", is it possible / advisable / etc to...

This is a basic question on CMOS processes. Given a fabrication process that is labellled as "1.8V process", is it possible / advisable / etc to have a design work at _lower_ voltages? If simulations, for instance at 1.2V show up OK, is there any risk? Pere


CMOS Divide by 5.9 Cicuit

Started by Ken Knowles in sci.electronics.design3 years ago 27 replies

I have a CD4060 that uses a 32,768Hz crystal to generate a 32Hz square wave. I would like to divide this down several times in 5.9Hz...

I have a CD4060 that uses a 32,768Hz crystal to generate a 32Hz square wave. I would like to divide this down several times in 5.9Hz increments, while keeping the duty cycle at 50%. What would be the most straightforward method, preferably keeping in CMOS? Ken Knowles


Why Hasn't This Been Done with Silicon Carbide

Started by John Savard in sci.electronics.design3 years ago 58 replies

Today's microprocessors are all made using the CMOS logic family. It has the advantage of using a minimum amount of electricity, since -...

Today's microprocessors are all made using the CMOS logic family. It has the advantage of using a minimum amount of electricity, since - exce= pt for leakage currents, which are becoming more important as transistors a= nd wires shrink - electrical power is only used during changes of state. However, the performance of CMOS circuits is limited by the slower P-type F= ET branch of them - t...


Using CMOS logic for amplifying small signals

Started by Mr. B in sci.electronics.design10 years ago 16 replies

Something has occurred to me, and I was wondering if anyone knew more about this. Could a CMOS logic inverter, like a 4049, be used as a very...

Something has occurred to me, and I was wondering if anyone knew more about this. Could a CMOS logic inverter, like a 4049, be used as a very high gain amplifier if it were properly biased? I figured that the DC offset should be set at just about half the supply voltage, so that the gate was always between a '1' and a '0'. I am not sure if the gate would behave linearly in that region, or...


CMOS checksum fails

Started by Skybuck Flying in sci.electronics.design3 years ago 31 replies

Not sure what could be causing it. Seems to happen after power loss... and hard reset... also after weird electrical problem which happens...

Not sure what could be causing it. Seems to happen after power loss... and hard reset... also after weird electrical problem which happens rarely, which is solved by full power down, disconnect of cables etc. After saving settings and exiting bios, PC works as normal. Checksum error indicates some bits flipped ? What exactly is checksummed for CMOS ? Bye, Skybuck.


TS555IN question (CMOS timer)

Started by M Philbrook in sci.electronics.design2 years ago 7 replies

We have a remote signaling device that operates from a 3.2V battery source using a CMOS version of the timer.. ...

We have a remote signaling device that operates from a 3.2V battery source using a CMOS version of the timer.. http://www.st.com/web/en/resource/technical/document/datasheet/CD0000089 3.pdf At random and I mean very random, the circuit may need a power cycle. I was able to probe it while in a failed state and it appears that the chip could be latching? The only input t...


About CMOS Sensors SNR estimation

Started by kyori in sci.electronics.design10 years ago 8 replies

Hi, I wonder how to calculate the Signal-to-Noise Ratio with the datasheet of a CMOS sensor? I calculate the total excited photons...

Hi, I wonder how to calculate the Signal-to-Noise Ratio with the datasheet of a CMOS sensor? I calculate the total excited photons (Signal_N) from the irradiance, conversion gain and quantum efficiency. But, I am confused with the noise estimation. The datasheet gives, Parameter Specification Remarks FPN


Mixing 4000-series CMOS and 74HC in a 5V system - any issues?

Started by Steve Goldstein in sci.electronics.design7 months ago 29 replies

Do 4000-series CMOS inputs have any problems coping with the much faster edge rates of 74HC outputs? Everything would be running on 5V, of...

Do 4000-series CMOS inputs have any problems coping with the much faster edge rates of 74HC outputs? Everything would be running on 5V, of course. It's all "just" digital logic, but sometimes the transistors inside forget that... And yes, I know I could use a processor and write code instead of using a few packages of random logic. That's not my desire.


Cmos Battery/Clock

Started by amdx in sci.electronics.design3 years ago 23 replies

Well I've received my M48T86PC1 Cmos Clock Lithium Battery as a gift from China, according to the custom declaration. It is an ST...

Well I've received my M48T86PC1 Cmos Clock Lithium Battery as a gift from China, according to the custom declaration. It is an ST microelectronics part, my concern is the manufacturing date. The Chip is labeled as below, M48T86PC1 Real-Time Clock Contains Lithium Cell 990SN VH MYS 99 1033 WO723Y I hate s...


Low RDSon Logic CMOS Gate

Started by Klaus Kragelund in sci.electronics.design5 years ago 63 replies

Hi I need a CMOS gate with low voltage drop at about 30mA current source and s= ink. The tiny logic NL27WZ14 has 600mV drop at 32mA which...

Hi I need a CMOS gate with low voltage drop at about 30mA current source and s= ink. The tiny logic NL27WZ14 has 600mV drop at 32mA which equates to 18ohm = RDS on. I am searching for a device with less than 5-10 ohms and it would need to b= e ok to parallel to get lower resistance. Also, it must not have to much cr= ossover shoot-through (so probably schmitt trigger type) and must have ...


5-volt tolerant CMOS

Started by John Larkin in sci.electronics.design4 years ago 38 replies

Lots of CMOS gates and such are tolerant of pin voltages above Vcc, typically rated for 7 volts max. Does anybody know what sort of input...

Lots of CMOS gates and such are tolerant of pin voltages above Vcc, typically rated for 7 volts max. Does anybody know what sort of input circuits are typically used? Does it behave like a zener? To ground? Some parts specify an allowed input curent in the pullup direction, some don't. I'm designing a really tiny board, and an opamp can potentially overdrive an analog mux, an FSA3157....


New 555 Spice Model

Started by Jim Thompson in sci.electronics.design7 years ago 25 replies

Got annoyed at the flaky 555 models that are out there, so I rolled my own... http://www.analog-innovations.com/SED/MyLMC555.zip Based on...

Got annoyed at the flaky 555 models that are out there, so I rolled my own... http://www.analog-innovations.com/SED/MyLMC555.zip Based on old AMI 20V CMOS device models, mostly form/fit/function with CMOS, but some behavioral on the front-end where it doesn't matter. Optimized and fitted to National LMC555 at 5V operation. It'll work at other voltages but may sink/source more or less ...


CMOS Cookbook

Started by bitrex in sci.electronics.design4 months ago 5 replies

The local liberal arts college seems to have a copy of the 1988 edition of the CMOS Cookbook! Even seems to have been a fairly popular...

The local liberal arts college seems to have a copy of the 1988 edition of the CMOS Cookbook! Even seems to have been a fairly popular checkout in the years prior to the card catalog going all electronic:


4XXX CMOS Levels: VIL/VIH (1/3..2/3 vs 30%..70% VDD)

Started by Warren in sci.electronics.design2 years ago 4 replies

I'm trying to put this in perspective, but I haven't found a satisfying answer. You have a 1/3 VDD and 2/3 VDD as described below for logic...

I'm trying to put this in perspective, but I haven't found a satisfying answer. You have a 1/3 VDD and 2/3 VDD as described below for logic levels: https://en.wikipedia.org/wiki/Logic_level (under Logic voltage levels). And yet the datasheet values are often values that represent 30%/70%. Then there is Don Lancaster's CMOS Cookbook, which speaks of 30% and 70% levels (page 19 of the 2nd...


PING: Phil Hobbs, JFET Noise

Started by Jim Thompson in sci.electronics.design1 year ago 11 replies

Phil, What makes a JFET less noisy than a enhancement mode CMOS device? Would a depletion mode CMOS device be quieter? ...

Phil, What makes a JFET less noisy than a enhancement mode CMOS device? Would a depletion mode CMOS device be quieter? ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San ...


PSRR of CMOS inverter

Started by Martin Gruber in sci.electronics.design4 years ago 2 replies

How to calculate the PSRR for a CMOS inverter? I'm struggling a bit because I do not get meaningful result values. Let explain what I have. I...

How to calculate the PSRR for a CMOS inverter? I'm struggling a bit because I do not get meaningful result values. Let explain what I have. I have the following transistor parameters from a simulation result. High-side PMOS: rds2 = 11.67k gm2 = 879.4 uS Low-side NMOS: rds1= 20.35k gm1 = 1.659 mS With that I want to calculate the PSRR. I created the small signal equivalent as shown...


Calculate PSS of CMOS inverter

Started by Martin Gruber in sci.electronics.design4 years ago 1 reply

How to calculate the PSS (power supply sensitivity) for a CMOS inverter? I'm struggling a bit because I do not get meaningful result values....

How to calculate the PSS (power supply sensitivity) for a CMOS inverter? I'm struggling a bit because I do not get meaningful result values. Let explain what I have. I have the following transistor parameters from a simulation result. High-side PMOS: rds2 = 11.67k gm2 = 879.4 uS Low-side NMOS: rds1= 20.35k gm1 = 1.659 mS With that I want to calculate the PSS. I created th...