Usually the smoothing filter after the DAC is supposed to have a cut-off freq.

Usually the smoothing filter after the DAC is supposed to have a cut-off freq.

Hi All, I am trying to work out the likely phase lag for a lowpass filter whose job is to take out the notches from a DAC. The DAC is 12...

Hi All, I am trying to work out the likely phase lag for a lowpass filter whose job is to take out the notches from a DAC. The DAC is 12 bit and will be generating a 400Hz sinewave. It will be driven at around 250x i.e. 100kHz. So the fundamental to filter out will be 100kHz. I am not good at maths but doing some digging around, it looks like a simple RC has a 45 deg phase shift at th...

It strikes me that John Larkin's original idea of synthesising trapezoids can be made to work. You would still use a fast 14- or 16 bit DAC,...

It strikes me that John Larkin's original idea of synthesising trapezoids can be made to work. You would still use a fast 14- or 16 bit DAC, but the waveform you fed into your comparator would be made up of four sequential components - all coming out of the DAC - high segment of arbitrary length, a falling edge, a low segment, and a risng edge With a 14-bit DAC - the LTC2000 c

We were talking about TCXOs. One measures temperature and drives a varicap through some nonlinear transfer function to get minumum net TC. We...

We were talking about TCXOs. One measures temperature and drives a varicap through some nonlinear transfer function to get minumum net TC. We don't want a digital design (ADC, lookup table or polynomial, DAC) because that might add phase noise. I guess you could use a static polynomial with the equivalent of nonvolatile DPOTS as the coefficients. This occurred to me, not as anything p...

I need an isolated DAC. I could just generate a PWM thing, isolate it, and lowpass filter on the high side. But we could also generate...

I need an isolated DAC. I could just generate a PWM thing, isolate it, and lowpass filter on the high side. But we could also generate a delta-sigma bit stream, which has advantages. If d-s, I might want to reclock it before lowpass filtering to get clean, fast edges. But then I could drive several d-flops. https://www.dropbox.com/s/0d7x6l6isyoldva/ML_DS_Dac.jpg?raw=1 The analog signal...

To make a programmable-frequency clock, the usual DDS chip has A frequency-set register, N=32 or 48 bits or something which adds, every...

To make a programmable-frequency clock, the usual DDS chip has A frequency-set register, N=32 or 48 bits or something which adds, every clock, to a phase accumulator M most-significant bits of that goes into a sine lookup table Which clocks D bits into a DAC Which drives a lowpass filter and a comparator. (Ignoring DAC quantization and zero-order hold, this is the tail end o...

I'm wanting to use a microcontroller to control the output of a switching regulator, maybe something like a LM2576 simple switcher. I see the...

I'm wanting to use a microcontroller to control the output of a switching regulator, maybe something like a LM2576 simple switcher. I see the adjustability is on the feedback lead but what's the best way make it adjustable from a microcontroller. I'm guessing the feedback may be used in switching timing, ie, I guess I can't just use a DAC and get an output of 1.23V more than the DAC ...

Does anyone use the LPC176* uPs? I need to know how much current the ADC/DAC VREFP pin uses, and I can't find that anywhere. You'd think they...

Does anyone use the LPC176* uPs? I need to know how much current the ADC/DAC VREFP pin uses, and I can't find that anywhere. You'd think they might spec that. They recommend filtering it, but the eval board uses a ferrite bead. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtec...

We have two 8-channel waveform generators that were shipped 4 months ago, and came back because the customer ordered too many or something. We...

We have two 8-channel waveform generators that were shipped 4 months ago, and came back because the customer ordered too many or something. We routinely test anything that comes back, before returning them or returning to stock. What's interesting is that all 16 channels have a negative DC offset. Each channel is a diff-current-output cmos DAC, an opamp diffamp, a passive LC filter, and ...

I've been researching this and see a lot of papers and appnotes that are mostly the same. We conjecture that some capacitive-DAC pipeline...

I've been researching this and see a lot of papers and appnotes that are mostly the same. We conjecture that some capacitive-DAC pipeline ADCs do not act as if they have a single sample-and-hold in the front end, but are more complex and have, essentially, multiple s/h elements. One consequence is that the presence of very high frequency components of the signal can cause missing codes if...

In some old schematics for analog music synthesizers, where the analog signal path is under microprocessor control, I see that they use a...

In some old schematics for analog music synthesizers, where the analog signal path is under microprocessor control, I see that they use a multiplexer arrangement to route control voltages around being driven from a single DAC, usually like a DAC08 or something. They feed it into something like a 4051 multiplexer, followed up with a JFET input amp like a TL084 configured as a buffer, ...

https://www.dropbox.com/s/ryp2m1t9mr9gi17/DDS_Diff_Filter_1.jpg?raw=1 Most DDS chips have complementary DAC current outputs and the...

https://www.dropbox.com/s/ryp2m1t9mr9gi17/DDS_Diff_Filter_1.jpg?raw=1 Most DDS chips have complementary DAC current outputs and the appnotes usually waste one and go to some effort to bias up a single-ended comparator. It's not any harder to go full diff on the filter, get twice the swing, and use the zero cross. To make a clock, the filter can have a ghastly Bode plot. It doesn't have t...

Here's a quantizer in LT Spice: ftp://jjlarkin.lmi.net/Quantizer.jpg It wasn't hard, but the HELP is really obscure about syntax, and...

Here's a quantizer in LT Spice: ftp://jjlarkin.lmi.net/Quantizer.jpg It wasn't hard, but the HELP is really obscure about syntax, and there is no example of a schematic with a b-source that I could find. There is a sample-and-hold schematic symbol, so one can simulate the effects of a clocked ADC or a DAC on a control loop. John Version 4 SHEET 1 880 680 WIRE 48 48 0 48 W...

Hi, all, I have a gig coming in that will have me revisiting my thesis research from nearly 30 years ago, on interferometric laser...

Hi, all, I have a gig coming in that will have me revisiting my thesis research from nearly 30 years ago, on interferometric laser microscopes. (Fun.) Back in the day, I made a nulling-type phase digitizer at 60 MHz by driving a phase shifter with a 12-bit DAC (AD-DAC80), and wrapping a 13-bit successive approximation loop round it (AM2904 with an extra flipflop). With quite a lot ...

This is looking like a real project. I need a dual pulse with low jitter, something like...

This is looking like a real project. I need a dual pulse with low jitter, something like this: https://www.dropbox.com/s/j4df10lj6l4lcla/T500_Timing_Ramp_1.jpg?raw=1 The comparators have no spec for voltage or current noise. Worse, their input current transitions from 0 to max as the ramp crosses their various DAC thresholds. Messy. BUF602 is slick. I was considering a fast current-m...

What's the fastest periodic IRQ that you have ever run? We have one board with 12 isolated LPC1758 ARMs. Each gets interrupted by its on-chip...

What's the fastest periodic IRQ that you have ever run? We have one board with 12 isolated LPC1758 ARMs. Each gets interrupted by its on-chip ADC at 100 KHz and does a bunch of filtering and runs a PID loop, which outputs to the on-chip DAC. We cranked the CPU clock down some to save power, so the ISR runs for about 7 usec max. I ask because if I use a Pi Pico on some new projects, it has...

Hi I need to introduce and error in a signal, both quantization and sample/hold Sofar I have done it by placing an opamp based sample/hold...

Hi I need to introduce and error in a signal, both quantization and sample/hold Sofar I have done it by placing an opamp based sample/hold followed by a 8bit ADC (ADC8break) and a 8 bit DAC (DAC8break) But it doesn't feel right to use that much circuitry just to simulate an error in the system Anyone know if it can be done with ABM blocks? (sample and hold can be done with a zero order...

Dear all, at first I want to thank all the experienced guys, Phil, Winfield, Gerhard... who share their valuable knowledge. That helps a lot!...

Dear all, at first I want to thank all the experienced guys, Phil, Winfield, Gerhard... who share their valuable knowledge. That helps a lot! Thank you! I'm working at a Helmholtz facility in Germany/Dresden on equipment used in fundamental research. To measure e- and ion beam currents down to sub-pA I built up Fameio, a module including TIA (9 decadic ranges), diffamp, ADC/DAC, supplies, b...

Greetings people ! So lately, I have been working on my Sigma Delta ADC and before going advance, I wanted to have a base model WORKING (1ST...

Greetings people ! So lately, I have been working on my Sigma Delta ADC and before going advance, I wanted to have a base model WORKING (1ST ORDER, 3 bit digital output) . The circuit is quite simple. Input (x) -> Difference Amplifier -> Integrator (op-amp) -> Quantizer-> Encoder -> 3-bit Output (Y) -> Feedback DAC to the non-inverting pin of Difference Amplifier (I am using I

I'm trying to switch two 24 volt coaxial switches using a LabJack U6. I bought a sainsmart solid state relay board rated for 240AC @ 2A under...

I'm trying to switch two 24 volt coaxial switches using a LabJack U6. I bought a sainsmart solid state relay board rated for 240AC @ 2A under the (wrong?) assumption that it should have no issue with switching 24VDC. I'm using the VS output of the LabJack (4.9V) to power the input side of the relay board. I'm switching the logic inputs using the DAC 4.8 - 0 outputs (assuming the 3.3V l...