Hi guys. The last time I put ddr2 on an fpga was with virtex 4 and I was able to terminate ras/cas etc internally. I want to do the same with an artix device and I can't find any documentation except the mig user guide which says that I can't do it. Does anyone have any experience with this, it will be a single ddr so I don't need to "stub series terminate" the signals with external VTT from an SI point of view. Thanks in advance, Rob
ddr2 on artix fpga's
Started by ●May 19, 2021
Reply by ●May 19, 20212021-05-19
On Wed, 19 May 2021 08:46:08 -0700 (PDT), rj dee <rjdgroups4567@gmail.com> wrote:>Hi guys. >The last time I put ddr2 on an fpga was with virtex 4 and I was able to terminate ras/cas etc internally. I want to do the same with an artix device and I can't find any documentation except the mig user guide which says that I can't do it. Does anyone have any experience with this, it will be a single ddr so I don't need to "stub series terminate" the signals with external VTT from an SI point of view. > >Thanks in advance, RobWe recently did a DDR3 onto an XC7A15. It just worked. https://www.dropbox.com/sh/9lui60l07xygepn/AABpQ4v54OyVacYh3NnN3-o2a?dl=0 We only terminated the differential clock. Single-chip ddr rams are fairly easy. -- John Larkin Highland Technology, Inc The best designs are necessarily accidental.
Reply by ●May 19, 20212021-05-19
On Wednesday, May 19, 2021 at 11:46:12 AM UTC-4, rjdgro...@gmail.com wrote:> Hi guys. > The last time I put ddr2 on an fpga was with virtex 4 and I was able to terminate ras/cas etc internally. I want to do the same with an artix device and I can't find any documentation except the mig user guide which says that I can't do it. Does anyone have any experience with this, it will be a single ddr so I don't need to "stub series terminate" the signals with external VTT from an SI point of view. > > Thanks in advance, RobWhat Larkin said. If you keep your traces short enough you don't need to worry about transmission line effects. I believe 8 inches (4 cm) is about a ns on a circuit board. How fast are the edges? You will want to terminate the clock line to prevent double clocking and preserve the waveform shape and timing. Otherwise an optimal layout can handle the data lines, no? -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
Reply by ●May 19, 20212021-05-19
On 5/19/2021 19:12, jlarkin@highlandsniptechnology.com wrote:> On Wed, 19 May 2021 08:46:08 -0700 (PDT), rj dee > <rjdgroups4567@gmail.com> wrote: > >> Hi guys. >> The last time I put ddr2 on an fpga was with virtex 4 and I was able to terminate ras/cas etc internally. I want to do the same with an artix device and I can't find any documentation except the mig user guide which says that I can't do it. Does anyone have any experience with this, it will be a single ddr so I don't need to "stub series terminate" the signals with external VTT from an SI point of view. >> >> Thanks in advance, Rob > > We recently did a DDR3 onto an XC7A15. It just worked. > > https://www.dropbox.com/sh/9lui60l07xygepn/AABpQ4v54OyVacYh3NnN3-o2a?dl=0 > > We only terminated the differential clock. > > Single-chip ddr rams are fairly easy. > > > >What data rate did you manage? I am sort of planning something with Artix and ddr3, I wonder how long a burst their DDR controller can do (I have had - not one an FPGA - DDR controllers which are pretty limited on that, about half the time they spend on preparing the burst).
Reply by ●May 19, 20212021-05-19
onsdag den 19. maj 2021 kl. 17.46.12 UTC+2 skrev rjdgro...@gmail.com:> Hi guys. > The last time I put ddr2 on an fpga was with virtex 4 and I was able to terminate ras/cas etc internally. I want to do the same with an artix device and I can't find any documentation except the mig user guide which says that I can't do it. Does anyone have any experience with this, it will be a single ddr so I don't need to "stub series terminate" the signals with external VTT from an SI point of view. > > Thanks in advance, Robwhy DDR2 and not DDR3 ?
Reply by ●May 19, 20212021-05-19
On Wed, 19 May 2021 19:55:24 +0300, Dimiter_Popoff <dp@tgi-sci.com> wrote:>On 5/19/2021 19:12, jlarkin@highlandsniptechnology.com wrote: >> On Wed, 19 May 2021 08:46:08 -0700 (PDT), rj dee >> <rjdgroups4567@gmail.com> wrote: >> >>> Hi guys. >>> The last time I put ddr2 on an fpga was with virtex 4 and I was able to terminate ras/cas etc internally. I want to do the same with an artix device and I can't find any documentation except the mig user guide which says that I can't do it. Does anyone have any experience with this, it will be a single ddr so I don't need to "stub series terminate" the signals with external VTT from an SI point of view. >>> >>> Thanks in advance, Rob >> >> We recently did a DDR3 onto an XC7A15. It just worked. >> >> https://www.dropbox.com/sh/9lui60l07xygepn/AABpQ4v54OyVacYh3NnN3-o2a?dl=0 >> >> We only terminated the differential clock. >> >> Single-chip ddr rams are fairly easy. >> >> >> >> > >What data rate did you manage? I am sort of planning something with >Artix and ddr3, I wonder how long a burst their DDR controller can do >(I have had - not one an FPGA - DDR controllers which are pretty limited >on that, about half the time they spend on preparing the burst).I'll ask my FPGA pro; he did the Artix design. This is waveform memory for a 400 Hz power source, so we didn't need supercomputer sorts of speed. It's easy to interface one DDR chip. More makes routing and termination difficult. -- John Larkin Highland Technology, Inc The best designs are necessarily accidental.
Reply by ●May 19, 20212021-05-19
On 2021-05-19, Rick C <gnuarm.deletethisbit@gmail.com> wrote:> On Wednesday, May 19, 2021 at 11:46:12 AM UTC-4, rjdgro...@gmail.com wrote: >> Hi guys. The last time I put ddr2 on an fpga was with virtex 4 and I >> was able to terminate ras/cas etc internally. I want to do the same >> with an artix device and I can't find any documentation except the >> mig user guide which says that I can't do it. Does anyone have any >> experience with this, it will be a single ddr so I don't need to >> "stub series terminate" the signals with external VTT from an SI >> point of view. >> >> Thanks in advance, Rob > > What Larkin said. If you keep your traces short enough you don't need > to worry about transmission line effects. I believe 8 inches (4 cm)^^^^^^^^^^^^^^^???? 8 in is aprox 20cm or 4cm is aprox 1 9/16th inch> is about a ns on a circuit board. How fast are the edges? You will > want to terminate the clock line to prevent double clocking and > preserve the waveform shape and timing. Otherwise an optimal layout > can handle the data lines, no? >
Reply by ●May 19, 20212021-05-19
On 5/19/2021 20:41, jlarkin@highlandsniptechnology.com wrote:> On Wed, 19 May 2021 19:55:24 +0300, Dimiter_Popoff <dp@tgi-sci.com> > wrote: > >> On 5/19/2021 19:12, jlarkin@highlandsniptechnology.com wrote: >>> On Wed, 19 May 2021 08:46:08 -0700 (PDT), rj dee >>> <rjdgroups4567@gmail.com> wrote: >>> >>>> Hi guys. >>>> The last time I put ddr2 on an fpga was with virtex 4 and I was able to terminate ras/cas etc internally. I want to do the same with an artix device and I can't find any documentation except the mig user guide which says that I can't do it. Does anyone have any experience with this, it will be a single ddr so I don't need to "stub series terminate" the signals with external VTT from an SI point of view. >>>> >>>> Thanks in advance, Rob >>> >>> We recently did a DDR3 onto an XC7A15. It just worked. >>> >>> https://www.dropbox.com/sh/9lui60l07xygepn/AABpQ4v54OyVacYh3NnN3-o2a?dl=0 >>> >>> We only terminated the differential clock. >>> >>> Single-chip ddr rams are fairly easy. >>> >>> >>> >>> >> >> What data rate did you manage? I am sort of planning something with >> Artix and ddr3, I wonder how long a burst their DDR controller can do >> (I have had - not one an FPGA - DDR controllers which are pretty limited >> on that, about half the time they spend on preparing the burst). > > I'll ask my FPGA pro; he did the Artix design. > > This is waveform memory for a 400 Hz power source, so we didn't need > supercomputer sorts of speed. > > It's easy to interface one DDR chip. More makes routing and > termination difficult. > > >Thanks, please do ask them. I'll have much worse than this DDR3 on this board (64 bit DDR4 via a SODIMM connector - I was advised to prefer that to soldering DDR parts like I have done before for DDR1). The DDR3 I need just as display framebuffer memory, hence the need for speed. I considered using some static RAM but the figures come out pretty tragic, the least tragic part being the SRAMs will cost well in excess of $100. If I can manage to do at least say 64 clock bursts things should be fine I guess. I am (still after a very long time) at the headscratching phase, hopefully soon I'll manage to get around to doing it.
Reply by ●May 19, 20212021-05-19
On Wednesday, May 19, 2021 at 5:56:29 PM UTC+1, lang...@fonz.dk wrote:> onsdag den 19. maj 2021 kl. 17.46.12 UTC+2 skrev rjdgro...@gmail.com: > > Hi guys. > > The last time I put ddr2 on an fpga was with virtex 4 and I was able to terminate ras/cas etc internally. I want to do the same with an artix device and I can't find any documentation except the mig user guide which says that I can't do it. Does anyone have any experience with this, it will be a single ddr so I don't need to "stub series terminate" the signals with external VTT from an SI point of view. > > > > Thanks in advance, Rob > why DDR2 and not DDR3 ?I really need a few other pins on a 1v8 bank, I have none spare and 400MHz easily gives me the bandwidth I need.
Reply by ●May 19, 20212021-05-19
> > > Thanks, please do ask them. > I'll have much worse than this DDR3 on this board (64 bit DDR4 via a > SODIMM connector - I was advised to prefer that to soldering DDR parts > like I have done before for DDR1). The DDR3 I need just as display > framebuffer memory, hence the need for speed. I considered using some > static RAM but the figures come out pretty tragic, the least tragic > part being the SRAMs will cost well in excess of $100. If I can manage > to do at least say 64 clock bursts things should be fine I guess. > I am (still after a very long time) at the headscratching phase, > hopefully soon I'll manage to get around to doing it.I've designed broadcast quality realtime HD mpeg transcoders with DDR3 memories easily keeping up with the bandwidth required. Also used for 4K but each transcoder only doing a quarter of the image.
