This looks interesting but I'm having trouble deciphering how it's actually supposed to work due to poor tech writing/diagramming on the part of the authors. Can anyone explain how this system is actually supposed to work or what a real-world FPGA implementation might look like? <file:///home/matt/Downloads/freescale_programmable.pdf>
Freescale fractional clock divider paper
Started by ●November 28, 2017
Reply by ●November 28, 20172017-11-28
On 11/28/2017 01:25 PM, bitrex wrote:> This looks interesting but I'm having trouble deciphering how it's > actually supposed to work due to poor tech writing/diagramming on the > part of the authors. Can anyone explain how this system is actually > supposed to work or what a real-world FPGA implementation might look > like? > > <file:///home/matt/Downloads/freescale_programmable.pdf>Well that definitely won't help. Try this: <http://www.edn.com/Pdf/ViewPdf?contentItemId=4425716>
Reply by ●November 28, 20172017-11-28
On Tue, 28 Nov 2017 13:27:34 -0500, bitrex <bitrex@de.lete.earthlink.net> wrote:>On 11/28/2017 01:25 PM, bitrex wrote: >> This looks interesting but I'm having trouble deciphering how it's >> actually supposed to work due to poor tech writing/diagramming on the >> part of the authors. Can anyone explain how this system is actually >> supposed to work or what a real-world FPGA implementation might look >> like? >> >> <file:///home/matt/Downloads/freescale_programmable.pdf> > >Well that definitely won't help. Try this: > ><http://www.edn.com/Pdf/ViewPdf?contentItemId=4425716>What's the big deal? See... <http://www.analog-innovations.com/SED/DivideBy2p5.pdf> on the S.E.D/Schematics Page of my website, posted some 14 years ago. The "big deal" is that these two "engineers" will get H1B visas and come to the US and take your job >:-} ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | It's what you learn, after you know it all, that counts.
Reply by ●November 28, 20172017-11-28
On 11/28/2017 05:25 PM, Jim Thompson wrote:> On Tue, 28 Nov 2017 13:27:34 -0500, bitrex > <bitrex@de.lete.earthlink.net> wrote: > >> On 11/28/2017 01:25 PM, bitrex wrote: >>> This looks interesting but I'm having trouble deciphering how it's >>> actually supposed to work due to poor tech writing/diagramming on the >>> part of the authors. Can anyone explain how this system is actually >>> supposed to work or what a real-world FPGA implementation might look >>> like? >>> >>> <file:///home/matt/Downloads/freescale_programmable.pdf> >> >> Well that definitely won't help. Try this: >> >> <http://www.edn.com/Pdf/ViewPdf?contentItemId=4425716> > > What's the big deal? See... > > <http://www.analog-innovations.com/SED/DivideBy2p5.pdf> > > on the S.E.D/Schematics Page of my website, posted some 14 years ago.I'm hoping to use a colorburst xtal oscillator and divide it down by 227.5 to get the horizontal NTSC line frequency without the use of a fractional PLL (which I don't have the hardware to implement in the device I have to use) The linked paper looks like a variant on something I've seen before; have two counters that divde by 227 or 228, run them into a 2 channel multiplexer/3 bit LUT, feed the output into a divide-by-227 and run that back to the multi line-select input. Not sure exactly what improvements/ modifications they're making here> The "big deal" is that these two "engineers" will get H1B visas and > come to the US and take your job >:-} > > ...Jim Thompson >If this is the average quality of professional writing coming out of the subcontinent I'll go there and take 50 of theirs with time to spare. Hope they like shoveling snow, suckas!
Reply by ●November 28, 20172017-11-28
On 11/28/2017 05:43 PM, bitrex wrote:> On 11/28/2017 05:25 PM, Jim Thompson wrote: >> On Tue, 28 Nov 2017 13:27:34 -0500, bitrex >> <bitrex@de.lete.earthlink.net> wrote: >> >>> On 11/28/2017 01:25 PM, bitrex wrote: >>>> This looks interesting but I'm having trouble deciphering how it's >>>> actually supposed to work due to poor tech writing/diagramming on the >>>> part of the authors. Can anyone explain how this system is actually >>>> supposed to work or what a real-world FPGA implementation might look >>>> like? >>>> >>>> <file:///home/matt/Downloads/freescale_programmable.pdf> >>> >>> Well that definitely won't help. Try this: >>> >>> <http://www.edn.com/Pdf/ViewPdf?contentItemId=4425716> >> >> What's the big deal? See... >> >> <http://www.analog-innovations.com/SED/DivideBy2p5.pdf> >> >> on the S.E.D/Schematics Page of my website, posted some 14 years ago. > > I'm hoping to use a colorburst xtal oscillator and divide it down by > 227.5 to get the horizontal NTSC line frequency without the use of a > fractional PLL (which I don't have the hardware to implement in the > device I have to use) > > The linked paper looks like a variant on something I've seen before; > have two counters that divde by 227 or 228, run them into a 2 channel227 _and_ 228, rather
Reply by ●November 28, 20172017-11-28
On Tue, 28 Nov 2017 17:43:07 -0500, bitrex <bitrex@de.lete.earthlink.net> wrote:>On 11/28/2017 05:25 PM, Jim Thompson wrote: >> On Tue, 28 Nov 2017 13:27:34 -0500, bitrex >> <bitrex@de.lete.earthlink.net> wrote: >> >>> On 11/28/2017 01:25 PM, bitrex wrote: >>>> This looks interesting but I'm having trouble deciphering how it's >>>> actually supposed to work due to poor tech writing/diagramming on the >>>> part of the authors. Can anyone explain how this system is actually >>>> supposed to work or what a real-world FPGA implementation might look >>>> like? >>>> >>>> <file:///home/matt/Downloads/freescale_programmable.pdf> >>> >>> Well that definitely won't help. Try this: >>> >>> <http://www.edn.com/Pdf/ViewPdf?contentItemId=4425716> >> >> What's the big deal? See... >> >> <http://www.analog-innovations.com/SED/DivideBy2p5.pdf> >> >> on the S.E.D/Schematics Page of my website, posted some 14 years ago. > >I'm hoping to use a colorburst xtal oscillator and divide it down by >227.5 to get the horizontal NTSC line frequency without the use of a >fractional PLL (which I don't have the hardware to implement in the >device I have to use) > >The linked paper looks like a variant on something I've seen before; >have two counters that divde by 227 or 228, run them into a 2 channel >multiplexer/3 bit LUT, feed the output into a divide-by-227 and run that >back to the multi line-select input. Not sure exactly what improvements/ >modifications they're making here > > >> The "big deal" is that these two "engineers" will get H1B visas and >> come to the US and take your job >:-} >> >> ...Jim Thompson >> > >If this is the average quality of professional writing coming out of the >subcontinent I'll go there and take 50 of theirs with time to spare. >Hope they like shoveling snow, suckas!From my post: Drive U1A:A from 3.579545... Run U1A:Y thru a DIV455 ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | It's what you learn, after you know it all, that counts.
Reply by ●November 29, 20172017-11-29
On Tuesday, November 28, 2017 at 2:25:50 PM UTC-8, Jim Thompson wrote:> On Tue, 28 Nov 2017 13:27:34 -0500, bitrex > <bitrex@de.lete.earthlink.net> wrote: > > >On 11/28/2017 01:25 PM, bitrex wrote: > >> This looks interesting> ><http://www.edn.com/Pdf/ViewPdf?contentItemId=4425716> > > What's the big deal? See... > > <http://www.analog-innovations.com/SED/DivideBy2p5.pdf> > > on the S.E.D/Schematics Page of my website, posted some 14 years ago.Or, look at some old HP gear that squared up a 40 MHz clock with 74H00 and trapped the fifth harmonic... to get 200 MHz so they could divide by N, N.2, N.4, N.6, N.8... The '74H' dates the scheme, that would have been early-mid 1970s...
Reply by ●November 29, 20172017-11-29
bitrex <bitrex@de.lete.earthlink.net> wrote:> I'm hoping to use a colorburst xtal oscillator and divide it down by > 227.5 to get the horizontal NTSC line frequency without the use of a > fractional PLL (which I don't have the hardware to implement in the > device I have to use)Are they still using NTSC and designing new stuff for it?
Reply by ●November 29, 20172017-11-29
On 11/29/2017 06:46 AM, Rob wrote:> bitrex <bitrex@de.lete.earthlink.net> wrote: >> I'm hoping to use a colorburst xtal oscillator and divide it down by >> 227.5 to get the horizontal NTSC line frequency without the use of a >> fractional PLL (which I don't have the hardware to implement in the >> device I have to use) > > Are they still using NTSC and designing new stuff for it? >Who's "they"? Lots of stuff still has NTSC/PAL composite video inputs and as long as that's the case there will probably be a need for stuff with composite video outputs. The fact that with "modern" displays the signal is just fed to an ADC immediately and processed digitally is irrelevant - it still needs to have the correct timing/sync pulses.
Reply by ●November 29, 20172017-11-29
On Tuesday, 28 November 2017 18:26:02 UTC, bitrex wrote:> This looks interesting but I'm having trouble deciphering how it's > actually supposed to work due to poor tech writing/diagramming on the > part of the authors. Can anyone explain how this system is actually > supposed to work or what a real-world FPGA implementation might look > like? > > <file:///home/matt/Downloads/freescale_programmable.pdf>It's a while since I played with such things but could one not just feed the signal to an oscillator running at around 1/2.5th the frequency and have it lock. With the right amplitude it should lock on the voltage extremes but not the centre voltage of the osc input. My memory says no, only whole multiples, but I can't think of any reason why. NT
