Forums

Sigma-Delta vs. Ramp

Started by Ricketty C August 28, 2020
I need to sample a number of analog signals in an FPGA.  I don't want to use a BGA so the I/O count is rather limited as well as the variety of FPGAs.  Lattice makes some nice 4kLUT parts in a 48QFN, but the I/O count tops at 39 and that has to include the JTAG/configuration signals.  

If I use sigma delta ADCs each one is three pins, the two pin LVDS inputs and the signal output.  Three of my input signals need to be sampled at 1 ksps and 12 bits, so I'm thinking this is the best way to do it.  Four other signals are low speed and so one input can be multiplexed between them.  I can make an adequate mux with resistors and an enable signal on the four inputs.  So that is 7 I/Os for these four inputs and 9 for the higher speed signals (not that 1 ksps is fast, lol).  

The main clock is 16 MHz and I could probably add an oscillator for something faster if I need it.  I'm wondering if it is practical to save a few pins by generating a ramp instead and using a single output for the comparators rather than four outputs.  

To get 12 bit resolution on a full scale ramp would preclude PWM.  A sigma delta DAC might be able to give adequate resolution, but I'm not sure the numbers add up.  

This is a bit frustrating.  Lattice has this excellent device for what I need and they provide it in an easy to use package, but it's just a bit shy on I/O count for this app.  I suppose I could add I/O expander chips to drive the LEDs.  That would free up lines.  It just seems like a silly thing to do.  When everyone else is making smallish FPGAs with 200 I/Os and packages to match, these parts have 39 I/Os max regardless of package.  The 48QFN is the large package in this family.  

4 kLUTs, 10 kB of RAM, 4 DSP units and a PLL, but 39 I/Os max. 

The pin count problem could be solved by using the single pin LEDs.  But I don't know how much space I need to leave for the part to be out of alignment from soldering.  The light pipe we are using has a 5x5 mm space for the LED chip.  One side of that space has a leg.  So the LED will have to be off center.  How far off center depends on the amount of tolerance required for the LED to float around during soldering.  

They use vision machines to check for missing components and misalignment like diodes being reversed.  Can they check for chips not well centered?  I wonder what tolerance is normally applied? 

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  Rick C.

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On Friday, August 28, 2020 at 7:00:25 AM UTC+2, Ricketty C wrote:
> I need to sample a number of analog signals in an FPGA. I don't want to use a BGA so the I/O count is rather limited as well as the variety of FPGAs. Lattice makes some nice 4kLUT parts in a 48QFN, but the I/O count tops at 39 and that has to include the JTAG/configuration signals. > > If I use sigma delta ADCs each one is three pins, the two pin LVDS inputs and the signal output. Three of my input signals need to be sampled at 1 ksps and 12 bits, so I'm thinking this is the best way to do it. Four other signals are low speed and so one input can be multiplexed between them. I can make an adequate mux with resistors and an enable signal on the four inputs. So that is 7 I/Os for these four inputs and 9 for the higher speed signals (not that 1 ksps is fast, lol). > > The main clock is 16 MHz and I could probably add an oscillator for something faster if I need it. I'm wondering if it is practical to save a few pins by generating a ramp instead and using a single output for the comparators rather than four outputs. > > To get 12 bit resolution on a full scale ramp would preclude PWM. A sigma delta DAC might be able to give adequate resolution, but I'm not sure the numbers add up. > > This is a bit frustrating. Lattice has this excellent device for what I need and they provide it in an easy to use package, but it's just a bit shy on I/O count for this app. I suppose I could add I/O expander chips to drive the LEDs. That would free up lines. It just seems like a silly thing to do. When everyone else is making smallish FPGAs with 200 I/Os and packages to match, these parts have 39 I/Os max regardless of package. The 48QFN is the large package in this family. > > 4 kLUTs, 10 kB of RAM, 4 DSP units and a PLL, but 39 I/Os max. > > The pin count problem could be solved by using the single pin LEDs. But I don't know how much space I need to leave for the part to be out of alignment from soldering. The light pipe we are using has a 5x5 mm space for the LED chip. One side of that space has a leg. So the LED will have to be off center. How far off center depends on the amount of tolerance required for the LED to float around during soldering. > > They use vision machines to check for missing components and misalignment like diodes being reversed. Can they check for chips not well centered? I wonder what tolerance is normally applied? >
Add a 20 cent microcontroller with ADC. Then you also get 20 more IO and flexibility Cheers Klaus
On Friday, August 28, 2020 at 8:26:03 AM UTC+2, Klaus Kragelund wrote:
> On Friday, August 28, 2020 at 7:00:25 AM UTC+2, Ricketty C wrote: > > I need to sample a number of analog signals in an FPGA. I don't want to use a BGA so the I/O count is rather limited as well as the variety of FPGAs. Lattice makes some nice 4kLUT parts in a 48QFN, but the I/O count tops at 39 and that has to include the JTAG/configuration signals. > > > > If I use sigma delta ADCs each one is three pins, the two pin LVDS inputs and the signal output. Three of my input signals need to be sampled at 1 ksps and 12 bits, so I'm thinking this is the best way to do it. Four other signals are low speed and so one input can be multiplexed between them. I can make an adequate mux with resistors and an enable signal on the four inputs. So that is 7 I/Os for these four inputs and 9 for the higher speed signals (not that 1 ksps is fast, lol). > > > > The main clock is 16 MHz and I could probably add an oscillator for something faster if I need it. I'm wondering if it is practical to save a few pins by generating a ramp instead and using a single output for the comparators rather than four outputs. > > > > To get 12 bit resolution on a full scale ramp would preclude PWM. A sigma delta DAC might be able to give adequate resolution, but I'm not sure the numbers add up. > > > > This is a bit frustrating. Lattice has this excellent device for what I need and they provide it in an easy to use package, but it's just a bit shy on I/O count for this app. I suppose I could add I/O expander chips to drive the LEDs. That would free up lines. It just seems like a silly thing to do. When everyone else is making smallish FPGAs with 200 I/Os and packages to match, these parts have 39 I/Os max regardless of package. The 48QFN is the large package in this family. > > > > 4 kLUTs, 10 kB of RAM, 4 DSP units and a PLL, but 39 I/Os max. > > > > The pin count problem could be solved by using the single pin LEDs. But I don't know how much space I need to leave for the part to be out of alignment from soldering. The light pipe we are using has a 5x5 mm space for the LED chip. One side of that space has a leg. So the LED will have to be off center. How far off center depends on the amount of tolerance required for the LED to float around during soldering. > > > > They use vision machines to check for missing components and misalignment like diodes being reversed. Can they check for chips not well centered? I wonder what tolerance is normally applied? > > > Add a 20 cent microcontroller with ADC. Then you also get 20 more IO and flexibility >
Oh, if this is the same application with the motor control, the microcontroller can only be used for non-safety functions
On Thu, 27 Aug 2020 23:34:50 -0700 (PDT), Klaus Kragelund
<klauskvik@hotmail.com> wrote:

>On Friday, August 28, 2020 at 8:26:03 AM UTC+2, Klaus Kragelund wrote: >> On Friday, August 28, 2020 at 7:00:25 AM UTC+2, Ricketty C wrote: >> > I need to sample a number of analog signals in an FPGA. I don't want to use a BGA so the I/O count is rather limited as well as the variety of FPGAs. Lattice makes some nice 4kLUT parts in a 48QFN, but the I/O count tops at 39 and that has to include the JTAG/configuration signals. >> > >> > If I use sigma delta ADCs each one is three pins, the two pin LVDS inputs and the signal output. Three of my input signals need to be sampled at 1 ksps and 12 bits, so I'm thinking this is the best way to do it. Four other signals are low speed and so one input can be multiplexed between them. I can make an adequate mux with resistors and an enable signal on the four inputs. So that is 7 I/Os for these four inputs and 9 for the higher speed signals (not that 1 ksps is fast, lol). >> > >> > The main clock is 16 MHz and I could probably add an oscillator for something faster if I need it. I'm wondering if it is practical to save a few pins by generating a ramp instead and using a single output for the comparators rather than four outputs. >> > >> > To get 12 bit resolution on a full scale ramp would preclude PWM. A sigma delta DAC might be able to give adequate resolution, but I'm not sure the numbers add up. >> > >> > This is a bit frustrating. Lattice has this excellent device for what I need and they provide it in an easy to use package, but it's just a bit shy on I/O count for this app. I suppose I could add I/O expander chips to drive the LEDs. That would free up lines. It just seems like a silly thing to do. When everyone else is making smallish FPGAs with 200 I/Os and packages to match, these parts have 39 I/Os max regardless of package. The 48QFN is the large package in this family. >> > >> > 4 kLUTs, 10 kB of RAM, 4 DSP units and a PLL, but 39 I/Os max. >> > >> > The pin count problem could be solved by using the single pin LEDs. But I don't know how much space I need to leave for the part to be out of alignment from soldering. The light pipe we are using has a 5x5 mm space for the LED chip. One side of that space has a leg. So the LED will have to be off center. How far off center depends on the amount of tolerance required for the LED to float around during soldering. >> > >> > They use vision machines to check for missing components and misalignment like diodes being reversed. Can they check for chips not well centered? I wonder what tolerance is normally applied? >> > >> Add a 20 cent microcontroller with ADC. Then you also get 20 more IO and flexibility >> >Oh, if this is the same application with the motor control, the microcontroller can only be used for non-safety functions
If this is related to the ventilator project, it should be noted that these might be used close by to a defibrillator, so make sure that your device EMC handling is adequate. This is a reason to avoid processors or sequential logic whenever possible.