On Wednesday, August 17, 2022 at 1:12:32 PM UTC+10, jla...@highlandsniptechnology.com wrote:> On Tue, 16 Aug 2022 11:50:57 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote: > >tirsdag den 16. august 2022 kl. 19.46.45 UTC+2 skrev Joe Gwinn: > >> On Mon, 15 Aug 2022 19:26:28 -0700, jla...@highlandsniptechnology.com wrote: > >> >On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <d...@tgi-sci.com> wrote: > >> >>On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: > >> >>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> wrote: > >> >>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: > >> >>>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > >> >>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> wrote: > >> >>>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >> >>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:<snip>> >> >>>>>>>>> s?ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org:> One could think of clusters of bits as harmonic terms in a Fourier > series. A bit of grouping and scaling and adding could reshape a sine > into something more square. That's hard to think about too.What puzzles me is how John Larkin finds customers dumb enough to be impressed by this kind of meaningless twaddle.> Bummer is, a DDS doesn't generally step one tick at a time. In fact, it's a mess.A DDS doesn't generate ticks. It generates a staircase approximations to sine waves. John Larkin's mode of thinking about what's going on is definitely a mess.> https://www.dropbox.com/s/1xx7sz1e5rg6jsi/JLDDS_100M_4K.jpg?raw=1> and it's very different at low frequencies.The treads on the staircase are very close together - with 14-bit DAC there are 16,384 of them - and each one can sit there for a while. So what? -- Bill Sloman, Sydney
Direct digital synthesis of square waves
Started by ●August 14, 2022
Reply by ●August 17, 20222022-08-17
Reply by ●August 17, 20222022-08-17
On 2022-08-16, whit3rd <whit3rd@gmail.com> wrote:> > A smaller sine/cos table might be used with > > sine(a+b) = sine(a) cos(b) + cos(a)sine(b) > > as in, with small deviations 'b' from major steps in the table, two multiplies and > an add give you 2^20 different accurate sines from a 2^10 size sine table. > Since cos(b) will always be near unity ( 1 plus order of 2^-20 when b is under 2^-10), > you can make that one multiply and an add. Perhaps that's what the 'phase > accumulator' is for, estimating the 'b'?AKA "CORDIC" -- Jasen.
Reply by ●August 17, 20222022-08-17
On Wed, 17 Aug 2022 06:44:18 -0000 (UTC), Jasen Betts <usenet@revmaps.no-ip.org> wrote:>On 2022-08-16, whit3rd <whit3rd@gmail.com> wrote: >> >> A smaller sine/cos table might be used with >> >> sine(a+b) = sine(a) cos(b) + cos(a)sine(b) >> >> as in, with small deviations 'b' from major steps in the table, two multiplies and >> an add give you 2^20 different accurate sines from a 2^10 size sine table. >> Since cos(b) will always be near unity ( 1 plus order of 2^-20 when b is under 2^-10), >> you can make that one multiply and an add. Perhaps that's what the 'phase >> accumulator' is for, estimating the 'b'? > >AKA "CORDIC"In an FPGA, one could have the basic sine table and an interpolation slope table and maybe just add. Do the math at compile time, not run time. At some point, dac resolution becomes the limit, not sine table resolution.
Reply by ●August 17, 20222022-08-17
On Wednesday, August 17, 2022 at 11:58:31 PM UTC+10, jla...@highlandsniptechnology.com wrote:> On Wed, 17 Aug 2022 06:44:18 -0000 (UTC), Jasen Betts > <use...@revmaps.no-ip.org> wrote: > > >On 2022-08-16, whit3rd <whi...@gmail.com> wrote: > >> > >> A smaller sine/cos table might be used with > >> > >> sine(a+b) = sine(a) cos(b) + cos(a)sine(b) > >> > >> as in, with small deviations 'b' from major steps in the table, two multiplies and > >> an add give you 2^20 different accurate sines from a 2^10 size sine table. > >> Since cos(b) will always be near unity ( 1 plus order of 2^-20 when b is under 2^-10), > >> you can make that one multiply and an add. Perhaps that's what the 'phase > >> accumulator' is for, estimating the 'b'? > > > >AKA "CORDIC" > > In an FPGA, one could have the basic sine table and an interpolation > slope table and maybe just add. Do the math at compile time, not run > time. > > At some point, dac resolution becomes the limit, not sine table resolution.It's always the limit.Getting the numbers precise enough to fully exploit the DAC you've got is just putting enough digital hardware together to get long enough words. It may not be trivial, but it's always do-able. Using the DAC sensibly to solve the problem that you've got doesn't seem to be trivial either. -- Bill Sloman, Sydney
Reply by ●August 17, 20222022-08-17
On Tue, 16 Aug 2022 11:32:12 -0700, John Larkin <jlarkin@highland_atwork_technology.com> wrote:>On Tue, 16 Aug 2022 13:46:32 -0400, Joe Gwinn <joegwinn@comcast.net> >wrote: > >>On Mon, 15 Aug 2022 19:26:28 -0700, jlarkin@highlandsniptechnology.com >>wrote: >> >>>On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>>wrote: >>> >>>>On 8/15/2022 17:17, jlarkin@highlandsniptechnology.com wrote: >>>>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>>>> wrote: >>>>> >>>>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: >>>>>>> On 8/15/2022 1:08, jlarkin@highlandsniptechnology.com wrote: >>>>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>>>>>>> wrote: >>>>>>>> >>>>>>>>> On 8/14/2022 17:14, jlarkin@highlandsniptechnology.com wrote: >>>>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>>>> <langwadt@fonz.dk> wrote: >>>>>>>>>> >>>>>>>>>>> s�ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >>>>>>>>>>>> It strikes me that John Larkin's original idea of synthesising >>>>>>>>>>>> trapezoids can be made to work. >>>>>>>>>>>> >>>>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you >>>>>>>>>>>> fed into your comparator would be made up of four sequential >>>>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary >>>>>>>>>>>> length, a falling edge, a low segment, and a risng edge >>>>>>>>>>>> >>>>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind >>>>>>>>>>>> >>>>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as >>>>>>>>>>>> 16-successive steps of a staircase waveform. >>>>>>>>>>> >>>>>>>>>>> since it is for a trigger and the falling edge probably doesn't >>>>>>>>>>> matter, why not a single variable voltage step into a filter, sorta >>>>>>>>>>> like a time-to-amplitude in reverse >>>>>>>>>> >>>>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform >>>>>>>>>> to make a faster edge into a filter and comparator, to get better time >>>>>>>>>> resolution, less jitter, at low frequencies. >>>>>>>>> >>>>>>>>> I am only curious if I understand what you are after - is it some sort >>>>>>>>> of "the larger the step the less low pass I want applied to it"? >>>>>>>> >>>>>>>> When synthesizing a low frequency DDS sine wave, we step slowly >>>>>>>> through the waveform lookup table and a fixed filter doesn't >>>>>>>> interpolate waveform steps any more; it settles every step. >>>>>>>> >>>>>>>> So, is there a better waveform to use at low frequencies? >>>>>>>> >>>>>>> >>>>>>> Hmmm. I get it now (though I don't get why this is a problem, >>>>>>> likely specific to your application). I don't know how one >>>>>>> waveform would be better for you that another, don't know >>>>>>> what it is you are doing (perhaps you said and I missed it, >>>>>>> I am not following closely). >>>>>>> A pretty complex way of dealing with the steps at low frequencies >>>>>>> is perhaps to have two DACs, one of them making the output filter >>>>>>> programmable so you can dynamically change it, based on step, >>>>>>> with some preemption etc., you get the idea - and I am not sure >>>>>>> it is practical, not only because it is complex but also because >>>>>>> I have never done this, I am just musing. >>>>>> >>>>>> I missed the "we step slowly" in your post, now I get it. >>>>>> Well, the simplest way out is to step at a constant rate all the >>>>>> time. >>>>> >>>>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That >>>>> needs a sine lookup table with about 50 billion entries. And an >>>>> equally impossible DAC and comparator. >>>>> >>>>> We'll probably wind up synthesizing the high range, an octave or so, >>>>> and divide down as needed. The trick will be to make the gear shifts >>>>> appear to be seamless. >>>>> >>>>> That could get interesting. >>>>> >>>> >>>>I still don't understand what you are trying to do. Periodic sine >>>>wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >>>>wave lookup table for the slowest case. If you want to switch by >>>>operator action you have milliseconds of time to recalculate the table. >>>>If you want to switch by some external gating you only need two >>>>tables to switch between, this makes up to 200 entries. >>>>This is all way too simple and obvious so you must be after something >>>>more than that - which I haven't got yet. >>> >>>I just want a programmable-frequency trigger generator that changes >>>frequency on demand and doesn't stop for reprogramming and doesn't >>>blow up someone's laser by generating any goofy triggers. In other >>>words, goes smoothly from F1 to F2. >>> >>>With low period jitter from, say, 1 mHz to 15 Mhz. >>> >>>mHz resolution is good too. >> >>I guess I'm not seeing the problem. Ordinary DDS units with 48-bit >>accumulators can do just this, with phase continuity between the two >>frequencies, so no glitches. People implement arbitrary >>frequency-keyed waveforms this way. >> >>The phase to trig converter typically uses only the upper 10 to 14 >>bits of the 48-bit accumulator. Converter implementations vary: >>table-lookup and CORDIC being very common approaches. >> > >One problem is that, at low frequencies, the LSB of that 10 to 14 bits >changes infrequently and the lowpass filter doesn't interpolate >multiple points any more. So one gets a lot of period jitter > >>Perhaps it's time to bring the various discussion threads together and >>re-focus by restating the problem to be solved. > >I've stated it a few times: We want a perfect, programmable, >glitch-free, always right, low period jitter trigger clock. > >It's an interesting problem.If all you want to do is to generate a trigger at any frequency from 10^-3 Hz to 15*10^6 Hz in 10^-3 Hz steps, that is easily done in a phase-only DDS topology (no trig conversion needed), which can be implemented directly in a FPGA. This is also known as a Numerically Controlled Oscillator: .<https://en.wikipedia.org/wiki/Numerically-controlled_oscillator> Our output would be point /M in Figure 1 in the above Wiki article. (Never mind that M is actually a bit width in that figure.) How big must the accumulator be? 15*10^6/10^-3 = 15*10^9 possible frequencies. Log2[ 15*10^9 ] = 33.8 bits. There was also talk of needing 50^10^9 steps, which would be 35.5 bits, minimum. In either case, a 48-bit accumulator will work with room to spare. If not, simply make the accumulator larger - 64 bits is also common. One can also choose the clock rate for convenience given the chosen accumulator length. The trigger signal is when the accumulator rolls over. If the Frequency Control Word is small, this will take some time. If large, much faster. Joe Gwinn
Reply by ●August 17, 20222022-08-17
onsdag den 17. august 2022 kl. 19.02.50 UTC+2 skrev Joe Gwinn:> On Tue, 16 Aug 2022 11:32:12 -0700, John Larkin > <jlarkin@highland_atwork_technology.com> wrote: > > >On Tue, 16 Aug 2022 13:46:32 -0400, Joe Gwinn <joeg...@comcast.net> > >wrote: > > > >>On Mon, 15 Aug 2022 19:26:28 -0700, jla...@highlandsniptechnology.com > >>wrote: > >> > >>>On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>>wrote: > >>> > >>>>On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: > >>>>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>>>> wrote: > >>>>> > >>>>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: > >>>>>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > >>>>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>>>>>>> wrote: > >>>>>>>> > >>>>>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >>>>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen > >>>>>>>>>> <lang...@fonz.dk> wrote: > >>>>>>>>>> > >>>>>>>>>>> sųndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > >>>>>>>>>>>> It strikes me that John Larkin's original idea of synthesising > >>>>>>>>>>>> trapezoids can be made to work. > >>>>>>>>>>>> > >>>>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you > >>>>>>>>>>>> fed into your comparator would be made up of four sequential > >>>>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary > >>>>>>>>>>>> length, a falling edge, a low segment, and a risng edge > >>>>>>>>>>>> > >>>>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind > >>>>>>>>>>>> > >>>>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf > >>>>>>>>>>>> > >>>>>>>>>>>> > >>>>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as > >>>>>>>>>>>> 16-successive steps of a staircase waveform. > >>>>>>>>>>> > >>>>>>>>>>> since it is for a trigger and the falling edge probably doesn't > >>>>>>>>>>> matter, why not a single variable voltage step into a filter, sorta > >>>>>>>>>>> like a time-to-amplitude in reverse > >>>>>>>>>> > >>>>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform > >>>>>>>>>> to make a faster edge into a filter and comparator, to get better time > >>>>>>>>>> resolution, less jitter, at low frequencies. > >>>>>>>>> > >>>>>>>>> I am only curious if I understand what you are after - is it some sort > >>>>>>>>> of "the larger the step the less low pass I want applied to it"? > >>>>>>>> > >>>>>>>> When synthesizing a low frequency DDS sine wave, we step slowly > >>>>>>>> through the waveform lookup table and a fixed filter doesn't > >>>>>>>> interpolate waveform steps any more; it settles every step. > >>>>>>>> > >>>>>>>> So, is there a better waveform to use at low frequencies? > >>>>>>>> > >>>>>>> > >>>>>>> Hmmm. I get it now (though I don't get why this is a problem, > >>>>>>> likely specific to your application). I don't know how one > >>>>>>> waveform would be better for you that another, don't know > >>>>>>> what it is you are doing (perhaps you said and I missed it, > >>>>>>> I am not following closely). > >>>>>>> A pretty complex way of dealing with the steps at low frequencies > >>>>>>> is perhaps to have two DACs, one of them making the output filter > >>>>>>> programmable so you can dynamically change it, based on step, > >>>>>>> with some preemption etc., you get the idea - and I am not sure > >>>>>>> it is practical, not only because it is complex but also because > >>>>>>> I have never done this, I am just musing. > >>>>>> > >>>>>> I missed the "we step slowly" in your post, now I get it. > >>>>>> Well, the simplest way out is to step at a constant rate all the > >>>>>> time. > >>>>> > >>>>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > >>>>> needs a sine lookup table with about 50 billion entries. And an > >>>>> equally impossible DAC and comparator. > >>>>> > >>>>> We'll probably wind up synthesizing the high range, an octave or so, > >>>>> and divide down as needed. The trick will be to make the gear shifts > >>>>> appear to be seamless. > >>>>> > >>>>> That could get interesting. > >>>>> > >>>> > >>>>I still don't understand what you are trying to do. Periodic sine > >>>>wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > >>>>wave lookup table for the slowest case. If you want to switch by > >>>>operator action you have milliseconds of time to recalculate the table. > >>>>If you want to switch by some external gating you only need two > >>>>tables to switch between, this makes up to 200 entries. > >>>>This is all way too simple and obvious so you must be after something > >>>>more than that - which I haven't got yet. > >>> > >>>I just want a programmable-frequency trigger generator that changes > >>>frequency on demand and doesn't stop for reprogramming and doesn't > >>>blow up someone's laser by generating any goofy triggers. In other > >>>words, goes smoothly from F1 to F2. > >>> > >>>With low period jitter from, say, 1 mHz to 15 Mhz. > >>> > >>>mHz resolution is good too. > >> > >>I guess I'm not seeing the problem. Ordinary DDS units with 48-bit > >>accumulators can do just this, with phase continuity between the two > >>frequencies, so no glitches. People implement arbitrary > >>frequency-keyed waveforms this way. > >> > >>The phase to trig converter typically uses only the upper 10 to 14 > >>bits of the 48-bit accumulator. Converter implementations vary: > >>table-lookup and CORDIC being very common approaches. > >> > > > >One problem is that, at low frequencies, the LSB of that 10 to 14 bits > >changes infrequently and the lowpass filter doesn't interpolate > >multiple points any more. So one gets a lot of period jitter > > > >>Perhaps it's time to bring the various discussion threads together and > >>re-focus by restating the problem to be solved. > > > >I've stated it a few times: We want a perfect, programmable, > >glitch-free, always right, low period jitter trigger clock. > > > >It's an interesting problem. > If all you want to do is to generate a trigger at any frequency from > 10^-3 Hz to 15*10^6 Hz in 10^-3 Hz steps, that is easily done in a > phase-only DDS topology (no trig conversion needed), which can be > implemented directly in a FPGA. > > This is also known as a Numerically Controlled Oscillator: > > .<https://en.wikipedia.org/wiki/Numerically-controlled_oscillator> > > Our output would be point /M in Figure 1 in the above Wiki article. > (Never mind that M is actually a bit width in that figure.) > > How big must the accumulator be? 15*10^6/10^-3 = 15*10^9 possible > frequencies. Log2[ 15*10^9 ] = 33.8 bits. There was also talk of > needing 50^10^9 steps, which would be 35.5 bits, minimum. In either > case, a 48-bit accumulator will work with room to spare. > > If not, simply make the accumulator larger - 64 bits is also common. > One can also choose the clock rate for convenience given the chosen > accumulator length. > > The trigger signal is when the accumulator rolls over. If thedid you miss the whole discussion? doing that with say a 100MHz clock give you 10ns jitter, which might be ok low frequency, but terrible at 15MHz
Reply by ●August 17, 20222022-08-17
On Wed, 17 Aug 2022 11:15:06 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>onsdag den 17. august 2022 kl. 19.02.50 UTC+2 skrev Joe Gwinn: >> On Tue, 16 Aug 2022 11:32:12 -0700, John Larkin >> <jlarkin@highland_atwork_technology.com> wrote: >> >> >On Tue, 16 Aug 2022 13:46:32 -0400, Joe Gwinn <joeg...@comcast.net> >> >wrote: >> > >> >>On Mon, 15 Aug 2022 19:26:28 -0700, jla...@highlandsniptechnology.com >> >>wrote: >> >> >> >>>On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <d...@tgi-sci.com> >> >>>wrote: >> >>> >> >>>>On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: >> >>>>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> >> >>>>> wrote: >> >>>>> >> >>>>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: >> >>>>>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: >> >>>>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> >> >>>>>>>> wrote: >> >>>>>>>> >> >>>>>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: >> >>>>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >> >>>>>>>>>> <lang...@fonz.dk> wrote: >> >>>>>>>>>> >> >>>>>>>>>>> s?ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >> >>>>>>>>>>>> It strikes me that John Larkin's original idea of synthesising >> >>>>>>>>>>>> trapezoids can be made to work. >> >>>>>>>>>>>> >> >>>>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you >> >>>>>>>>>>>> fed into your comparator would be made up of four sequential >> >>>>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary >> >>>>>>>>>>>> length, a falling edge, a low segment, and a risng edge >> >>>>>>>>>>>> >> >>>>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind >> >>>>>>>>>>>> >> >>>>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >> >>>>>>>>>>>> >> >>>>>>>>>>>> >> >>>>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as >> >>>>>>>>>>>> 16-successive steps of a staircase waveform. >> >>>>>>>>>>> >> >>>>>>>>>>> since it is for a trigger and the falling edge probably doesn't >> >>>>>>>>>>> matter, why not a single variable voltage step into a filter, sorta >> >>>>>>>>>>> like a time-to-amplitude in reverse >> >>>>>>>>>> >> >>>>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform >> >>>>>>>>>> to make a faster edge into a filter and comparator, to get better time >> >>>>>>>>>> resolution, less jitter, at low frequencies. >> >>>>>>>>> >> >>>>>>>>> I am only curious if I understand what you are after - is it some sort >> >>>>>>>>> of "the larger the step the less low pass I want applied to it"? >> >>>>>>>> >> >>>>>>>> When synthesizing a low frequency DDS sine wave, we step slowly >> >>>>>>>> through the waveform lookup table and a fixed filter doesn't >> >>>>>>>> interpolate waveform steps any more; it settles every step. >> >>>>>>>> >> >>>>>>>> So, is there a better waveform to use at low frequencies? >> >>>>>>>> >> >>>>>>> >> >>>>>>> Hmmm. I get it now (though I don't get why this is a problem, >> >>>>>>> likely specific to your application). I don't know how one >> >>>>>>> waveform would be better for you that another, don't know >> >>>>>>> what it is you are doing (perhaps you said and I missed it, >> >>>>>>> I am not following closely). >> >>>>>>> A pretty complex way of dealing with the steps at low frequencies >> >>>>>>> is perhaps to have two DACs, one of them making the output filter >> >>>>>>> programmable so you can dynamically change it, based on step, >> >>>>>>> with some preemption etc., you get the idea - and I am not sure >> >>>>>>> it is practical, not only because it is complex but also because >> >>>>>>> I have never done this, I am just musing. >> >>>>>> >> >>>>>> I missed the "we step slowly" in your post, now I get it. >> >>>>>> Well, the simplest way out is to step at a constant rate all the >> >>>>>> time. >> >>>>> >> >>>>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That >> >>>>> needs a sine lookup table with about 50 billion entries. And an >> >>>>> equally impossible DAC and comparator. >> >>>>> >> >>>>> We'll probably wind up synthesizing the high range, an octave or so, >> >>>>> and divide down as needed. The trick will be to make the gear shifts >> >>>>> appear to be seamless. >> >>>>> >> >>>>> That could get interesting. >> >>>>> >> >>>> >> >>>>I still don't understand what you are trying to do. Periodic sine >> >>>>wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >> >>>>wave lookup table for the slowest case. If you want to switch by >> >>>>operator action you have milliseconds of time to recalculate the table. >> >>>>If you want to switch by some external gating you only need two >> >>>>tables to switch between, this makes up to 200 entries. >> >>>>This is all way too simple and obvious so you must be after something >> >>>>more than that - which I haven't got yet. >> >>> >> >>>I just want a programmable-frequency trigger generator that changes >> >>>frequency on demand and doesn't stop for reprogramming and doesn't >> >>>blow up someone's laser by generating any goofy triggers. In other >> >>>words, goes smoothly from F1 to F2. >> >>> >> >>>With low period jitter from, say, 1 mHz to 15 Mhz. >> >>> >> >>>mHz resolution is good too. >> >> >> >>I guess I'm not seeing the problem. Ordinary DDS units with 48-bit >> >>accumulators can do just this, with phase continuity between the two >> >>frequencies, so no glitches. People implement arbitrary >> >>frequency-keyed waveforms this way. >> >> >> >>The phase to trig converter typically uses only the upper 10 to 14 >> >>bits of the 48-bit accumulator. Converter implementations vary: >> >>table-lookup and CORDIC being very common approaches. >> >> >> > >> >One problem is that, at low frequencies, the LSB of that 10 to 14 bits >> >changes infrequently and the lowpass filter doesn't interpolate >> >multiple points any more. So one gets a lot of period jitter >> > >> >>Perhaps it's time to bring the various discussion threads together and >> >>re-focus by restating the problem to be solved. >> > >> >I've stated it a few times: We want a perfect, programmable, >> >glitch-free, always right, low period jitter trigger clock. >> > >> >It's an interesting problem. >> If all you want to do is to generate a trigger at any frequency from >> 10^-3 Hz to 15*10^6 Hz in 10^-3 Hz steps, that is easily done in a >> phase-only DDS topology (no trig conversion needed), which can be >> implemented directly in a FPGA. >> >> This is also known as a Numerically Controlled Oscillator: >> >> .<https://en.wikipedia.org/wiki/Numerically-controlled_oscillator> >> >> Our output would be point /M in Figure 1 in the above Wiki article. >> (Never mind that M is actually a bit width in that figure.) >> >> How big must the accumulator be? 15*10^6/10^-3 = 15*10^9 possible >> frequencies. Log2[ 15*10^9 ] = 33.8 bits. There was also talk of >> needing 50^10^9 steps, which would be 35.5 bits, minimum. In either >> case, a 48-bit accumulator will work with room to spare. >> >> If not, simply make the accumulator larger - 64 bits is also common. >> One can also choose the clock rate for convenience given the chosen >> accumulator length. >> >> The trigger signal is when the accumulator rolls over. If the > >did you miss the whole discussion? > >doing that with say a 100MHz clock give you 10ns jitter, which might be ok low frequency, but terrible at 15MHz > >The lowpass filter, between the DAC and the comparator, smooths the samples and reduces the jitter to picoseconds. https://www.dropbox.com/s/1xx7sz1e5rg6jsi/JLDDS_100M_4K.jpg?raw=1 The real jitter problem is at low frequencies where the filter doesn't help much. I was doodling a lowpass filter that is sort of adaptive, to help the low-end jitter. Mr Shannon was a nice guy, but we aren't trying to reproduce a signal, we just want to make a clock.
Reply by ●August 17, 20222022-08-17
On Wednesday, August 17, 2022 at 12:07:20 PM UTC-7, jla...@highlandsniptechnology.com wrote:> The real jitter problem is at low frequencies where the filter doesn't > help much. > > I was doodling a lowpass filter that is sort of adaptive, to help the > low-end jitter.By 'doodling', I trust you mean that the tracking filter isn't looking like a good solution.>Mr Shannon was a nice guy, but we aren't trying to > reproduce a signal, we just want to make a clock.Oh, no, you already HAVE a clock, what you want is a derived infinitely-adjustable variable clock based on that digital clock source. An easy way, is to use integer-ratio phase locking to the master clock to generate a digitally adjustable clock#2, for coarse adjustments, and use a sinewave variable oscillator (yeah, LC and varactor or moving parts) which can be metered by the master clock and fine-adjusted, then with a diode mixer combine the two. One discrete-time oscillator and one infinitely-adjustable oscillator, and a mixer. Follow up with an IF-style filter to make sinewaves, then amplifier to make 'em square. 'Tracking filter' functionality is exactly the LC oscillator feature that a totally digital system is missing, and gives you the ability to fill in the gaps in an N/M synthesis. Mr. Shannon assures us that there will be jitter, as does quantum mechanics, and thermodynamics. Making it small enough is your only option; frequency, for instance, is UNDEFINED mathematically, except for long time scales (it isn't just warmup time that makes a precise frequency measurement of long duration).
Reply by ●August 17, 20222022-08-17
onsdag den 17. august 2022 kl. 21.07.20 UTC+2 skrev jla...@highlandsniptechnology.com:> On Wed, 17 Aug 2022 11:15:06 -0700 (PDT), Lasse Langwadt Christensen > <lang...@fonz.dk> wrote: > > >onsdag den 17. august 2022 kl. 19.02.50 UTC+2 skrev Joe Gwinn: > >> On Tue, 16 Aug 2022 11:32:12 -0700, John Larkin > >> <jlarkin@highland_atwork_technology.com> wrote: > >> > >> >On Tue, 16 Aug 2022 13:46:32 -0400, Joe Gwinn <joeg...@comcast.net> > >> >wrote: > >> > > >> >>On Mon, 15 Aug 2022 19:26:28 -0700, jla...@highlandsniptechnology.com > >> >>wrote: > >> >> > >> >>>On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >> >>>wrote: > >> >>> > >> >>>>On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: > >> >>>>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >> >>>>> wrote: > >> >>>>> > >> >>>>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: > >> >>>>>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > >> >>>>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >> >>>>>>>> wrote: > >> >>>>>>>> > >> >>>>>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >> >>>>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen > >> >>>>>>>>>> <lang...@fonz.dk> wrote: > >> >>>>>>>>>> > >> >>>>>>>>>>> s?ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > >> >>>>>>>>>>>> It strikes me that John Larkin's original idea of synthesising > >> >>>>>>>>>>>> trapezoids can be made to work. > >> >>>>>>>>>>>> > >> >>>>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you > >> >>>>>>>>>>>> fed into your comparator would be made up of four sequential > >> >>>>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary > >> >>>>>>>>>>>> length, a falling edge, a low segment, and a risng edge > >> >>>>>>>>>>>> > >> >>>>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind > >> >>>>>>>>>>>> > >> >>>>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf > >> >>>>>>>>>>>> > >> >>>>>>>>>>>> > >> >>>>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as > >> >>>>>>>>>>>> 16-successive steps of a staircase waveform. > >> >>>>>>>>>>> > >> >>>>>>>>>>> since it is for a trigger and the falling edge probably doesn't > >> >>>>>>>>>>> matter, why not a single variable voltage step into a filter, sorta > >> >>>>>>>>>>> like a time-to-amplitude in reverse > >> >>>>>>>>>> > >> >>>>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform > >> >>>>>>>>>> to make a faster edge into a filter and comparator, to get better time > >> >>>>>>>>>> resolution, less jitter, at low frequencies. > >> >>>>>>>>> > >> >>>>>>>>> I am only curious if I understand what you are after - is it some sort > >> >>>>>>>>> of "the larger the step the less low pass I want applied to it"? > >> >>>>>>>> > >> >>>>>>>> When synthesizing a low frequency DDS sine wave, we step slowly > >> >>>>>>>> through the waveform lookup table and a fixed filter doesn't > >> >>>>>>>> interpolate waveform steps any more; it settles every step. > >> >>>>>>>> > >> >>>>>>>> So, is there a better waveform to use at low frequencies? > >> >>>>>>>> > >> >>>>>>> > >> >>>>>>> Hmmm. I get it now (though I don't get why this is a problem, > >> >>>>>>> likely specific to your application). I don't know how one > >> >>>>>>> waveform would be better for you that another, don't know > >> >>>>>>> what it is you are doing (perhaps you said and I missed it, > >> >>>>>>> I am not following closely). > >> >>>>>>> A pretty complex way of dealing with the steps at low frequencies > >> >>>>>>> is perhaps to have two DACs, one of them making the output filter > >> >>>>>>> programmable so you can dynamically change it, based on step, > >> >>>>>>> with some preemption etc., you get the idea - and I am not sure > >> >>>>>>> it is practical, not only because it is complex but also because > >> >>>>>>> I have never done this, I am just musing. > >> >>>>>> > >> >>>>>> I missed the "we step slowly" in your post, now I get it. > >> >>>>>> Well, the simplest way out is to step at a constant rate all the > >> >>>>>> time. > >> >>>>> > >> >>>>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > >> >>>>> needs a sine lookup table with about 50 billion entries. And an > >> >>>>> equally impossible DAC and comparator. > >> >>>>> > >> >>>>> We'll probably wind up synthesizing the high range, an octave or so, > >> >>>>> and divide down as needed. The trick will be to make the gear shifts > >> >>>>> appear to be seamless. > >> >>>>> > >> >>>>> That could get interesting. > >> >>>>> > >> >>>> > >> >>>>I still don't understand what you are trying to do. Periodic sine > >> >>>>wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > >> >>>>wave lookup table for the slowest case. If you want to switch by > >> >>>>operator action you have milliseconds of time to recalculate the table. > >> >>>>If you want to switch by some external gating you only need two > >> >>>>tables to switch between, this makes up to 200 entries. > >> >>>>This is all way too simple and obvious so you must be after something > >> >>>>more than that - which I haven't got yet. > >> >>> > >> >>>I just want a programmable-frequency trigger generator that changes > >> >>>frequency on demand and doesn't stop for reprogramming and doesn't > >> >>>blow up someone's laser by generating any goofy triggers. In other > >> >>>words, goes smoothly from F1 to F2. > >> >>> > >> >>>With low period jitter from, say, 1 mHz to 15 Mhz. > >> >>> > >> >>>mHz resolution is good too. > >> >> > >> >>I guess I'm not seeing the problem. Ordinary DDS units with 48-bit > >> >>accumulators can do just this, with phase continuity between the two > >> >>frequencies, so no glitches. People implement arbitrary > >> >>frequency-keyed waveforms this way. > >> >> > >> >>The phase to trig converter typically uses only the upper 10 to 14 > >> >>bits of the 48-bit accumulator. Converter implementations vary: > >> >>table-lookup and CORDIC being very common approaches. > >> >> > >> > > >> >One problem is that, at low frequencies, the LSB of that 10 to 14 bits > >> >changes infrequently and the lowpass filter doesn't interpolate > >> >multiple points any more. So one gets a lot of period jitter > >> > > >> >>Perhaps it's time to bring the various discussion threads together and > >> >>re-focus by restating the problem to be solved. > >> > > >> >I've stated it a few times: We want a perfect, programmable, > >> >glitch-free, always right, low period jitter trigger clock. > >> > > >> >It's an interesting problem. > >> If all you want to do is to generate a trigger at any frequency from > >> 10^-3 Hz to 15*10^6 Hz in 10^-3 Hz steps, that is easily done in a > >> phase-only DDS topology (no trig conversion needed), which can be > >> implemented directly in a FPGA. > >> > >> This is also known as a Numerically Controlled Oscillator: > >> > >> .<https://en.wikipedia.org/wiki/Numerically-controlled_oscillator> > >> > >> Our output would be point /M in Figure 1 in the above Wiki article. > >> (Never mind that M is actually a bit width in that figure.) > >> > >> How big must the accumulator be? 15*10^6/10^-3 = 15*10^9 possible > >> frequencies. Log2[ 15*10^9 ] = 33.8 bits. There was also talk of > >> needing 50^10^9 steps, which would be 35.5 bits, minimum. In either > >> case, a 48-bit accumulator will work with room to spare. > >> > >> If not, simply make the accumulator larger - 64 bits is also common. > >> One can also choose the clock rate for convenience given the chosen > >> accumulator length. > >> > >> The trigger signal is when the accumulator rolls over. If the > > > >did you miss the whole discussion? > > > >doing that with say a 100MHz clock give you 10ns jitter, which might be ok low frequency, but terrible at 15MHz > > > > > The lowpass filter, between the DAC and the comparator, smooths the > samples and reduces the jitter to picoseconds.sure but not if you make the square wave directly from the MSB of the accumulator with no DAC> https://www.dropbox.com/s/1xx7sz1e5rg6jsi/JLDDS_100M_4K.jpg?raw=1 > > The real jitter problem is at low frequencies where the filter doesn't > help much.you could also question how much 10ns of jitter matters on a 1Hz signal, it's 10ppb how accurate is the oscillator over a second?
Reply by ●August 17, 20222022-08-17
On Wed, 17 Aug 2022 13:26:53 -0700 (PDT), whit3rd <whit3rd@gmail.com> wrote:>On Wednesday, August 17, 2022 at 12:07:20 PM UTC-7, jla...@highlandsniptechnology.com wrote: > >> The real jitter problem is at low frequencies where the filter doesn't >> help much. >> >> I was doodling a lowpass filter that is sort of adaptive, to help the >> low-end jitter. > >By 'doodling', I trust you mean that the tracking filter isn't looking >like a good solution.Thinking is not a bad thing to do now and then. And I said adaptive, not tracking. I'd have to simulate it to see if it's worth doing, and what the side effects might be.> >>Mr Shannon was a nice guy, but we aren't trying to >> reproduce a signal, we just want to make a clock. > >Oh, no, you already HAVE a clock, what you want is a derived >infinitely-adjustable variable clock based on that digital clock source. > >An easy way, is to use integer-ratio phase locking to >the master clock to generate a digitally adjustable clock#2, >for coarse adjustments, and use a sinewave variable oscillator >(yeah, LC and varactor or moving parts) which can be metered by the master clock >and fine-adjusted, then with a diode mixer combine the two. > >One discrete-time oscillator and one infinitely-adjustable oscillator, and a mixer. >Follow up with an IF-style filter to make sinewaves, then amplifier to make 'em square. >'Tracking filter' functionality is exactly the LC oscillator feature that a totally digital >system is missing, and gives you the ability to fill in the gaps in an N/M synthesis. > >Mr. Shannon assures us that there will be jitter,The Sampling Theorem describes a sampled system that perfectly reproduces its input. No time delay even. https://en.wikipedia.org/wiki/Nyquist%E2%80%93Shannon_sampling_theorem Someone noted that most of the great Nobel scientists at Bell Labs had one thing in common: they ate lunch with Harry Nyquist.
