On Wed, 17 Aug 2022 12:07:09 -0700, jlarkin@highlandsniptechnology.com wrote:>On Wed, 17 Aug 2022 11:15:06 -0700 (PDT), Lasse Langwadt Christensen ><langwadt@fonz.dk> wrote: > >>onsdag den 17. august 2022 kl. 19.02.50 UTC+2 skrev Joe Gwinn: >>> On Tue, 16 Aug 2022 11:32:12 -0700, John Larkin >>> <jlarkin@highland_atwork_technology.com> wrote: >>> >>> >On Tue, 16 Aug 2022 13:46:32 -0400, Joe Gwinn <joeg...@comcast.net> >>> >wrote: >>> > >>> >>On Mon, 15 Aug 2022 19:26:28 -0700, jla...@highlandsniptechnology.com >>> >>wrote: >>> >> >>> >>>On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <d...@tgi-sci.com> >>> >>>wrote: >>> >>> >>> >>>>On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: >>> >>>>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> >>> >>>>> wrote: >>> >>>>> >>> >>>>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: >>> >>>>>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: >>> >>>>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> >>> >>>>>>>> wrote: >>> >>>>>>>> >>> >>>>>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: >>> >>>>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >>> >>>>>>>>>> <lang...@fonz.dk> wrote: >>> >>>>>>>>>> >>> >>>>>>>>>>> s?ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >>> >>>>>>>>>>>> It strikes me that John Larkin's original idea of synthesising >>> >>>>>>>>>>>> trapezoids can be made to work. >>> >>>>>>>>>>>> >>> >>>>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you >>> >>>>>>>>>>>> fed into your comparator would be made up of four sequential >>> >>>>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary >>> >>>>>>>>>>>> length, a falling edge, a low segment, and a risng edge >>> >>>>>>>>>>>> >>> >>>>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind >>> >>>>>>>>>>>> >>> >>>>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >>> >>>>>>>>>>>> >>> >>>>>>>>>>>> >>> >>>>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as >>> >>>>>>>>>>>> 16-successive steps of a staircase waveform. >>> >>>>>>>>>>> >>> >>>>>>>>>>> since it is for a trigger and the falling edge probably doesn't >>> >>>>>>>>>>> matter, why not a single variable voltage step into a filter, sorta >>> >>>>>>>>>>> like a time-to-amplitude in reverse >>> >>>>>>>>>> >>> >>>>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform >>> >>>>>>>>>> to make a faster edge into a filter and comparator, to get better time >>> >>>>>>>>>> resolution, less jitter, at low frequencies. >>> >>>>>>>>> >>> >>>>>>>>> I am only curious if I understand what you are after - is it some sort >>> >>>>>>>>> of "the larger the step the less low pass I want applied to it"? >>> >>>>>>>> >>> >>>>>>>> When synthesizing a low frequency DDS sine wave, we step slowly >>> >>>>>>>> through the waveform lookup table and a fixed filter doesn't >>> >>>>>>>> interpolate waveform steps any more; it settles every step. >>> >>>>>>>> >>> >>>>>>>> So, is there a better waveform to use at low frequencies? >>> >>>>>>>> >>> >>>>>>> >>> >>>>>>> Hmmm. I get it now (though I don't get why this is a problem, >>> >>>>>>> likely specific to your application). I don't know how one >>> >>>>>>> waveform would be better for you that another, don't know >>> >>>>>>> what it is you are doing (perhaps you said and I missed it, >>> >>>>>>> I am not following closely). >>> >>>>>>> A pretty complex way of dealing with the steps at low frequencies >>> >>>>>>> is perhaps to have two DACs, one of them making the output filter >>> >>>>>>> programmable so you can dynamically change it, based on step, >>> >>>>>>> with some preemption etc., you get the idea - and I am not sure >>> >>>>>>> it is practical, not only because it is complex but also because >>> >>>>>>> I have never done this, I am just musing. >>> >>>>>> >>> >>>>>> I missed the "we step slowly" in your post, now I get it. >>> >>>>>> Well, the simplest way out is to step at a constant rate all the >>> >>>>>> time. >>> >>>>> >>> >>>>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That >>> >>>>> needs a sine lookup table with about 50 billion entries. And an >>> >>>>> equally impossible DAC and comparator. >>> >>>>> >>> >>>>> We'll probably wind up synthesizing the high range, an octave or so, >>> >>>>> and divide down as needed. The trick will be to make the gear shifts >>> >>>>> appear to be seamless. >>> >>>>> >>> >>>>> That could get interesting. >>> >>>>> >>> >>>> >>> >>>>I still don't understand what you are trying to do. Periodic sine >>> >>>>wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >>> >>>>wave lookup table for the slowest case. If you want to switch by >>> >>>>operator action you have milliseconds of time to recalculate the table. >>> >>>>If you want to switch by some external gating you only need two >>> >>>>tables to switch between, this makes up to 200 entries. >>> >>>>This is all way too simple and obvious so you must be after something >>> >>>>more than that - which I haven't got yet. >>> >>> >>> >>>I just want a programmable-frequency trigger generator that changes >>> >>>frequency on demand and doesn't stop for reprogramming and doesn't >>> >>>blow up someone's laser by generating any goofy triggers. In other >>> >>>words, goes smoothly from F1 to F2. >>> >>> >>> >>>With low period jitter from, say, 1 mHz to 15 Mhz. >>> >>> >>> >>>mHz resolution is good too. >>> >> >>> >>I guess I'm not seeing the problem. Ordinary DDS units with 48-bit >>> >>accumulators can do just this, with phase continuity between the two >>> >>frequencies, so no glitches. People implement arbitrary >>> >>frequency-keyed waveforms this way. >>> >> >>> >>The phase to trig converter typically uses only the upper 10 to 14 >>> >>bits of the 48-bit accumulator. Converter implementations vary: >>> >>table-lookup and CORDIC being very common approaches. >>> >> >>> > >>> >One problem is that, at low frequencies, the LSB of that 10 to 14 bits >>> >changes infrequently and the lowpass filter doesn't interpolate >>> >multiple points any more. So one gets a lot of period jitter >>> > >>> >>Perhaps it's time to bring the various discussion threads together and >>> >>re-focus by restating the problem to be solved. >>> > >>> >I've stated it a few times: We want a perfect, programmable, >>> >glitch-free, always right, low period jitter trigger clock. >>> > >>> >It's an interesting problem. >>> If all you want to do is to generate a trigger at any frequency from >>> 10^-3 Hz to 15*10^6 Hz in 10^-3 Hz steps, that is easily done in a >>> phase-only DDS topology (no trig conversion needed), which can be >>> implemented directly in a FPGA. >>> >>> This is also known as a Numerically Controlled Oscillator: >>> >>> .<https://en.wikipedia.org/wiki/Numerically-controlled_oscillator> >>> >>> Our output would be point /M in Figure 1 in the above Wiki article. >>> (Never mind that M is actually a bit width in that figure.) >>> >>> How big must the accumulator be? 15*10^6/10^-3 = 15*10^9 possible >>> frequencies. Log2[ 15*10^9 ] = 33.8 bits. There was also talk of >>> needing 50^10^9 steps, which would be 35.5 bits, minimum. In either >>> case, a 48-bit accumulator will work with room to spare. >>> >>> If not, simply make the accumulator larger - 64 bits is also common. >>> One can also choose the clock rate for convenience given the chosen >>> accumulator length. >>> >>> The trigger signal is when the accumulator rolls over. If the >> >>did you miss the whole discussion?In a sense, yes. Thus the call for a re-baseline.>>doing that with say a 100MHz clock give you 10ns jitter, which might be ok low frequency, but terrible at 15MHz >> >> > >The lowpass filter, between the DAC and the comparator, smooths the >samples and reduces the jitter to picoseconds. > >https://www.dropbox.com/s/1xx7sz1e5rg6jsi/JLDDS_100M_4K.jpg?raw=1 > >The real jitter problem is at low frequencies where the filter doesn't >help much. > >I was doodling a lowpass filter that is sort of adaptive, to help the >low-end jitter. Mr Shannon was a nice guy, but we aren't trying to >reproduce a signal, we just want to make a clock.Well, I didn't mention it, but there are some classic dodges: Pre-packaged full DDS units are made to fit presumed markets, and may not fit the uncommon requirement. But if one implements the NCO plus sinus conversion in a FPGA and uses the output to drive a ADC chip, it's easy to get many more bits of analog width. First is to use a wider DAC to convert phase to sinus voltage; this will smooth the jaggies at 15 MHz (which is pretty slow by current DAC standards. Second is to have two paths in parallel, we'll call them fast and slow, with their analog outputs combined by means of a crossover network of some kind. Third is to multiply the 200 MHz up to say 800 MHz, limited only by the FPGA. Or some combination of all above. Joe Gwinn
Direct digital synthesis of square waves
Started by ●August 14, 2022
Reply by ●August 17, 20222022-08-17
Reply by ●August 17, 20222022-08-17
On Wed, 17 Aug 2022 14:03:36 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>onsdag den 17. august 2022 kl. 21.07.20 UTC+2 skrev jla...@highlandsniptechnology.com: >> On Wed, 17 Aug 2022 11:15:06 -0700 (PDT), Lasse Langwadt Christensen >> <lang...@fonz.dk> wrote: >> >> >onsdag den 17. august 2022 kl. 19.02.50 UTC+2 skrev Joe Gwinn: >> >> On Tue, 16 Aug 2022 11:32:12 -0700, John Larkin >> >> <jlarkin@highland_atwork_technology.com> wrote: >> >> >> >> >On Tue, 16 Aug 2022 13:46:32 -0400, Joe Gwinn <joeg...@comcast.net> >> >> >wrote: >> >> > >> >> >>On Mon, 15 Aug 2022 19:26:28 -0700, jla...@highlandsniptechnology.com >> >> >>wrote: >> >> >> >> >> >>>On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <d...@tgi-sci.com> >> >> >>>wrote: >> >> >>> >> >> >>>>On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: >> >> >>>>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> >> >> >>>>> wrote: >> >> >>>>> >> >> >>>>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: >> >> >>>>>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: >> >> >>>>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> >> >> >>>>>>>> wrote: >> >> >>>>>>>> >> >> >>>>>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: >> >> >>>>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >> >> >>>>>>>>>> <lang...@fonz.dk> wrote: >> >> >>>>>>>>>> >> >> >>>>>>>>>>> s?ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >> >> >>>>>>>>>>>> It strikes me that John Larkin's original idea of synthesising >> >> >>>>>>>>>>>> trapezoids can be made to work. >> >> >>>>>>>>>>>> >> >> >>>>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you >> >> >>>>>>>>>>>> fed into your comparator would be made up of four sequential >> >> >>>>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary >> >> >>>>>>>>>>>> length, a falling edge, a low segment, and a risng edge >> >> >>>>>>>>>>>> >> >> >>>>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind >> >> >>>>>>>>>>>> >> >> >>>>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >> >> >>>>>>>>>>>> >> >> >>>>>>>>>>>> >> >> >>>>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as >> >> >>>>>>>>>>>> 16-successive steps of a staircase waveform. >> >> >>>>>>>>>>> >> >> >>>>>>>>>>> since it is for a trigger and the falling edge probably doesn't >> >> >>>>>>>>>>> matter, why not a single variable voltage step into a filter, sorta >> >> >>>>>>>>>>> like a time-to-amplitude in reverse >> >> >>>>>>>>>> >> >> >>>>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform >> >> >>>>>>>>>> to make a faster edge into a filter and comparator, to get better time >> >> >>>>>>>>>> resolution, less jitter, at low frequencies. >> >> >>>>>>>>> >> >> >>>>>>>>> I am only curious if I understand what you are after - is it some sort >> >> >>>>>>>>> of "the larger the step the less low pass I want applied to it"? >> >> >>>>>>>> >> >> >>>>>>>> When synthesizing a low frequency DDS sine wave, we step slowly >> >> >>>>>>>> through the waveform lookup table and a fixed filter doesn't >> >> >>>>>>>> interpolate waveform steps any more; it settles every step. >> >> >>>>>>>> >> >> >>>>>>>> So, is there a better waveform to use at low frequencies? >> >> >>>>>>>> >> >> >>>>>>> >> >> >>>>>>> Hmmm. I get it now (though I don't get why this is a problem, >> >> >>>>>>> likely specific to your application). I don't know how one >> >> >>>>>>> waveform would be better for you that another, don't know >> >> >>>>>>> what it is you are doing (perhaps you said and I missed it, >> >> >>>>>>> I am not following closely). >> >> >>>>>>> A pretty complex way of dealing with the steps at low frequencies >> >> >>>>>>> is perhaps to have two DACs, one of them making the output filter >> >> >>>>>>> programmable so you can dynamically change it, based on step, >> >> >>>>>>> with some preemption etc., you get the idea - and I am not sure >> >> >>>>>>> it is practical, not only because it is complex but also because >> >> >>>>>>> I have never done this, I am just musing. >> >> >>>>>> >> >> >>>>>> I missed the "we step slowly" in your post, now I get it. >> >> >>>>>> Well, the simplest way out is to step at a constant rate all the >> >> >>>>>> time. >> >> >>>>> >> >> >>>>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That >> >> >>>>> needs a sine lookup table with about 50 billion entries. And an >> >> >>>>> equally impossible DAC and comparator. >> >> >>>>> >> >> >>>>> We'll probably wind up synthesizing the high range, an octave or so, >> >> >>>>> and divide down as needed. The trick will be to make the gear shifts >> >> >>>>> appear to be seamless. >> >> >>>>> >> >> >>>>> That could get interesting. >> >> >>>>> >> >> >>>> >> >> >>>>I still don't understand what you are trying to do. Periodic sine >> >> >>>>wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >> >> >>>>wave lookup table for the slowest case. If you want to switch by >> >> >>>>operator action you have milliseconds of time to recalculate the table. >> >> >>>>If you want to switch by some external gating you only need two >> >> >>>>tables to switch between, this makes up to 200 entries. >> >> >>>>This is all way too simple and obvious so you must be after something >> >> >>>>more than that - which I haven't got yet. >> >> >>> >> >> >>>I just want a programmable-frequency trigger generator that changes >> >> >>>frequency on demand and doesn't stop for reprogramming and doesn't >> >> >>>blow up someone's laser by generating any goofy triggers. In other >> >> >>>words, goes smoothly from F1 to F2. >> >> >>> >> >> >>>With low period jitter from, say, 1 mHz to 15 Mhz. >> >> >>> >> >> >>>mHz resolution is good too. >> >> >> >> >> >>I guess I'm not seeing the problem. Ordinary DDS units with 48-bit >> >> >>accumulators can do just this, with phase continuity between the two >> >> >>frequencies, so no glitches. People implement arbitrary >> >> >>frequency-keyed waveforms this way. >> >> >> >> >> >>The phase to trig converter typically uses only the upper 10 to 14 >> >> >>bits of the 48-bit accumulator. Converter implementations vary: >> >> >>table-lookup and CORDIC being very common approaches. >> >> >> >> >> > >> >> >One problem is that, at low frequencies, the LSB of that 10 to 14 bits >> >> >changes infrequently and the lowpass filter doesn't interpolate >> >> >multiple points any more. So one gets a lot of period jitter >> >> > >> >> >>Perhaps it's time to bring the various discussion threads together and >> >> >>re-focus by restating the problem to be solved. >> >> > >> >> >I've stated it a few times: We want a perfect, programmable, >> >> >glitch-free, always right, low period jitter trigger clock. >> >> > >> >> >It's an interesting problem. >> >> If all you want to do is to generate a trigger at any frequency from >> >> 10^-3 Hz to 15*10^6 Hz in 10^-3 Hz steps, that is easily done in a >> >> phase-only DDS topology (no trig conversion needed), which can be >> >> implemented directly in a FPGA. >> >> >> >> This is also known as a Numerically Controlled Oscillator: >> >> >> >> .<https://en.wikipedia.org/wiki/Numerically-controlled_oscillator> >> >> >> >> Our output would be point /M in Figure 1 in the above Wiki article. >> >> (Never mind that M is actually a bit width in that figure.) >> >> >> >> How big must the accumulator be? 15*10^6/10^-3 = 15*10^9 possible >> >> frequencies. Log2[ 15*10^9 ] = 33.8 bits. There was also talk of >> >> needing 50^10^9 steps, which would be 35.5 bits, minimum. In either >> >> case, a 48-bit accumulator will work with room to spare. >> >> >> >> If not, simply make the accumulator larger - 64 bits is also common. >> >> One can also choose the clock rate for convenience given the chosen >> >> accumulator length. >> >> >> >> The trigger signal is when the accumulator rolls over. If the >> > >> >did you miss the whole discussion? >> > >> >doing that with say a 100MHz clock give you 10ns jitter, which might be ok low frequency, but terrible at 15MHz >> > >> > >> The lowpass filter, between the DAC and the comparator, smooths the >> samples and reduces the jitter to picoseconds. > >sure but not if you make the square wave directly from the MSB of the accumulator with no DACThe phase accumulator MSB is pretty good at low frequencies and hideous at high frequencies. Possibly we can make a reasonably clean transition from sinewave DDS to MSB only at some frequency.> >> https://www.dropbox.com/s/1xx7sz1e5rg6jsi/JLDDS_100M_4K.jpg?raw=1 >> >> The real jitter problem is at low frequencies where the filter doesn't >> help much. > >you could also question how much 10ns of jitter matters on a 1Hz signal, it's 10ppb >how accurate is the oscillator over a second?1 PPM RMS jitter would be OK. We're redesigning a product, and the old one uses an ADI spi-interface DDS chip that has horrible jitter at low frequencies, something like 100 PPM. A customer can program it high and kick in a divisor, which reduces jitter radically, but the transition to a new frequency is messy and some people whine about blown-up lasers or something silly like that. Our XO can be locked to a better oscillator, and we have an internal OCXO option. Only a few per cent of our sales have the OCXO. http://www.highlandtechnology.com/DSS/T564DS.shtml It's pretty good, but I want to make it better next rev. Prettier too.
Reply by ●August 17, 20222022-08-17
onsdag den 17. august 2022 kl. 23.49.21 UTC+2 skrev jla...@highlandsniptechnology.com:> On Wed, 17 Aug 2022 14:03:36 -0700 (PDT), Lasse Langwadt Christensen > <lang...@fonz.dk> wrote: > > >onsdag den 17. august 2022 kl. 21.07.20 UTC+2 skrev jla...@highlandsniptechnology.com: > >> On Wed, 17 Aug 2022 11:15:06 -0700 (PDT), Lasse Langwadt Christensen > >> <lang...@fonz.dk> wrote: > >> > >> >onsdag den 17. august 2022 kl. 19.02.50 UTC+2 skrev Joe Gwinn: > >> >> On Tue, 16 Aug 2022 11:32:12 -0700, John Larkin > >> >> <jlarkin@highland_atwork_technology.com> wrote: > >> >> > >> >> >On Tue, 16 Aug 2022 13:46:32 -0400, Joe Gwinn <joeg...@comcast.net> > >> >> >wrote: > >> >> > > >> >> >>On Mon, 15 Aug 2022 19:26:28 -0700, jla...@highlandsniptechnology.com > >> >> >>wrote: > >> >> >> > >> >> >>>On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >> >> >>>wrote: > >> >> >>> > >> >> >>>>On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: > >> >> >>>>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >> >> >>>>> wrote: > >> >> >>>>> > >> >> >>>>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: > >> >> >>>>>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > >> >> >>>>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >> >> >>>>>>>> wrote: > >> >> >>>>>>>> > >> >> >>>>>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >> >> >>>>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen > >> >> >>>>>>>>>> <lang...@fonz.dk> wrote: > >> >> >>>>>>>>>> > >> >> >>>>>>>>>>> s?ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > >> >> >>>>>>>>>>>> It strikes me that John Larkin's original idea of synthesising > >> >> >>>>>>>>>>>> trapezoids can be made to work. > >> >> >>>>>>>>>>>> > >> >> >>>>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you > >> >> >>>>>>>>>>>> fed into your comparator would be made up of four sequential > >> >> >>>>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary > >> >> >>>>>>>>>>>> length, a falling edge, a low segment, and a risng edge > >> >> >>>>>>>>>>>> > >> >> >>>>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind > >> >> >>>>>>>>>>>> > >> >> >>>>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf > >> >> >>>>>>>>>>>> > >> >> >>>>>>>>>>>> > >> >> >>>>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as > >> >> >>>>>>>>>>>> 16-successive steps of a staircase waveform. > >> >> >>>>>>>>>>> > >> >> >>>>>>>>>>> since it is for a trigger and the falling edge probably doesn't > >> >> >>>>>>>>>>> matter, why not a single variable voltage step into a filter, sorta > >> >> >>>>>>>>>>> like a time-to-amplitude in reverse > >> >> >>>>>>>>>> > >> >> >>>>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform > >> >> >>>>>>>>>> to make a faster edge into a filter and comparator, to get better time > >> >> >>>>>>>>>> resolution, less jitter, at low frequencies. > >> >> >>>>>>>>> > >> >> >>>>>>>>> I am only curious if I understand what you are after - is it some sort > >> >> >>>>>>>>> of "the larger the step the less low pass I want applied to it"? > >> >> >>>>>>>> > >> >> >>>>>>>> When synthesizing a low frequency DDS sine wave, we step slowly > >> >> >>>>>>>> through the waveform lookup table and a fixed filter doesn't > >> >> >>>>>>>> interpolate waveform steps any more; it settles every step. > >> >> >>>>>>>> > >> >> >>>>>>>> So, is there a better waveform to use at low frequencies? > >> >> >>>>>>>> > >> >> >>>>>>> > >> >> >>>>>>> Hmmm. I get it now (though I don't get why this is a problem, > >> >> >>>>>>> likely specific to your application). I don't know how one > >> >> >>>>>>> waveform would be better for you that another, don't know > >> >> >>>>>>> what it is you are doing (perhaps you said and I missed it, > >> >> >>>>>>> I am not following closely). > >> >> >>>>>>> A pretty complex way of dealing with the steps at low frequencies > >> >> >>>>>>> is perhaps to have two DACs, one of them making the output filter > >> >> >>>>>>> programmable so you can dynamically change it, based on step, > >> >> >>>>>>> with some preemption etc., you get the idea - and I am not sure > >> >> >>>>>>> it is practical, not only because it is complex but also because > >> >> >>>>>>> I have never done this, I am just musing. > >> >> >>>>>> > >> >> >>>>>> I missed the "we step slowly" in your post, now I get it. > >> >> >>>>>> Well, the simplest way out is to step at a constant rate all the > >> >> >>>>>> time. > >> >> >>>>> > >> >> >>>>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > >> >> >>>>> needs a sine lookup table with about 50 billion entries. And an > >> >> >>>>> equally impossible DAC and comparator. > >> >> >>>>> > >> >> >>>>> We'll probably wind up synthesizing the high range, an octave or so, > >> >> >>>>> and divide down as needed. The trick will be to make the gear shifts > >> >> >>>>> appear to be seamless. > >> >> >>>>> > >> >> >>>>> That could get interesting. > >> >> >>>>> > >> >> >>>> > >> >> >>>>I still don't understand what you are trying to do. Periodic sine > >> >> >>>>wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > >> >> >>>>wave lookup table for the slowest case. If you want to switch by > >> >> >>>>operator action you have milliseconds of time to recalculate the table. > >> >> >>>>If you want to switch by some external gating you only need two > >> >> >>>>tables to switch between, this makes up to 200 entries. > >> >> >>>>This is all way too simple and obvious so you must be after something > >> >> >>>>more than that - which I haven't got yet. > >> >> >>> > >> >> >>>I just want a programmable-frequency trigger generator that changes > >> >> >>>frequency on demand and doesn't stop for reprogramming and doesn't > >> >> >>>blow up someone's laser by generating any goofy triggers. In other > >> >> >>>words, goes smoothly from F1 to F2. > >> >> >>> > >> >> >>>With low period jitter from, say, 1 mHz to 15 Mhz. > >> >> >>> > >> >> >>>mHz resolution is good too. > >> >> >> > >> >> >>I guess I'm not seeing the problem. Ordinary DDS units with 48-bit > >> >> >>accumulators can do just this, with phase continuity between the two > >> >> >>frequencies, so no glitches. People implement arbitrary > >> >> >>frequency-keyed waveforms this way. > >> >> >> > >> >> >>The phase to trig converter typically uses only the upper 10 to 14 > >> >> >>bits of the 48-bit accumulator. Converter implementations vary: > >> >> >>table-lookup and CORDIC being very common approaches. > >> >> >> > >> >> > > >> >> >One problem is that, at low frequencies, the LSB of that 10 to 14 bits > >> >> >changes infrequently and the lowpass filter doesn't interpolate > >> >> >multiple points any more. So one gets a lot of period jitter > >> >> > > >> >> >>Perhaps it's time to bring the various discussion threads together and > >> >> >>re-focus by restating the problem to be solved. > >> >> > > >> >> >I've stated it a few times: We want a perfect, programmable, > >> >> >glitch-free, always right, low period jitter trigger clock. > >> >> > > >> >> >It's an interesting problem. > >> >> If all you want to do is to generate a trigger at any frequency from > >> >> 10^-3 Hz to 15*10^6 Hz in 10^-3 Hz steps, that is easily done in a > >> >> phase-only DDS topology (no trig conversion needed), which can be > >> >> implemented directly in a FPGA. > >> >> > >> >> This is also known as a Numerically Controlled Oscillator: > >> >> > >> >> .<https://en.wikipedia.org/wiki/Numerically-controlled_oscillator> > >> >> > >> >> Our output would be point /M in Figure 1 in the above Wiki article. > >> >> (Never mind that M is actually a bit width in that figure.) > >> >> > >> >> How big must the accumulator be? 15*10^6/10^-3 = 15*10^9 possible > >> >> frequencies. Log2[ 15*10^9 ] = 33.8 bits. There was also talk of > >> >> needing 50^10^9 steps, which would be 35.5 bits, minimum. In either > >> >> case, a 48-bit accumulator will work with room to spare. > >> >> > >> >> If not, simply make the accumulator larger - 64 bits is also common. > >> >> One can also choose the clock rate for convenience given the chosen > >> >> accumulator length. > >> >> > >> >> The trigger signal is when the accumulator rolls over. If the > >> > > >> >did you miss the whole discussion? > >> > > >> >doing that with say a 100MHz clock give you 10ns jitter, which might be ok low frequency, but terrible at 15MHz > >> > > >> > > >> The lowpass filter, between the DAC and the comparator, smooths the > >> samples and reduces the jitter to picoseconds. > > > >sure but not if you make the square wave directly from the MSB of the accumulator with no DAC > The phase accumulator MSB is pretty good at low frequencies and > hideous at high frequencies. Possibly we can make a reasonably clean > transition from sinewave DDS to MSB only at some frequency.just add a frequency dependent gain so the the slew rate stays roughly the same, then there is no transition
Reply by ●August 17, 20222022-08-17
On 8/16/2022 20:13, John Larkin wrote:> On Tue, 16 Aug 2022 19:51:04 +0300, Dimiter_Popoff <dp@tgi-sci.com> > wrote: > >> On 8/16/2022 17:02, jlarkin@highlandsniptechnology.com wrote: >>> On Tue, 16 Aug 2022 15:44:27 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>> wrote: >>> >>>> On 8/16/2022 3:23, John Larkin wrote: >>>>> On Mon, 15 Aug 2022 16:45:18 -0700 (PDT), whit3rd <whit3rd@gmail.com> >>>>> wrote: >>>>> >>>>>> On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote: >>>>>>> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: >>>>>>>> mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff: >>>>>> >>>>>>>>> I still don't understand what you are trying to do. Periodic sine >>>>>>>>> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >>>>>>>>> wave lookup table for the slowest case. >>>>>>>> >>>>>>>> only if you want neat frequencies that add up to 100M >>>>>>>> >>>>>>> I don't understand what a neat frequency is, either. Any periodic >>>>>>> waveform at 1 MHz (the worst case) at 100 Msps update rate takes >>>>>>> a 100 entry table. >>>>>> >>>>>> But suppose you adjust to 0.99 MHz; do you now use a 101 entry table? >>>>>> And how about 0.995 MHz? >>>>>> The small-integer ratios for a given frequency don't support a fixed table >>>>>> size, and the 'update rate' might not be fine-adjustable enough. In contrast >>>>>> to a variable-LC tuning scheme, digital synthesis tables require... an exercise >>>>>> in ratios of integers to approximate a real number. >>>>> >>>>> With a DDS phase accumulator, the output frequency is >>>>> >>>>> Fxo * N / M >>>>> >>>>> where Fxo is the 100 MHz xtal oscillator >>>>> >>>>> N is the frequency set word >>>>> >>>>> M is the accumulator max count, say 2^48. >>>>> >>>>> Frequency set resolution would be below 1 uHz in this case. Just load >>>>> N. >>>>> >>>>> The sine lookup table is addressed by some number of MSBs of the phase >>>>> accumulator, 10 to 16 typically. It doesn't change in a given system. >>>>> >>>>> >>>>> >>>> >>>> Perhaps you could shorten the lookup table to some manageable size if >>>> you do lookup-and-interpolate. Will still be huge... And division >>>> at 100 Msps may well be prohibitive. >>> >>> Our FPGA will have at least a megabit of ram if we use the efinix, >>> lots more if we use the Zynq. A sine table can be folded 2:1 or 4:1, >>> so we can easily do 64K points of 16 bit data. >>> >>> One of my guys proposed an architecture that uses more bits of the >>> phase accumulator. A group of MS bits becomes the gate for a cluster >>> of LS bits. Envision a spinner dial that mostly parks at 0 degrees and >>> once in a while makes a single fast rotation. That essentially puts a >>> divisor *before* a cosine lookup table and DAC. >>> >>> Gotta simulate that somehow. >>> >>> >>> >> >> But if this is to be used as a trigger (similar to the sweep trigger >> on a scope, level knob etc.) can't you just do triangular instead of >> sine wave? Should even be better for that purpose - and no need for a >> lookup table at all... > > That has been considered. But Claude Shannon is the evil stepmother > lurking and plotting to keep us from living happily after. > > The sampling frequency is async to the trigger rate that we want, so > is a source of jitter. A triangle is not bandlimited to below the > Nyquist rate, and we can't afford an ideal lowpass filter either. >I still don't understand why someone would need sine wave for triggering rather than just some TTL or whatever pulse generator, you must have made dozens of these. Just dividing some low jitter oscillator is as trivial as it can get. But if it has to be sine wave well, things do get complicated. I anticipate once you have made that superb sine wave generator they will find out that noise or whatever is a source of some jitter to which the generator's will be negligible.... I don't know the application of course, this is how it looks to me at this point.
Reply by ●August 17, 20222022-08-17
torsdag den 18. august 2022 kl. 00.23.00 UTC+2 skrev Dimiter Popoff:> On 8/16/2022 20:13, John Larkin wrote: > > On Tue, 16 Aug 2022 19:51:04 +0300, Dimiter_Popoff <d...@tgi-sci.com> > > wrote: > > > >> On 8/16/2022 17:02, jla...@highlandsniptechnology.com wrote: > >>> On Tue, 16 Aug 2022 15:44:27 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>> wrote: > >>> > >>>> On 8/16/2022 3:23, John Larkin wrote: > >>>>> On Mon, 15 Aug 2022 16:45:18 -0700 (PDT), whit3rd <whi...@gmail.com> > >>>>> wrote: > >>>>> > >>>>>> On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote: > >>>>>>> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: > >>>>>>>> mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff: > >>>>>> > >>>>>>>>> I still don't understand what you are trying to do. Periodic sine > >>>>>>>>> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > >>>>>>>>> wave lookup table for the slowest case. > >>>>>>>> > >>>>>>>> only if you want neat frequencies that add up to 100M > >>>>>>>> > >>>>>>> I don't understand what a neat frequency is, either. Any periodic > >>>>>>> waveform at 1 MHz (the worst case) at 100 Msps update rate takes > >>>>>>> a 100 entry table. > >>>>>> > >>>>>> But suppose you adjust to 0.99 MHz; do you now use a 101 entry table? > >>>>>> And how about 0.995 MHz? > >>>>>> The small-integer ratios for a given frequency don't support a fixed table > >>>>>> size, and the 'update rate' might not be fine-adjustable enough. In contrast > >>>>>> to a variable-LC tuning scheme, digital synthesis tables require... an exercise > >>>>>> in ratios of integers to approximate a real number. > >>>>> > >>>>> With a DDS phase accumulator, the output frequency is > >>>>> > >>>>> Fxo * N / M > >>>>> > >>>>> where Fxo is the 100 MHz xtal oscillator > >>>>> > >>>>> N is the frequency set word > >>>>> > >>>>> M is the accumulator max count, say 2^48. > >>>>> > >>>>> Frequency set resolution would be below 1 uHz in this case. Just load > >>>>> N. > >>>>> > >>>>> The sine lookup table is addressed by some number of MSBs of the phase > >>>>> accumulator, 10 to 16 typically. It doesn't change in a given system. > >>>>> > >>>>> > >>>>> > >>>> > >>>> Perhaps you could shorten the lookup table to some manageable size if > >>>> you do lookup-and-interpolate. Will still be huge... And division > >>>> at 100 Msps may well be prohibitive. > >>> > >>> Our FPGA will have at least a megabit of ram if we use the efinix, > >>> lots more if we use the Zynq. A sine table can be folded 2:1 or 4:1, > >>> so we can easily do 64K points of 16 bit data. > >>> > >>> One of my guys proposed an architecture that uses more bits of the > >>> phase accumulator. A group of MS bits becomes the gate for a cluster > >>> of LS bits. Envision a spinner dial that mostly parks at 0 degrees and > >>> once in a while makes a single fast rotation. That essentially puts a > >>> divisor *before* a cosine lookup table and DAC. > >>> > >>> Gotta simulate that somehow. > >>> > >>> > >>> > >> > >> But if this is to be used as a trigger (similar to the sweep trigger > >> on a scope, level knob etc.) can't you just do triangular instead of > >> sine wave? Should even be better for that purpose - and no need for a > >> lookup table at all... > > > > That has been considered. But Claude Shannon is the evil stepmother > > lurking and plotting to keep us from living happily after. > > > > The sampling frequency is async to the trigger rate that we want, so > > is a source of jitter. A triangle is not bandlimited to below the > > Nyquist rate, and we can't afford an ideal lowpass filter either. > > > I still don't understand why someone would need sine wave for triggering > rather than just some TTL or whatever pulse generator, you must have > made dozens of these. Just dividing some low jitter oscillator is as > trivial as it can get. But if it has to be sine wave well, things do > get complicated. I anticipate once you have made that superb sine > wave generator they will find out that noise or whatever is a source > of some jitter to which the generator's will be negligible.... > I don't know the application of course, this is how it looks > to me at this point.try generating arbitrary frequencies that isn't necessarily a multiple of 10ns with a 100MHz clk with just a divider...
Reply by ●August 17, 20222022-08-17
On 8/18/2022 1:37, Lasse Langwadt Christensen wrote:> torsdag den 18. august 2022 kl. 00.23.00 UTC+2 skrev Dimiter Popoff: >> On 8/16/2022 20:13, John Larkin wrote: >>> On Tue, 16 Aug 2022 19:51:04 +0300, Dimiter_Popoff <d...@tgi-sci.com> >>> wrote: >>> >>>> On 8/16/2022 17:02, jla...@highlandsniptechnology.com wrote: >>>>> On Tue, 16 Aug 2022 15:44:27 +0300, Dimiter_Popoff <d...@tgi-sci.com> >>>>> wrote: >>>>> >>>>>> On 8/16/2022 3:23, John Larkin wrote: >>>>>>> On Mon, 15 Aug 2022 16:45:18 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>> wrote: >>>>>>> >>>>>>>> On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote: >>>>>>>>> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: >>>>>>>>>> mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff: >>>>>>>> >>>>>>>>>>> I still don't understand what you are trying to do. Periodic sine >>>>>>>>>>> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >>>>>>>>>>> wave lookup table for the slowest case. >>>>>>>>>> >>>>>>>>>> only if you want neat frequencies that add up to 100M >>>>>>>>>> >>>>>>>>> I don't understand what a neat frequency is, either. Any periodic >>>>>>>>> waveform at 1 MHz (the worst case) at 100 Msps update rate takes >>>>>>>>> a 100 entry table. >>>>>>>> >>>>>>>> But suppose you adjust to 0.99 MHz; do you now use a 101 entry table? >>>>>>>> And how about 0.995 MHz? >>>>>>>> The small-integer ratios for a given frequency don't support a fixed table >>>>>>>> size, and the 'update rate' might not be fine-adjustable enough. In contrast >>>>>>>> to a variable-LC tuning scheme, digital synthesis tables require... an exercise >>>>>>>> in ratios of integers to approximate a real number. >>>>>>> >>>>>>> With a DDS phase accumulator, the output frequency is >>>>>>> >>>>>>> Fxo * N / M >>>>>>> >>>>>>> where Fxo is the 100 MHz xtal oscillator >>>>>>> >>>>>>> N is the frequency set word >>>>>>> >>>>>>> M is the accumulator max count, say 2^48. >>>>>>> >>>>>>> Frequency set resolution would be below 1 uHz in this case. Just load >>>>>>> N. >>>>>>> >>>>>>> The sine lookup table is addressed by some number of MSBs of the phase >>>>>>> accumulator, 10 to 16 typically. It doesn't change in a given system. >>>>>>> >>>>>>> >>>>>>> >>>>>> >>>>>> Perhaps you could shorten the lookup table to some manageable size if >>>>>> you do lookup-and-interpolate. Will still be huge... And division >>>>>> at 100 Msps may well be prohibitive. >>>>> >>>>> Our FPGA will have at least a megabit of ram if we use the efinix, >>>>> lots more if we use the Zynq. A sine table can be folded 2:1 or 4:1, >>>>> so we can easily do 64K points of 16 bit data. >>>>> >>>>> One of my guys proposed an architecture that uses more bits of the >>>>> phase accumulator. A group of MS bits becomes the gate for a cluster >>>>> of LS bits. Envision a spinner dial that mostly parks at 0 degrees and >>>>> once in a while makes a single fast rotation. That essentially puts a >>>>> divisor *before* a cosine lookup table and DAC. >>>>> >>>>> Gotta simulate that somehow. >>>>> >>>>> >>>>> >>>> >>>> But if this is to be used as a trigger (similar to the sweep trigger >>>> on a scope, level knob etc.) can't you just do triangular instead of >>>> sine wave? Should even be better for that purpose - and no need for a >>>> lookup table at all... >>> >>> That has been considered. But Claude Shannon is the evil stepmother >>> lurking and plotting to keep us from living happily after. >>> >>> The sampling frequency is async to the trigger rate that we want, so >>> is a source of jitter. A triangle is not bandlimited to below the >>> Nyquist rate, and we can't afford an ideal lowpass filter either. >>> >> I still don't understand why someone would need sine wave for triggering >> rather than just some TTL or whatever pulse generator, you must have >> made dozens of these. Just dividing some low jitter oscillator is as >> trivial as it can get. But if it has to be sine wave well, things do >> get complicated. I anticipate once you have made that superb sine >> wave generator they will find out that noise or whatever is a source >> of some jitter to which the generator's will be negligible.... >> I don't know the application of course, this is how it looks >> to me at this point. > > try generating arbitrary frequencies that isn't necessarily a multiple of 10ns with a 100MHz clk > with just a divider...Obviously you can't do that, I am just wondering about the application that needs 10 seconds period with picoseconds of jitter. Or with a ns of jitter, for that. But other people asked about making sort of the same thing, clearly there is some demand.
Reply by ●August 17, 20222022-08-17
torsdag den 18. august 2022 kl. 01.11.22 UTC+2 skrev Dimiter Popoff:> On 8/18/2022 1:37, Lasse Langwadt Christensen wrote: > > torsdag den 18. august 2022 kl. 00.23.00 UTC+2 skrev Dimiter Popoff: > >> On 8/16/2022 20:13, John Larkin wrote: > >>> On Tue, 16 Aug 2022 19:51:04 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>> wrote: > >>> > >>>> On 8/16/2022 17:02, jla...@highlandsniptechnology.com wrote: > >>>>> On Tue, 16 Aug 2022 15:44:27 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>>>> wrote: > >>>>> > >>>>>> On 8/16/2022 3:23, John Larkin wrote: > >>>>>>> On Mon, 15 Aug 2022 16:45:18 -0700 (PDT), whit3rd <whi...@gmail.com> > >>>>>>> wrote: > >>>>>>> > >>>>>>>> On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote: > >>>>>>>>> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: > >>>>>>>>>> mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff: > >>>>>>>> > >>>>>>>>>>> I still don't understand what you are trying to do. Periodic sine > >>>>>>>>>>> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > >>>>>>>>>>> wave lookup table for the slowest case. > >>>>>>>>>> > >>>>>>>>>> only if you want neat frequencies that add up to 100M > >>>>>>>>>> > >>>>>>>>> I don't understand what a neat frequency is, either. Any periodic > >>>>>>>>> waveform at 1 MHz (the worst case) at 100 Msps update rate takes > >>>>>>>>> a 100 entry table. > >>>>>>>> > >>>>>>>> But suppose you adjust to 0.99 MHz; do you now use a 101 entry table? > >>>>>>>> And how about 0.995 MHz? > >>>>>>>> The small-integer ratios for a given frequency don't support a fixed table > >>>>>>>> size, and the 'update rate' might not be fine-adjustable enough. In contrast > >>>>>>>> to a variable-LC tuning scheme, digital synthesis tables require... an exercise > >>>>>>>> in ratios of integers to approximate a real number. > >>>>>>> > >>>>>>> With a DDS phase accumulator, the output frequency is > >>>>>>> > >>>>>>> Fxo * N / M > >>>>>>> > >>>>>>> where Fxo is the 100 MHz xtal oscillator > >>>>>>> > >>>>>>> N is the frequency set word > >>>>>>> > >>>>>>> M is the accumulator max count, say 2^48. > >>>>>>> > >>>>>>> Frequency set resolution would be below 1 uHz in this case. Just load > >>>>>>> N. > >>>>>>> > >>>>>>> The sine lookup table is addressed by some number of MSBs of the phase > >>>>>>> accumulator, 10 to 16 typically. It doesn't change in a given system. > >>>>>>> > >>>>>>> > >>>>>>> > >>>>>> > >>>>>> Perhaps you could shorten the lookup table to some manageable size if > >>>>>> you do lookup-and-interpolate. Will still be huge... And division > >>>>>> at 100 Msps may well be prohibitive. > >>>>> > >>>>> Our FPGA will have at least a megabit of ram if we use the efinix, > >>>>> lots more if we use the Zynq. A sine table can be folded 2:1 or 4:1, > >>>>> so we can easily do 64K points of 16 bit data. > >>>>> > >>>>> One of my guys proposed an architecture that uses more bits of the > >>>>> phase accumulator. A group of MS bits becomes the gate for a cluster > >>>>> of LS bits. Envision a spinner dial that mostly parks at 0 degrees and > >>>>> once in a while makes a single fast rotation. That essentially puts a > >>>>> divisor *before* a cosine lookup table and DAC. > >>>>> > >>>>> Gotta simulate that somehow. > >>>>> > >>>>> > >>>>> > >>>> > >>>> But if this is to be used as a trigger (similar to the sweep trigger > >>>> on a scope, level knob etc.) can't you just do triangular instead of > >>>> sine wave? Should even be better for that purpose - and no need for a > >>>> lookup table at all... > >>> > >>> That has been considered. But Claude Shannon is the evil stepmother > >>> lurking and plotting to keep us from living happily after. > >>> > >>> The sampling frequency is async to the trigger rate that we want, so > >>> is a source of jitter. A triangle is not bandlimited to below the > >>> Nyquist rate, and we can't afford an ideal lowpass filter either. > >>> > >> I still don't understand why someone would need sine wave for triggering > >> rather than just some TTL or whatever pulse generator, you must have > >> made dozens of these. Just dividing some low jitter oscillator is as > >> trivial as it can get. But if it has to be sine wave well, things do > >> get complicated. I anticipate once you have made that superb sine > >> wave generator they will find out that noise or whatever is a source > >> of some jitter to which the generator's will be negligible.... > >> I don't know the application of course, this is how it looks > >> to me at this point. > > > > try generating arbitrary frequencies that isn't necessarily a multiple of 10ns with a 100MHz clk > > with just a divider... > Obviously you can't do that, I am just wondering about the application > that needs 10 seconds period with picoseconds of jitter. Or with a ns > of jitter, for that. > But other people asked about making sort of the same thing, clearly > there is some demand.the discussion is about making a dothat that does everything from 10 sec to ~60ns periods with low jitter in all cases and no weird transitions
Reply by ●August 17, 20222022-08-17
On Wednesday, August 17, 2022 at 2:31:22 PM UTC-7, jla...@highlandsniptechnology.com wrote:> On Wed, 17 Aug 2022 13:26:53 -0700 (PDT), whit3rd <whi...@gmail.com> > wrote:> >Mr. Shannon assures us that there will be jitter, > The Sampling Theorem describes a sampled system that perfectly > reproduces its input. No time delay even.Irrelevant; the OTHER Shannon work is information content limited by bandwidth and signal/noise, and... the 'ideal' zero-jitter constant frequency with a broad frequency range just has too much information content; whatever number of bits you use to describe the output frequency, it's not enough bits. My proposed 'IF filter' solution only covers a limited bandwidth, by intent; you'd use regular old synchronous counters to divide down the (high) frequency to your target; jitter at low frequency is assuredly not high.
Reply by ●August 17, 20222022-08-17
On Wednesday, August 17, 2022 at 1:02:50 PM UTC-4, Joe Gwinn wrote:> On Tue, 16 Aug 2022 11:32:12 -0700, John Larkin > <jlarkin@highland_atwork_technology.com> wrote: > > >On Tue, 16 Aug 2022 13:46:32 -0400, Joe Gwinn <joeg...@comcast.net> > >wrote: > > > >>On Mon, 15 Aug 2022 19:26:28 -0700, jla...@highlandsniptechnology.com > >>wrote: > >> > >>>On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>>wrote: > >>> > >>>>On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: > >>>>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>>>> wrote: > >>>>> > >>>>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: > >>>>>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > >>>>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>>>>>>> wrote: > >>>>>>>> > >>>>>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >>>>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen > >>>>>>>>>> <lang...@fonz.dk> wrote: > >>>>>>>>>> > >>>>>>>>>>> sųndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > >>>>>>>>>>>> It strikes me that John Larkin's original idea of synthesising > >>>>>>>>>>>> trapezoids can be made to work. > >>>>>>>>>>>> > >>>>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you > >>>>>>>>>>>> fed into your comparator would be made up of four sequential > >>>>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary > >>>>>>>>>>>> length, a falling edge, a low segment, and a risng edge > >>>>>>>>>>>> > >>>>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind > >>>>>>>>>>>> > >>>>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf > >>>>>>>>>>>> > >>>>>>>>>>>> > >>>>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as > >>>>>>>>>>>> 16-successive steps of a staircase waveform. > >>>>>>>>>>> > >>>>>>>>>>> since it is for a trigger and the falling edge probably doesn't > >>>>>>>>>>> matter, why not a single variable voltage step into a filter, sorta > >>>>>>>>>>> like a time-to-amplitude in reverse > >>>>>>>>>> > >>>>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform > >>>>>>>>>> to make a faster edge into a filter and comparator, to get better time > >>>>>>>>>> resolution, less jitter, at low frequencies. > >>>>>>>>> > >>>>>>>>> I am only curious if I understand what you are after - is it some sort > >>>>>>>>> of "the larger the step the less low pass I want applied to it"? > >>>>>>>> > >>>>>>>> When synthesizing a low frequency DDS sine wave, we step slowly > >>>>>>>> through the waveform lookup table and a fixed filter doesn't > >>>>>>>> interpolate waveform steps any more; it settles every step. > >>>>>>>> > >>>>>>>> So, is there a better waveform to use at low frequencies? > >>>>>>>> > >>>>>>> > >>>>>>> Hmmm. I get it now (though I don't get why this is a problem, > >>>>>>> likely specific to your application). I don't know how one > >>>>>>> waveform would be better for you that another, don't know > >>>>>>> what it is you are doing (perhaps you said and I missed it, > >>>>>>> I am not following closely). > >>>>>>> A pretty complex way of dealing with the steps at low frequencies > >>>>>>> is perhaps to have two DACs, one of them making the output filter > >>>>>>> programmable so you can dynamically change it, based on step, > >>>>>>> with some preemption etc., you get the idea - and I am not sure > >>>>>>> it is practical, not only because it is complex but also because > >>>>>>> I have never done this, I am just musing. > >>>>>> > >>>>>> I missed the "we step slowly" in your post, now I get it. > >>>>>> Well, the simplest way out is to step at a constant rate all the > >>>>>> time. > >>>>> > >>>>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > >>>>> needs a sine lookup table with about 50 billion entries. And an > >>>>> equally impossible DAC and comparator. > >>>>> > >>>>> We'll probably wind up synthesizing the high range, an octave or so, > >>>>> and divide down as needed. The trick will be to make the gear shifts > >>>>> appear to be seamless. > >>>>> > >>>>> That could get interesting. > >>>>> > >>>> > >>>>I still don't understand what you are trying to do. Periodic sine > >>>>wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > >>>>wave lookup table for the slowest case. If you want to switch by > >>>>operator action you have milliseconds of time to recalculate the table. > >>>>If you want to switch by some external gating you only need two > >>>>tables to switch between, this makes up to 200 entries. > >>>>This is all way too simple and obvious so you must be after something > >>>>more than that - which I haven't got yet. > >>> > >>>I just want a programmable-frequency trigger generator that changes > >>>frequency on demand and doesn't stop for reprogramming and doesn't > >>>blow up someone's laser by generating any goofy triggers. In other > >>>words, goes smoothly from F1 to F2. > >>> > >>>With low period jitter from, say, 1 mHz to 15 Mhz. > >>> > >>>mHz resolution is good too. > >> > >>I guess I'm not seeing the problem. Ordinary DDS units with 48-bit > >>accumulators can do just this, with phase continuity between the two > >>frequencies, so no glitches. People implement arbitrary > >>frequency-keyed waveforms this way. > >> > >>The phase to trig converter typically uses only the upper 10 to 14 > >>bits of the 48-bit accumulator. Converter implementations vary: > >>table-lookup and CORDIC being very common approaches. > >> > > > >One problem is that, at low frequencies, the LSB of that 10 to 14 bits > >changes infrequently and the lowpass filter doesn't interpolate > >multiple points any more. So one gets a lot of period jitter > > > >>Perhaps it's time to bring the various discussion threads together and > >>re-focus by restating the problem to be solved. > > > >I've stated it a few times: We want a perfect, programmable, > >glitch-free, always right, low period jitter trigger clock. > > > >It's an interesting problem. > If all you want to do is to generate a trigger at any frequency from > 10^-3 Hz to 15*10^6 Hz in 10^-3 Hz steps, that is easily done in a > phase-only DDS topology (no trig conversion needed), which can be > implemented directly in a FPGA. > > This is also known as a Numerically Controlled Oscillator: > > .<https://en.wikipedia.org/wiki/Numerically-controlled_oscillator> > > Our output would be point /M in Figure 1 in the above Wiki article. > (Never mind that M is actually a bit width in that figure.) > > How big must the accumulator be? 15*10^6/10^-3 = 15*10^9 possible > frequencies. Log2[ 15*10^9 ] = 33.8 bits. There was also talk of > needing 50^10^9 steps, which would be 35.5 bits, minimum. In either > case, a 48-bit accumulator will work with room to spare. > > If not, simply make the accumulator larger - 64 bits is also common. > One can also choose the clock rate for convenience given the chosen > accumulator length. > > The trigger signal is when the accumulator rolls over. If the > Frequency Control Word is small, this will take some time. If large, > much faster.The problem is the jitter is a full clock cycle. That's the point of generating a sine wave, then filtering it. The zero crossing is no longer aligned to the master clock and you have a new clock related by the ratio of two large integers, so lots of resolution and low jitter. -- Rick C. ++ Get 1,000 miles of free Supercharging ++ Tesla referral code - https://ts.la/richard11209
Reply by ●August 17, 20222022-08-17
On Wednesday, August 17, 2022 at 6:23:00 PM UTC-4, Dimiter Popoff wrote:> On 8/16/2022 20:13, John Larkin wrote: > > On Tue, 16 Aug 2022 19:51:04 +0300, Dimiter_Popoff <d...@tgi-sci.com> > > wrote: > > > >> On 8/16/2022 17:02, jla...@highlandsniptechnology.com wrote: > >>> On Tue, 16 Aug 2022 15:44:27 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>> wrote: > >>> > >>>> On 8/16/2022 3:23, John Larkin wrote: > >>>>> On Mon, 15 Aug 2022 16:45:18 -0700 (PDT), whit3rd <whi...@gmail.com> > >>>>> wrote: > >>>>> > >>>>>> On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote: > >>>>>>> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: > >>>>>>>> mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff: > >>>>>> > >>>>>>>>> I still don't understand what you are trying to do. Periodic sine > >>>>>>>>> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > >>>>>>>>> wave lookup table for the slowest case. > >>>>>>>> > >>>>>>>> only if you want neat frequencies that add up to 100M > >>>>>>>> > >>>>>>> I don't understand what a neat frequency is, either. Any periodic > >>>>>>> waveform at 1 MHz (the worst case) at 100 Msps update rate takes > >>>>>>> a 100 entry table. > >>>>>> > >>>>>> But suppose you adjust to 0.99 MHz; do you now use a 101 entry table? > >>>>>> And how about 0.995 MHz? > >>>>>> The small-integer ratios for a given frequency don't support a fixed table > >>>>>> size, and the 'update rate' might not be fine-adjustable enough. In contrast > >>>>>> to a variable-LC tuning scheme, digital synthesis tables require... an exercise > >>>>>> in ratios of integers to approximate a real number. > >>>>> > >>>>> With a DDS phase accumulator, the output frequency is > >>>>> > >>>>> Fxo * N / M > >>>>> > >>>>> where Fxo is the 100 MHz xtal oscillator > >>>>> > >>>>> N is the frequency set word > >>>>> > >>>>> M is the accumulator max count, say 2^48. > >>>>> > >>>>> Frequency set resolution would be below 1 uHz in this case. Just load > >>>>> N. > >>>>> > >>>>> The sine lookup table is addressed by some number of MSBs of the phase > >>>>> accumulator, 10 to 16 typically. It doesn't change in a given system. > >>>>> > >>>>> > >>>>> > >>>> > >>>> Perhaps you could shorten the lookup table to some manageable size if > >>>> you do lookup-and-interpolate. Will still be huge... And division > >>>> at 100 Msps may well be prohibitive. > >>> > >>> Our FPGA will have at least a megabit of ram if we use the efinix, > >>> lots more if we use the Zynq. A sine table can be folded 2:1 or 4:1, > >>> so we can easily do 64K points of 16 bit data. > >>> > >>> One of my guys proposed an architecture that uses more bits of the > >>> phase accumulator. A group of MS bits becomes the gate for a cluster > >>> of LS bits. Envision a spinner dial that mostly parks at 0 degrees and > >>> once in a while makes a single fast rotation. That essentially puts a > >>> divisor *before* a cosine lookup table and DAC. > >>> > >>> Gotta simulate that somehow. > >>> > >>> > >>> > >> > >> But if this is to be used as a trigger (similar to the sweep trigger > >> on a scope, level knob etc.) can't you just do triangular instead of > >> sine wave? Should even be better for that purpose - and no need for a > >> lookup table at all... > > > > That has been considered. But Claude Shannon is the evil stepmother > > lurking and plotting to keep us from living happily after. > > > > The sampling frequency is async to the trigger rate that we want, so > > is a source of jitter. A triangle is not bandlimited to below the > > Nyquist rate, and we can't afford an ideal lowpass filter either. > > > I still don't understand why someone would need sine wave for triggering > rather than just some TTL or whatever pulse generator, you must have > made dozens of these. Just dividing some low jitter oscillator is as > trivial as it can get. But if it has to be sine wave well, things do > get complicated. I anticipate once you have made that superb sine > wave generator they will find out that noise or whatever is a source > of some jitter to which the generator's will be negligible.... > I don't know the application of course, this is how it looks > to me at this point.Ok, generate a 1.23456789 MHz clock from a 100 MHz reference using simple digital dividers. The sine wave is how the jitter is reduced to as close to zero as you can afford with the filtering. -- Rick C. --- Get 1,000 miles of free Supercharging --- Tesla referral code - https://ts.la/richard11209
