torsdag den 18. august 2022 kl. 04.52.23 UTC+2 skrev Ricky:> On Wednesday, August 17, 2022 at 6:23:00 PM UTC-4, Dimiter Popoff wrote: > > On 8/16/2022 20:13, John Larkin wrote: > > > On Tue, 16 Aug 2022 19:51:04 +0300, Dimiter_Popoff <d...@tgi-sci.com> > > > wrote: > > > > > >> On 8/16/2022 17:02, jla...@highlandsniptechnology.com wrote: > > >>> On Tue, 16 Aug 2022 15:44:27 +0300, Dimiter_Popoff <d...@tgi-sci.com> > > >>> wrote: > > >>> > > >>>> On 8/16/2022 3:23, John Larkin wrote: > > >>>>> On Mon, 15 Aug 2022 16:45:18 -0700 (PDT), whit3rd <whi...@gmail.com> > > >>>>> wrote: > > >>>>> > > >>>>>> On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote: > > >>>>>>> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: > > >>>>>>>> mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff: > > >>>>>> > > >>>>>>>>> I still don't understand what you are trying to do. Periodic sine > > >>>>>>>>> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > > >>>>>>>>> wave lookup table for the slowest case. > > >>>>>>>> > > >>>>>>>> only if you want neat frequencies that add up to 100M > > >>>>>>>> > > >>>>>>> I don't understand what a neat frequency is, either. Any periodic > > >>>>>>> waveform at 1 MHz (the worst case) at 100 Msps update rate takes > > >>>>>>> a 100 entry table. > > >>>>>> > > >>>>>> But suppose you adjust to 0.99 MHz; do you now use a 101 entry table? > > >>>>>> And how about 0.995 MHz? > > >>>>>> The small-integer ratios for a given frequency don't support a fixed table > > >>>>>> size, and the 'update rate' might not be fine-adjustable enough. In contrast > > >>>>>> to a variable-LC tuning scheme, digital synthesis tables require... an exercise > > >>>>>> in ratios of integers to approximate a real number. > > >>>>> > > >>>>> With a DDS phase accumulator, the output frequency is > > >>>>> > > >>>>> Fxo * N / M > > >>>>> > > >>>>> where Fxo is the 100 MHz xtal oscillator > > >>>>> > > >>>>> N is the frequency set word > > >>>>> > > >>>>> M is the accumulator max count, say 2^48. > > >>>>> > > >>>>> Frequency set resolution would be below 1 uHz in this case. Just load > > >>>>> N. > > >>>>> > > >>>>> The sine lookup table is addressed by some number of MSBs of the phase > > >>>>> accumulator, 10 to 16 typically. It doesn't change in a given system. > > >>>>> > > >>>>> > > >>>>> > > >>>> > > >>>> Perhaps you could shorten the lookup table to some manageable size if > > >>>> you do lookup-and-interpolate. Will still be huge... And division > > >>>> at 100 Msps may well be prohibitive. > > >>> > > >>> Our FPGA will have at least a megabit of ram if we use the efinix, > > >>> lots more if we use the Zynq. A sine table can be folded 2:1 or 4:1, > > >>> so we can easily do 64K points of 16 bit data. > > >>> > > >>> One of my guys proposed an architecture that uses more bits of the > > >>> phase accumulator. A group of MS bits becomes the gate for a cluster > > >>> of LS bits. Envision a spinner dial that mostly parks at 0 degrees and > > >>> once in a while makes a single fast rotation. That essentially puts a > > >>> divisor *before* a cosine lookup table and DAC. > > >>> > > >>> Gotta simulate that somehow. > > >>> > > >>> > > >>> > > >> > > >> But if this is to be used as a trigger (similar to the sweep trigger > > >> on a scope, level knob etc.) can't you just do triangular instead of > > >> sine wave? Should even be better for that purpose - and no need for a > > >> lookup table at all... > > > > > > That has been considered. But Claude Shannon is the evil stepmother > > > lurking and plotting to keep us from living happily after. > > > > > > The sampling frequency is async to the trigger rate that we want, so > > > is a source of jitter. A triangle is not bandlimited to below the > > > Nyquist rate, and we can't afford an ideal lowpass filter either. > > > > > I still don't understand why someone would need sine wave for triggering > > rather than just some TTL or whatever pulse generator, you must have > > made dozens of these. Just dividing some low jitter oscillator is as > > trivial as it can get. But if it has to be sine wave well, things do > > get complicated. I anticipate once you have made that superb sine > > wave generator they will find out that noise or whatever is a source > > of some jitter to which the generator's will be negligible.... > > I don't know the application of course, this is how it looks > > to me at this point. > Ok, generate a 1.23456789 MHz clock from a 100 MHz reference using simple digital dividers.divide by 81 ;)
Direct digital synthesis of square waves
Started by ●August 14, 2022
Reply by ●August 18, 20222022-08-18
Reply by ●August 18, 20222022-08-18
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>> Ok, generate a 1.23456789 MHz clock from a 100 MHz reference using >> simple digital dividers. > > divide by 81 ;) >Off a bit: 100/81 = 1.23456790123 -- MRM
Reply by ●August 18, 20222022-08-18
torsdag den 18. august 2022 kl. 10.20.49 UTC+2 skrev Mike Monett VE3BTI:> Lasse Langwadt Christensen <lang...@fonz.dk> wrote: > >> Ok, generate a 1.23456789 MHz clock from a 100 MHz reference using > >> simple digital dividers. > > > > divide by 81 ;) > > > Off a bit: > 100/81 = 1.23456790123~1ppm
Reply by ●August 18, 20222022-08-18
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:> torsdag den 18. august 2022 kl. 10.20.49 UTC+2 skrev Mike Monett VE3BTI: >> Lasse Langwadt Christensen <lang...@fonz.dk> wrote: >> >> Ok, generate a 1.23456789 MHz clock from a 100 MHz reference using >> >> simple digital dividers. >> > >> > divide by 81 ;) >> > >> Off a bit: >> 100/81 = 1.23456790123 > > ~1ppmSet the frequency to 1.23456789 * 81 = 99.99999909 MHz - exact Use a GPSDO for 1e-12 accuracy Measure with a FA-2 counter: https://www.banggood.com/FA-2-1Hz-12_4GHz-Frequency-Counter-Kit-Frequency- Meter-Statistical-Function-11-bits-or-sec-Tester-with-Power-Adapter-p- 1645869.html Manual: https://www.eevblog.com/forum/metrology/bg7tbl-fa1-frequency-analyzer/? action=dlattach;attach=876418 Discussion: https://www.eevblog.com/forum/metrology/bg7tbl-fa1-frequency-analyzer/ Time-Nuts Discussion: https://www.mail-archive.com/search?q=fa-2+counter&l=time-nuts% 40lists.febo.com Alternative: Stanford Research Frequency Counter SR620 � 13 digit Time interval / frequency counter, from $4950 https://www.thinksrs.com/products/sr620.html Make it into a SRS SG380 Signal Generator: The Stanford Research Systems group has introduced a new method of frequency generation described below: Introducing the new SG380 Series RF Signal Generators - finally, high performance, affordable RF sources. The SG380 Series RF Signal Generators use a unique, innovative architecture (Rational Approximation Frequency Synthesis) to deliver ultra-high frequency resolution (1 �Hz), excellent phase noise, and versatile modulation capabilities (AM, FM, �M, pulse modulation and sweeps) at a fraction of the cost of competing designs. A New Frequency Synthesis Technique The SG380 Series Signal Generators are based on a new frequency synthesis technique called Rational Approximation Frequency Synthesis (RAFS). RAFS uses small integer divisors in a conventional phase-locked loop (PLL) to synthesize a frequency that would be close to the desired frequency (typically within �100 ppm) using the nominal PLL reference frequency. The PLL reference frequency, which is sourced by a voltage control crystal oscillator that is phase locked to a dithered direct digital synthesizer, is adjusted so that the PLL generates the exact frequency. Doing so provides a high phase comparison frequency (typically 25 MHz) yielding low phase noise while moving the PLL reference spurs far from the carrier where they can be easily removed. The end result is an agile RF source with low phase noise, essentially infinite frequency resolution, without the spurs of fractional-N synthesis or the cost of a YIG oscillator. https://www.thinksrs.com/products/sg380.html The manual is at https://www.thinksrs.com/downloads/pdfs/manuals/SG380m.pdf The description of Rational Approximation Synthesis starts on page 151. A block diagram is on page 156. -- MRM
Reply by ●August 18, 20222022-08-18
On 8/17/22 9:58 AM, jlarkin@highlandsniptechnology.com wrote:> On Wed, 17 Aug 2022 06:44:18 -0000 (UTC), Jasen Betts > <usenet@revmaps.no-ip.org> wrote: > >> On 2022-08-16, whit3rd <whit3rd@gmail.com> wrote: >>> >>> A smaller sine/cos table might be used with >>> >>> sine(a+b) = sine(a) cos(b) + cos(a)sine(b) >>> >>> as in, with small deviations 'b' from major steps in the table, two multiplies and >>> an add give you 2^20 different accurate sines from a 2^10 size sine table. >>> Since cos(b) will always be near unity ( 1 plus order of 2^-20 when b is under 2^-10), >>> you can make that one multiply and an add. Perhaps that's what the 'phase >>> accumulator' is for, estimating the 'b'? >> >> AKA "CORDIC" > > In an FPGA, one could have the basic sine table and an interpolation > slope table and maybe just add. Do the math at compile time, not run > time. > > At some point, dac resolution becomes the limit, not sine table > resolution. >Apologies if somebody has pointed this out upthread--I didn't follow it all. If you have enough bits in the phase accumulator, and apply the right amount of numerical gain ahead of the DAC, you can always get a well-behaved trapezoidal waveform with a nice smooth fine-grained staircase near the zero crossing, which will filter well. (Saturating arithmetic is required, obviously.) You just need to make sure that the duration of the linear part is at least twice the filter's settling time (to the required accuracy), so that the ringing from the corner of the trapezoid has all settled out by the time you get to the zero crossing. If you increase the numerical gain like 1/f, this works down to as low a frequency as you like. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net https://hobbs-eo.com
Reply by ●August 18, 20222022-08-18
torsdag den 18. august 2022 kl. 18.41.52 UTC+2 skrev Phil Hobbs:> On 8/17/22 9:58 AM, jla...@highlandsniptechnology.com wrote: > > On Wed, 17 Aug 2022 06:44:18 -0000 (UTC), Jasen Betts > > <use...@revmaps.no-ip.org> wrote: > > > >> On 2022-08-16, whit3rd <whi...@gmail.com> wrote: > >>> > >>> A smaller sine/cos table might be used with > >>> > >>> sine(a+b) = sine(a) cos(b) + cos(a)sine(b) > >>> > >>> as in, with small deviations 'b' from major steps in the table, two multiplies and > >>> an add give you 2^20 different accurate sines from a 2^10 size sine table. > >>> Since cos(b) will always be near unity ( 1 plus order of 2^-20 when b is under 2^-10), > >>> you can make that one multiply and an add. Perhaps that's what the 'phase > >>> accumulator' is for, estimating the 'b'? > >> > >> AKA "CORDIC" > > > > In an FPGA, one could have the basic sine table and an interpolation > > slope table and maybe just add. Do the math at compile time, not run > > time. > > > > At some point, dac resolution becomes the limit, not sine table > > resolution. > > > Apologies if somebody has pointed this out upthread--I didn't follow it all. > > If you have enough bits in the phase accumulator, and apply the right > amount of numerical gain ahead of the DAC, you can always get a > well-behaved trapezoidal waveform with a nice smooth fine-grained > staircase near the zero crossing, which will filter well. (Saturating > arithmetic is required, obviously.) > > You just need to make sure that the duration of the linear part is at > least twice the filter's settling time (to the required accuracy), so > that the ringing from the corner of the trapezoid has all settled out by > the time you get to the zero crossing. If you increase the numerical > gain like 1/f, this works down to as low a frequency as you like. >something like this should be simple to implement by gaining and clamping the triangular wave going into the sine table https://imgur.com/6KqpCW9
Reply by ●August 18, 20222022-08-18
On Thursday, August 18, 2022 at 12:41:52 PM UTC-4, Phil Hobbs wrote:> On 8/17/22 9:58 AM, jla...@highlandsniptechnology.com wrote: > > On Wed, 17 Aug 2022 06:44:18 -0000 (UTC), Jasen Betts > > <use...@revmaps.no-ip.org> wrote: > > > >> On 2022-08-16, whit3rd <whi...@gmail.com> wrote: > >>> > >>> A smaller sine/cos table might be used with > >>> > >>> sine(a+b) = sine(a) cos(b) + cos(a)sine(b) > >>> > >>> as in, with small deviations 'b' from major steps in the table, two multiplies and > >>> an add give you 2^20 different accurate sines from a 2^10 size sine table. > >>> Since cos(b) will always be near unity ( 1 plus order of 2^-20 when b is under 2^-10), > >>> you can make that one multiply and an add. Perhaps that's what the 'phase > >>> accumulator' is for, estimating the 'b'? > >> > >> AKA "CORDIC" > > > > In an FPGA, one could have the basic sine table and an interpolation > > slope table and maybe just add. Do the math at compile time, not run > > time. > > > > At some point, dac resolution becomes the limit, not sine table > > resolution. > > > Apologies if somebody has pointed this out upthread--I didn't follow it all. > > If you have enough bits in the phase accumulator, and apply the right > amount of numerical gain ahead of the DAC, you can always get a > well-behaved trapezoidal waveform with a nice smooth fine-grained > staircase near the zero crossing, which will filter well. (Saturating > arithmetic is required, obviously.) > > You just need to make sure that the duration of the linear part is at > least twice the filter's settling time (to the required accuracy), so > that the ringing from the corner of the trapezoid has all settled out by > the time you get to the zero crossing. If you increase the numerical > gain like 1/f, this works down to as low a frequency as you like.The problem with the low frequency is not "Numerical gain", which is an odd way of putting it. If you use a standard sine table, it won't matter how much gain you provide after the quantization in the table output. The damage has been done. The issue becomes one of defining the transition from much lower significance bits in the phase word than the table can be sized for. Thus, a special transition table needs to be used, addressed only by the lsbs of the phase word, enabled by the upper bits. None of this complication is needed. A standard DDS can be used to create a high rate clock over a 2:1 frequency range. This clock will have low jitter. This clock can then be reduced by a programmable octave divider, to provide the final frequency. If this divider does not have sufficient jitter stability, this output is run through a FF, clocked by the output of the DDS, and using a technology which has sufficiently low jitter as to meet the requirement. Both the DDS and the programmable divider can be changed on the same clock cycle which means there will be no disruption in observed frequency output. Each pulse will be either one rate or the other or some period in between during the transition. No need for messy nonsense of trying to work around the issue of slow sine waves. The sine wave is always high frequency using well understood techniques. You are welcome. -- Rick C. --+ Get 1,000 miles of free Supercharging --+ Tesla referral code - https://ts.la/richard11209
Reply by ●August 18, 20222022-08-18
Mike Monett VE3BTI <spamme@not.com> wrote:> Set the frequency to 1.23456789 * 81 = 99.99999909 MHz > - exactTTCalc By Tomasz Sowa Free Developer's Description TTCalc is an open source bignum mathematical calculator. It features arithmetical functions, trigonometric functions, inverse trigonometric functions, hyperbolic functions, inverse hyperbolic functions, logical operators, logarithms, functions for converting between degrees and radians and so on. Additionally the program allows a user to define his own variables and functions. Operating Systems Windows 2003, Windows 2000, Windows Vista, Windows 98, Windows Me, Windows, Windows NT, Windows 7, Windows XP https://download.cnet.com/TTCalc/3000-2053_4-75445805.html -- MRM
Reply by ●August 18, 20222022-08-18
On Thu, 18 Aug 2022 01:22:51 +0300, Dimiter_Popoff <dp@tgi-sci.com> wrote:>On 8/16/2022 20:13, John Larkin wrote: >> On Tue, 16 Aug 2022 19:51:04 +0300, Dimiter_Popoff <dp@tgi-sci.com> >> wrote: >> >>> On 8/16/2022 17:02, jlarkin@highlandsniptechnology.com wrote: >>>> On Tue, 16 Aug 2022 15:44:27 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>>> wrote: >>>> >>>>> On 8/16/2022 3:23, John Larkin wrote: >>>>>> On Mon, 15 Aug 2022 16:45:18 -0700 (PDT), whit3rd <whit3rd@gmail.com> >>>>>> wrote: >>>>>> >>>>>>> On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote: >>>>>>>> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: >>>>>>>>> mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff: >>>>>>> >>>>>>>>>> I still don't understand what you are trying to do. Periodic sine >>>>>>>>>> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >>>>>>>>>> wave lookup table for the slowest case. >>>>>>>>> >>>>>>>>> only if you want neat frequencies that add up to 100M >>>>>>>>> >>>>>>>> I don't understand what a neat frequency is, either. Any periodic >>>>>>>> waveform at 1 MHz (the worst case) at 100 Msps update rate takes >>>>>>>> a 100 entry table. >>>>>>> >>>>>>> But suppose you adjust to 0.99 MHz; do you now use a 101 entry table? >>>>>>> And how about 0.995 MHz? >>>>>>> The small-integer ratios for a given frequency don't support a fixed table >>>>>>> size, and the 'update rate' might not be fine-adjustable enough. In contrast >>>>>>> to a variable-LC tuning scheme, digital synthesis tables require... an exercise >>>>>>> in ratios of integers to approximate a real number. >>>>>> >>>>>> With a DDS phase accumulator, the output frequency is >>>>>> >>>>>> Fxo * N / M >>>>>> >>>>>> where Fxo is the 100 MHz xtal oscillator >>>>>> >>>>>> N is the frequency set word >>>>>> >>>>>> M is the accumulator max count, say 2^48. >>>>>> >>>>>> Frequency set resolution would be below 1 uHz in this case. Just load >>>>>> N. >>>>>> >>>>>> The sine lookup table is addressed by some number of MSBs of the phase >>>>>> accumulator, 10 to 16 typically. It doesn't change in a given system. >>>>>> >>>>>> >>>>>> >>>>> >>>>> Perhaps you could shorten the lookup table to some manageable size if >>>>> you do lookup-and-interpolate. Will still be huge... And division >>>>> at 100 Msps may well be prohibitive. >>>> >>>> Our FPGA will have at least a megabit of ram if we use the efinix, >>>> lots more if we use the Zynq. A sine table can be folded 2:1 or 4:1, >>>> so we can easily do 64K points of 16 bit data. >>>> >>>> One of my guys proposed an architecture that uses more bits of the >>>> phase accumulator. A group of MS bits becomes the gate for a cluster >>>> of LS bits. Envision a spinner dial that mostly parks at 0 degrees and >>>> once in a while makes a single fast rotation. That essentially puts a >>>> divisor *before* a cosine lookup table and DAC. >>>> >>>> Gotta simulate that somehow. >>>> >>>> >>>> >>> >>> But if this is to be used as a trigger (similar to the sweep trigger >>> on a scope, level knob etc.) can't you just do triangular instead of >>> sine wave? Should even be better for that purpose - and no need for a >>> lookup table at all... >> >> That has been considered. But Claude Shannon is the evil stepmother >> lurking and plotting to keep us from living happily after. >> >> The sampling frequency is async to the trigger rate that we want, so >> is a source of jitter. A triangle is not bandlimited to below the >> Nyquist rate, and we can't afford an ideal lowpass filter either. >> > >I still don't understand why someone would need sine wave for triggering >rather than just some TTL or whatever pulse generator, you must have >made dozens of these.Most DDS theory uses sine waves. There could well be a better waveform, like a trapezoid, but that's going to need a lot of simulation to evaluate. Just dividing some low jitter oscillator is as>trivial as it can get.DDS has arbitrary frequency resolution and, potentially, very low jitter. Divisors have low jitter but quantify the frequency selections hard. Our users can already select the internal XO and a divisor. In fact, they can program a burst of N pulses every M pulses no matter what the clock source.
Reply by ●August 18, 20222022-08-18
On Thu, 18 Aug 2022 12:41:33 -0400, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>On 8/17/22 9:58 AM, jlarkin@highlandsniptechnology.com wrote: >> On Wed, 17 Aug 2022 06:44:18 -0000 (UTC), Jasen Betts >> <usenet@revmaps.no-ip.org> wrote: >> >>> On 2022-08-16, whit3rd <whit3rd@gmail.com> wrote: >>>> >>>> A smaller sine/cos table might be used with >>>> >>>> sine(a+b) = sine(a) cos(b) + cos(a)sine(b) >>>> >>>> as in, with small deviations 'b' from major steps in the table, two multiplies and >>>> an add give you 2^20 different accurate sines from a 2^10 size sine table. >>>> Since cos(b) will always be near unity ( 1 plus order of 2^-20 when b is under 2^-10), >>>> you can make that one multiply and an add. Perhaps that's what the 'phase >>>> accumulator' is for, estimating the 'b'? >>> >>> AKA "CORDIC" >> >> In an FPGA, one could have the basic sine table and an interpolation >> slope table and maybe just add. Do the math at compile time, not run >> time. >> >> At some point, dac resolution becomes the limit, not sine table >> resolution. >> > >Apologies if somebody has pointed this out upthread--I didn't follow it all. > >If you have enough bits in the phase accumulator, and apply the right >amount of numerical gain ahead of the DAC, you can always get a >well-behaved trapezoidal waveform with a nice smooth fine-grained >staircase near the zero crossing, which will filter well. (Saturating >arithmetic is required, obviously.) > >You just need to make sure that the duration of the linear part is at >least twice the filter's settling time (to the required accuracy), so >that the ringing from the corner of the trapezoid has all settled out by >the time you get to the zero crossing. If you increase the numerical >gain like 1/f, this works down to as low a frequency as you like.Right. The trapezoid corner happens at an XO edge, which makes output jitter, so the filter has to forget that corner but average as many samples as it can along the linear slope. The trapezoid is not bandlimited so violates the concept of the Sampling Theorem. This argues for making the comparator trip at near the top of the trapezoid, not the mid-voltage zero crossing equivalent. One might make the trapezoid edge steeper at low synthesized frequencies and maybe incorporate more LSBish phase accumulator bits. Somehow. Seamlessly.
