On 8/16/2022 17:02, jlarkin@highlandsniptechnology.com wrote:> On Tue, 16 Aug 2022 15:44:27 +0300, Dimiter_Popoff <dp@tgi-sci.com> > wrote: > >> On 8/16/2022 3:23, John Larkin wrote: >>> On Mon, 15 Aug 2022 16:45:18 -0700 (PDT), whit3rd <whit3rd@gmail.com> >>> wrote: >>> >>>> On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote: >>>>> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: >>>>>> mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff: >>>> >>>>>>> I still don't understand what you are trying to do. Periodic sine >>>>>>> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >>>>>>> wave lookup table for the slowest case. >>>>>> >>>>>> only if you want neat frequencies that add up to 100M >>>>>> >>>>> I don't understand what a neat frequency is, either. Any periodic >>>>> waveform at 1 MHz (the worst case) at 100 Msps update rate takes >>>>> a 100 entry table. >>>> >>>> But suppose you adjust to 0.99 MHz; do you now use a 101 entry table? >>>> And how about 0.995 MHz? >>>> The small-integer ratios for a given frequency don't support a fixed table >>>> size, and the 'update rate' might not be fine-adjustable enough. In contrast >>>> to a variable-LC tuning scheme, digital synthesis tables require... an exercise >>>> in ratios of integers to approximate a real number. >>> >>> With a DDS phase accumulator, the output frequency is >>> >>> Fxo * N / M >>> >>> where Fxo is the 100 MHz xtal oscillator >>> >>> N is the frequency set word >>> >>> M is the accumulator max count, say 2^48. >>> >>> Frequency set resolution would be below 1 uHz in this case. Just load >>> N. >>> >>> The sine lookup table is addressed by some number of MSBs of the phase >>> accumulator, 10 to 16 typically. It doesn't change in a given system. >>> >>> >>> >> >> Perhaps you could shorten the lookup table to some manageable size if >> you do lookup-and-interpolate. Will still be huge... And division >> at 100 Msps may well be prohibitive. > > Our FPGA will have at least a megabit of ram if we use the efinix, > lots more if we use the Zynq. A sine table can be folded 2:1 or 4:1, > so we can easily do 64K points of 16 bit data. > > One of my guys proposed an architecture that uses more bits of the > phase accumulator. A group of MS bits becomes the gate for a cluster > of LS bits. Envision a spinner dial that mostly parks at 0 degrees and > once in a while makes a single fast rotation. That essentially puts a > divisor *before* a cosine lookup table and DAC. > > Gotta simulate that somehow. > > >But if this is to be used as a trigger (similar to the sweep trigger on a scope, level knob etc.) can't you just do triangular instead of sine wave? Should even be better for that purpose - and no need for a lookup table at all...
Direct digital synthesis of square waves
Started by ●August 14, 2022
Reply by ●August 16, 20222022-08-16
Reply by ●August 16, 20222022-08-16
On Tue, 16 Aug 2022 19:51:04 +0300, Dimiter_Popoff <dp@tgi-sci.com> wrote:>On 8/16/2022 17:02, jlarkin@highlandsniptechnology.com wrote: >> On Tue, 16 Aug 2022 15:44:27 +0300, Dimiter_Popoff <dp@tgi-sci.com> >> wrote: >> >>> On 8/16/2022 3:23, John Larkin wrote: >>>> On Mon, 15 Aug 2022 16:45:18 -0700 (PDT), whit3rd <whit3rd@gmail.com> >>>> wrote: >>>> >>>>> On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote: >>>>>> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: >>>>>>> mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff: >>>>> >>>>>>>> I still don't understand what you are trying to do. Periodic sine >>>>>>>> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >>>>>>>> wave lookup table for the slowest case. >>>>>>> >>>>>>> only if you want neat frequencies that add up to 100M >>>>>>> >>>>>> I don't understand what a neat frequency is, either. Any periodic >>>>>> waveform at 1 MHz (the worst case) at 100 Msps update rate takes >>>>>> a 100 entry table. >>>>> >>>>> But suppose you adjust to 0.99 MHz; do you now use a 101 entry table? >>>>> And how about 0.995 MHz? >>>>> The small-integer ratios for a given frequency don't support a fixed table >>>>> size, and the 'update rate' might not be fine-adjustable enough. In contrast >>>>> to a variable-LC tuning scheme, digital synthesis tables require... an exercise >>>>> in ratios of integers to approximate a real number. >>>> >>>> With a DDS phase accumulator, the output frequency is >>>> >>>> Fxo * N / M >>>> >>>> where Fxo is the 100 MHz xtal oscillator >>>> >>>> N is the frequency set word >>>> >>>> M is the accumulator max count, say 2^48. >>>> >>>> Frequency set resolution would be below 1 uHz in this case. Just load >>>> N. >>>> >>>> The sine lookup table is addressed by some number of MSBs of the phase >>>> accumulator, 10 to 16 typically. It doesn't change in a given system. >>>> >>>> >>>> >>> >>> Perhaps you could shorten the lookup table to some manageable size if >>> you do lookup-and-interpolate. Will still be huge... And division >>> at 100 Msps may well be prohibitive. >> >> Our FPGA will have at least a megabit of ram if we use the efinix, >> lots more if we use the Zynq. A sine table can be folded 2:1 or 4:1, >> so we can easily do 64K points of 16 bit data. >> >> One of my guys proposed an architecture that uses more bits of the >> phase accumulator. A group of MS bits becomes the gate for a cluster >> of LS bits. Envision a spinner dial that mostly parks at 0 degrees and >> once in a while makes a single fast rotation. That essentially puts a >> divisor *before* a cosine lookup table and DAC. >> >> Gotta simulate that somehow. >> >> >> > >But if this is to be used as a trigger (similar to the sweep trigger >on a scope, level knob etc.) can't you just do triangular instead of >sine wave? Should even be better for that purpose - and no need for a >lookup table at all...That has been considered. But Claude Shannon is the evil stepmother lurking and plotting to keep us from living happily after. The sampling frequency is async to the trigger rate that we want, so is a source of jitter. A triangle is not bandlimited to below the Nyquist rate, and we can't afford an ideal lowpass filter either.
Reply by ●August 16, 20222022-08-16
On Tuesday, August 16, 2022 at 7:03:01 AM UTC-7, jla...@highlandsniptechnology.com wrote:> On Tue, 16 Aug 2022 15:44:27 +0300, Dimiter_Popoff <d...@tgi-sci.com> > wrote: > >On 8/16/2022 3:23, John Larkin wrote: > >> On Mon, 15 Aug 2022 16:45:18 -0700 (PDT), whit3rd <whi...@gmail.com> > >> wrote: > >> > >>> On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote: > >>>> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: > >>>>> mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff:> >>>>>> I still don't understand what you are trying to do. Periodic sine > >>>>>> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > >>>>>> wave lookup table for the slowest case.> >>> The small-integer ratios for a given frequency don't support a fixed table > >>> size, and the 'update rate' might not be fine-adjustable enough. In contrast > >>> to a variable-LC tuning scheme, digital synthesis tables require... an exercise > >>> in ratios of integers to approximate a real number. > >> > >> With a DDS phase accumulator, the output frequency is > >> > >> Fxo * N / M > >> > >> where Fxo is the 100 MHz xtal oscillator > >> > >> N is the frequency set word > >> > >> M is the accumulator max count, say 2^48. > >> > >> Frequency set resolution would be below 1 uHz in this case. Just load > >> N. > >> > >> The sine lookup table is addressed by some number of MSBs of the phase > >> accumulator, 10 to 16 typically. It doesn't change in a given system.> >Perhaps you could shorten the lookup table to some manageable size if > >you do lookup-and-interpolate. Will still be huge... And division > >at 100 Msps may well be prohibitive.> Our FPGA will have at least a megabit of ram if we use the efinix, > lots more if we use the Zynq. A sine table can be folded 2:1 or 4:1, > so we can easily do 64K points of 16 bit data.A smaller sine/cos table might be used with sine(a+b) = sine(a) cos(b) + cos(a)sine(b) as in, with small deviations 'b' from major steps in the table, two multiplies and an add give you 2^20 different accurate sines from a 2^10 size sine table. Since cos(b) will always be near unity ( 1 plus order of 2^-20 when b is under 2^-10), you can make that one multiply and an add. Perhaps that's what the 'phase accumulator' is for, estimating the 'b'?
Reply by ●August 16, 20222022-08-16
On Mon, 15 Aug 2022 19:26:28 -0700, jlarkin@highlandsniptechnology.com wrote:>On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <dp@tgi-sci.com> >wrote: > >>On 8/15/2022 17:17, jlarkin@highlandsniptechnology.com wrote: >>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>> wrote: >>> >>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: >>>>> On 8/15/2022 1:08, jlarkin@highlandsniptechnology.com wrote: >>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>>>>> wrote: >>>>>> >>>>>>> On 8/14/2022 17:14, jlarkin@highlandsniptechnology.com wrote: >>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>> <langwadt@fonz.dk> wrote: >>>>>>>> >>>>>>>>> s�ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >>>>>>>>>> It strikes me that John Larkin's original idea of synthesising >>>>>>>>>> trapezoids can be made to work. >>>>>>>>>> >>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you >>>>>>>>>> fed into your comparator would be made up of four sequential >>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary >>>>>>>>>> length, a falling edge, a low segment, and a risng edge >>>>>>>>>> >>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind >>>>>>>>>> >>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as >>>>>>>>>> 16-successive steps of a staircase waveform. >>>>>>>>> >>>>>>>>> since it is for a trigger and the falling edge probably doesn't >>>>>>>>> matter, why not a single variable voltage step into a filter, sorta >>>>>>>>> like a time-to-amplitude in reverse >>>>>>>> >>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform >>>>>>>> to make a faster edge into a filter and comparator, to get better time >>>>>>>> resolution, less jitter, at low frequencies. >>>>>>> >>>>>>> I am only curious if I understand what you are after - is it some sort >>>>>>> of "the larger the step the less low pass I want applied to it"? >>>>>> >>>>>> When synthesizing a low frequency DDS sine wave, we step slowly >>>>>> through the waveform lookup table and a fixed filter doesn't >>>>>> interpolate waveform steps any more; it settles every step. >>>>>> >>>>>> So, is there a better waveform to use at low frequencies? >>>>>> >>>>> >>>>> Hmmm. I get it now (though I don't get why this is a problem, >>>>> likely specific to your application). I don't know how one >>>>> waveform would be better for you that another, don't know >>>>> what it is you are doing (perhaps you said and I missed it, >>>>> I am not following closely). >>>>> A pretty complex way of dealing with the steps at low frequencies >>>>> is perhaps to have two DACs, one of them making the output filter >>>>> programmable so you can dynamically change it, based on step, >>>>> with some preemption etc., you get the idea - and I am not sure >>>>> it is practical, not only because it is complex but also because >>>>> I have never done this, I am just musing. >>>> >>>> I missed the "we step slowly" in your post, now I get it. >>>> Well, the simplest way out is to step at a constant rate all the >>>> time. >>> >>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That >>> needs a sine lookup table with about 50 billion entries. And an >>> equally impossible DAC and comparator. >>> >>> We'll probably wind up synthesizing the high range, an octave or so, >>> and divide down as needed. The trick will be to make the gear shifts >>> appear to be seamless. >>> >>> That could get interesting. >>> >> >>I still don't understand what you are trying to do. Periodic sine >>wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >>wave lookup table for the slowest case. If you want to switch by >>operator action you have milliseconds of time to recalculate the table. >>If you want to switch by some external gating you only need two >>tables to switch between, this makes up to 200 entries. >>This is all way too simple and obvious so you must be after something >>more than that - which I haven't got yet. > >I just want a programmable-frequency trigger generator that changes >frequency on demand and doesn't stop for reprogramming and doesn't >blow up someone's laser by generating any goofy triggers. In other >words, goes smoothly from F1 to F2. > >With low period jitter from, say, 1 mHz to 15 Mhz. > >mHz resolution is good too.I guess I'm not seeing the problem. Ordinary DDS units with 48-bit accumulators can do just this, with phase continuity between the two frequencies, so no glitches. People implement arbitrary frequency-keyed waveforms this way. The phase to trig converter typically uses only the upper 10 to 14 bits of the 48-bit accumulator. Converter implementations vary: table-lookup and CORDIC being very common approaches. Perhaps it's time to bring the various discussion threads together and re-focus by restating the problem to be solved. Joe Gwinn
Reply by ●August 16, 20222022-08-16
On Tue, 16 Aug 2022 13:46:32 -0400, Joe Gwinn <joegwinn@comcast.net> wrote:>On Mon, 15 Aug 2022 19:26:28 -0700, jlarkin@highlandsniptechnology.com >wrote: > >>On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>wrote: >> >>>On 8/15/2022 17:17, jlarkin@highlandsniptechnology.com wrote: >>>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>>> wrote: >>>> >>>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: >>>>>> On 8/15/2022 1:08, jlarkin@highlandsniptechnology.com wrote: >>>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>>>>>> wrote: >>>>>>> >>>>>>>> On 8/14/2022 17:14, jlarkin@highlandsniptechnology.com wrote: >>>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>>> <langwadt@fonz.dk> wrote: >>>>>>>>> >>>>>>>>>> s�ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >>>>>>>>>>> It strikes me that John Larkin's original idea of synthesising >>>>>>>>>>> trapezoids can be made to work. >>>>>>>>>>> >>>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you >>>>>>>>>>> fed into your comparator would be made up of four sequential >>>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary >>>>>>>>>>> length, a falling edge, a low segment, and a risng edge >>>>>>>>>>> >>>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind >>>>>>>>>>> >>>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as >>>>>>>>>>> 16-successive steps of a staircase waveform. >>>>>>>>>> >>>>>>>>>> since it is for a trigger and the falling edge probably doesn't >>>>>>>>>> matter, why not a single variable voltage step into a filter, sorta >>>>>>>>>> like a time-to-amplitude in reverse >>>>>>>>> >>>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform >>>>>>>>> to make a faster edge into a filter and comparator, to get better time >>>>>>>>> resolution, less jitter, at low frequencies. >>>>>>>> >>>>>>>> I am only curious if I understand what you are after - is it some sort >>>>>>>> of "the larger the step the less low pass I want applied to it"? >>>>>>> >>>>>>> When synthesizing a low frequency DDS sine wave, we step slowly >>>>>>> through the waveform lookup table and a fixed filter doesn't >>>>>>> interpolate waveform steps any more; it settles every step. >>>>>>> >>>>>>> So, is there a better waveform to use at low frequencies? >>>>>>> >>>>>> >>>>>> Hmmm. I get it now (though I don't get why this is a problem, >>>>>> likely specific to your application). I don't know how one >>>>>> waveform would be better for you that another, don't know >>>>>> what it is you are doing (perhaps you said and I missed it, >>>>>> I am not following closely). >>>>>> A pretty complex way of dealing with the steps at low frequencies >>>>>> is perhaps to have two DACs, one of them making the output filter >>>>>> programmable so you can dynamically change it, based on step, >>>>>> with some preemption etc., you get the idea - and I am not sure >>>>>> it is practical, not only because it is complex but also because >>>>>> I have never done this, I am just musing. >>>>> >>>>> I missed the "we step slowly" in your post, now I get it. >>>>> Well, the simplest way out is to step at a constant rate all the >>>>> time. >>>> >>>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That >>>> needs a sine lookup table with about 50 billion entries. And an >>>> equally impossible DAC and comparator. >>>> >>>> We'll probably wind up synthesizing the high range, an octave or so, >>>> and divide down as needed. The trick will be to make the gear shifts >>>> appear to be seamless. >>>> >>>> That could get interesting. >>>> >>> >>>I still don't understand what you are trying to do. Periodic sine >>>wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >>>wave lookup table for the slowest case. If you want to switch by >>>operator action you have milliseconds of time to recalculate the table. >>>If you want to switch by some external gating you only need two >>>tables to switch between, this makes up to 200 entries. >>>This is all way too simple and obvious so you must be after something >>>more than that - which I haven't got yet. >> >>I just want a programmable-frequency trigger generator that changes >>frequency on demand and doesn't stop for reprogramming and doesn't >>blow up someone's laser by generating any goofy triggers. In other >>words, goes smoothly from F1 to F2. >> >>With low period jitter from, say, 1 mHz to 15 Mhz. >> >>mHz resolution is good too. > >I guess I'm not seeing the problem. Ordinary DDS units with 48-bit >accumulators can do just this, with phase continuity between the two >frequencies, so no glitches. People implement arbitrary >frequency-keyed waveforms this way. > >The phase to trig converter typically uses only the upper 10 to 14 >bits of the 48-bit accumulator. Converter implementations vary: >table-lookup and CORDIC being very common approaches. >One problem is that, at low frequencies, the LSB of that 10 to 14 bits changes infrequently and the lowpass filter doesn't interpolate multiple points any more. So one gets a lot of period jitter>Perhaps it's time to bring the various discussion threads together and >re-focus by restating the problem to be solved.I've stated it a few times: We want a perfect, programmable, glitch-free, always right, low period jitter trigger clock. It's an interesting problem.
Reply by ●August 16, 20222022-08-16
tirsdag den 16. august 2022 kl. 19.46.45 UTC+2 skrev Joe Gwinn:> On Mon, 15 Aug 2022 19:26:28 -0700, jla...@highlandsniptechnology.com > wrote: > > >On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >wrote: > > > >>On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: > >>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>> wrote: > >>> > >>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: > >>>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > >>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>>>>> wrote: > >>>>>> > >>>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen > >>>>>>>> <lang...@fonz.dk> wrote: > >>>>>>>> > >>>>>>>>> sųndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > >>>>>>>>>> It strikes me that John Larkin's original idea of synthesising > >>>>>>>>>> trapezoids can be made to work. > >>>>>>>>>> > >>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you > >>>>>>>>>> fed into your comparator would be made up of four sequential > >>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary > >>>>>>>>>> length, a falling edge, a low segment, and a risng edge > >>>>>>>>>> > >>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind > >>>>>>>>>> > >>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf > >>>>>>>>>> > >>>>>>>>>> > >>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as > >>>>>>>>>> 16-successive steps of a staircase waveform. > >>>>>>>>> > >>>>>>>>> since it is for a trigger and the falling edge probably doesn't > >>>>>>>>> matter, why not a single variable voltage step into a filter, sorta > >>>>>>>>> like a time-to-amplitude in reverse > >>>>>>>> > >>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform > >>>>>>>> to make a faster edge into a filter and comparator, to get better time > >>>>>>>> resolution, less jitter, at low frequencies. > >>>>>>> > >>>>>>> I am only curious if I understand what you are after - is it some sort > >>>>>>> of "the larger the step the less low pass I want applied to it"? > >>>>>> > >>>>>> When synthesizing a low frequency DDS sine wave, we step slowly > >>>>>> through the waveform lookup table and a fixed filter doesn't > >>>>>> interpolate waveform steps any more; it settles every step. > >>>>>> > >>>>>> So, is there a better waveform to use at low frequencies? > >>>>>> > >>>>> > >>>>> Hmmm. I get it now (though I don't get why this is a problem, > >>>>> likely specific to your application). I don't know how one > >>>>> waveform would be better for you that another, don't know > >>>>> what it is you are doing (perhaps you said and I missed it, > >>>>> I am not following closely). > >>>>> A pretty complex way of dealing with the steps at low frequencies > >>>>> is perhaps to have two DACs, one of them making the output filter > >>>>> programmable so you can dynamically change it, based on step, > >>>>> with some preemption etc., you get the idea - and I am not sure > >>>>> it is practical, not only because it is complex but also because > >>>>> I have never done this, I am just musing. > >>>> > >>>> I missed the "we step slowly" in your post, now I get it. > >>>> Well, the simplest way out is to step at a constant rate all the > >>>> time. > >>> > >>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > >>> needs a sine lookup table with about 50 billion entries. And an > >>> equally impossible DAC and comparator. > >>> > >>> We'll probably wind up synthesizing the high range, an octave or so, > >>> and divide down as needed. The trick will be to make the gear shifts > >>> appear to be seamless. > >>> > >>> That could get interesting. > >>> > >> > >>I still don't understand what you are trying to do. Periodic sine > >>wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > >>wave lookup table for the slowest case. If you want to switch by > >>operator action you have milliseconds of time to recalculate the table. > >>If you want to switch by some external gating you only need two > >>tables to switch between, this makes up to 200 entries. > >>This is all way too simple and obvious so you must be after something > >>more than that - which I haven't got yet. > > > >I just want a programmable-frequency trigger generator that changes > >frequency on demand and doesn't stop for reprogramming and doesn't > >blow up someone's laser by generating any goofy triggers. In other > >words, goes smoothly from F1 to F2. > > > >With low period jitter from, say, 1 mHz to 15 Mhz. > > > >mHz resolution is good too. > I guess I'm not seeing the problem. Ordinary DDS units with 48-bit > accumulators can do just this, with phase continuity between the two > frequencies, so no glitches. People implement arbitrary > frequency-keyed waveforms this way. > > The phase to trig converter typically uses only the upper 10 to 14 > bits of the 48-bit accumulator. Converter implementations vary: > table-lookup and CORDIC being very common approaches. > > Perhaps it's time to bring the various discussion threads together and > re-focus by restating the problem to be solved.https://imgur.com/GwZ2q8A stepping through a sine table at F and 8*F much exaggerated by short sine table and low resolution
Reply by ●August 16, 20222022-08-16
tirsdag den 16. august 2022 kl. 20.32.22 UTC+2 skrev John Larkin:> On Tue, 16 Aug 2022 13:46:32 -0400, Joe Gwinn <joeg...@comcast.net> > wrote: > > >On Mon, 15 Aug 2022 19:26:28 -0700, jla...@highlandsniptechnology.com > >wrote: > > > >>On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>wrote: > >> > >>>On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: > >>>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>>> wrote: > >>>> > >>>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: > >>>>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > >>>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>>>>>> wrote: > >>>>>>> > >>>>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >>>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen > >>>>>>>>> <lang...@fonz.dk> wrote: > >>>>>>>>> > >>>>>>>>>> sųndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > >>>>>>>>>>> It strikes me that John Larkin's original idea of synthesising > >>>>>>>>>>> trapezoids can be made to work. > >>>>>>>>>>> > >>>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you > >>>>>>>>>>> fed into your comparator would be made up of four sequential > >>>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary > >>>>>>>>>>> length, a falling edge, a low segment, and a risng edge > >>>>>>>>>>> > >>>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind > >>>>>>>>>>> > >>>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf > >>>>>>>>>>> > >>>>>>>>>>> > >>>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as > >>>>>>>>>>> 16-successive steps of a staircase waveform. > >>>>>>>>>> > >>>>>>>>>> since it is for a trigger and the falling edge probably doesn't > >>>>>>>>>> matter, why not a single variable voltage step into a filter, sorta > >>>>>>>>>> like a time-to-amplitude in reverse > >>>>>>>>> > >>>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform > >>>>>>>>> to make a faster edge into a filter and comparator, to get better time > >>>>>>>>> resolution, less jitter, at low frequencies. > >>>>>>>> > >>>>>>>> I am only curious if I understand what you are after - is it some sort > >>>>>>>> of "the larger the step the less low pass I want applied to it"? > >>>>>>> > >>>>>>> When synthesizing a low frequency DDS sine wave, we step slowly > >>>>>>> through the waveform lookup table and a fixed filter doesn't > >>>>>>> interpolate waveform steps any more; it settles every step. > >>>>>>> > >>>>>>> So, is there a better waveform to use at low frequencies? > >>>>>>> > >>>>>> > >>>>>> Hmmm. I get it now (though I don't get why this is a problem, > >>>>>> likely specific to your application). I don't know how one > >>>>>> waveform would be better for you that another, don't know > >>>>>> what it is you are doing (perhaps you said and I missed it, > >>>>>> I am not following closely). > >>>>>> A pretty complex way of dealing with the steps at low frequencies > >>>>>> is perhaps to have two DACs, one of them making the output filter > >>>>>> programmable so you can dynamically change it, based on step, > >>>>>> with some preemption etc., you get the idea - and I am not sure > >>>>>> it is practical, not only because it is complex but also because > >>>>>> I have never done this, I am just musing. > >>>>> > >>>>> I missed the "we step slowly" in your post, now I get it. > >>>>> Well, the simplest way out is to step at a constant rate all the > >>>>> time. > >>>> > >>>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > >>>> needs a sine lookup table with about 50 billion entries. And an > >>>> equally impossible DAC and comparator. > >>>> > >>>> We'll probably wind up synthesizing the high range, an octave or so, > >>>> and divide down as needed. The trick will be to make the gear shifts > >>>> appear to be seamless. > >>>> > >>>> That could get interesting. > >>>> > >>> > >>>I still don't understand what you are trying to do. Periodic sine > >>>wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > >>>wave lookup table for the slowest case. If you want to switch by > >>>operator action you have milliseconds of time to recalculate the table. > >>>If you want to switch by some external gating you only need two > >>>tables to switch between, this makes up to 200 entries. > >>>This is all way too simple and obvious so you must be after something > >>>more than that - which I haven't got yet. > >> > >>I just want a programmable-frequency trigger generator that changes > >>frequency on demand and doesn't stop for reprogramming and doesn't > >>blow up someone's laser by generating any goofy triggers. In other > >>words, goes smoothly from F1 to F2. > >> > >>With low period jitter from, say, 1 mHz to 15 Mhz. > >> > >>mHz resolution is good too. > > > >I guess I'm not seeing the problem. Ordinary DDS units with 48-bit > >accumulators can do just this, with phase continuity between the two > >frequencies, so no glitches. People implement arbitrary > >frequency-keyed waveforms this way. > > > >The phase to trig converter typically uses only the upper 10 to 14 > >bits of the 48-bit accumulator. Converter implementations vary: > >table-lookup and CORDIC being very common approaches. > > > One problem is that, at low frequencies, the LSB of that 10 to 14 bits > changes infrequently and the lowpass filter doesn't interpolate > multiple points any more. So one gets a lot of period jitter > >Perhaps it's time to bring the various discussion threads together and > >re-focus by restating the problem to be solved. > I've stated it a few times: We want a perfect, programmable, > glitch-free, always right, low period jitter trigger clock. > > It's an interesting problem.https://imgur.com/6KqpCW9
Reply by ●August 16, 20222022-08-16
On Tuesday, August 16, 2022 at 1:46:45 PM UTC-4, Joe Gwinn wrote:> On Mon, 15 Aug 2022 19:26:28 -0700, jla...@highlandsniptechnology.com > wrote: > > >On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >wrote: > > > >>On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: > >>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>> wrote: > >>> > >>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: > >>>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > >>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>>>>> wrote: > >>>>>> > >>>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen > >>>>>>>> <lang...@fonz.dk> wrote: > >>>>>>>> > >>>>>>>>> sųndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > >>>>>>>>>> It strikes me that John Larkin's original idea of synthesising > >>>>>>>>>> trapezoids can be made to work. > >>>>>>>>>> > >>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you > >>>>>>>>>> fed into your comparator would be made up of four sequential > >>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary > >>>>>>>>>> length, a falling edge, a low segment, and a risng edge > >>>>>>>>>> > >>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind > >>>>>>>>>> > >>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf > >>>>>>>>>> > >>>>>>>>>> > >>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as > >>>>>>>>>> 16-successive steps of a staircase waveform. > >>>>>>>>> > >>>>>>>>> since it is for a trigger and the falling edge probably doesn't > >>>>>>>>> matter, why not a single variable voltage step into a filter, sorta > >>>>>>>>> like a time-to-amplitude in reverse > >>>>>>>> > >>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform > >>>>>>>> to make a faster edge into a filter and comparator, to get better time > >>>>>>>> resolution, less jitter, at low frequencies. > >>>>>>> > >>>>>>> I am only curious if I understand what you are after - is it some sort > >>>>>>> of "the larger the step the less low pass I want applied to it"? > >>>>>> > >>>>>> When synthesizing a low frequency DDS sine wave, we step slowly > >>>>>> through the waveform lookup table and a fixed filter doesn't > >>>>>> interpolate waveform steps any more; it settles every step. > >>>>>> > >>>>>> So, is there a better waveform to use at low frequencies? > >>>>>> > >>>>> > >>>>> Hmmm. I get it now (though I don't get why this is a problem, > >>>>> likely specific to your application). I don't know how one > >>>>> waveform would be better for you that another, don't know > >>>>> what it is you are doing (perhaps you said and I missed it, > >>>>> I am not following closely). > >>>>> A pretty complex way of dealing with the steps at low frequencies > >>>>> is perhaps to have two DACs, one of them making the output filter > >>>>> programmable so you can dynamically change it, based on step, > >>>>> with some preemption etc., you get the idea - and I am not sure > >>>>> it is practical, not only because it is complex but also because > >>>>> I have never done this, I am just musing. > >>>> > >>>> I missed the "we step slowly" in your post, now I get it. > >>>> Well, the simplest way out is to step at a constant rate all the > >>>> time. > >>> > >>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > >>> needs a sine lookup table with about 50 billion entries. And an > >>> equally impossible DAC and comparator. > >>> > >>> We'll probably wind up synthesizing the high range, an octave or so, > >>> and divide down as needed. The trick will be to make the gear shifts > >>> appear to be seamless. > >>> > >>> That could get interesting. > >>> > >> > >>I still don't understand what you are trying to do. Periodic sine > >>wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > >>wave lookup table for the slowest case. If you want to switch by > >>operator action you have milliseconds of time to recalculate the table. > >>If you want to switch by some external gating you only need two > >>tables to switch between, this makes up to 200 entries. > >>This is all way too simple and obvious so you must be after something > >>more than that - which I haven't got yet. > > > >I just want a programmable-frequency trigger generator that changes > >frequency on demand and doesn't stop for reprogramming and doesn't > >blow up someone's laser by generating any goofy triggers. In other > >words, goes smoothly from F1 to F2. > > > >With low period jitter from, say, 1 mHz to 15 Mhz. > > > >mHz resolution is good too. > I guess I'm not seeing the problem. Ordinary DDS units with 48-bit > accumulators can do just this, with phase continuity between the two > frequencies, so no glitches. People implement arbitrary > frequency-keyed waveforms this way. > > The phase to trig converter typically uses only the upper 10 to 14 > bits of the 48-bit accumulator. Converter implementations vary: > table-lookup and CORDIC being very common approaches. > > Perhaps it's time to bring the various discussion threads together and > re-focus by restating the problem to be solved.Or maybe someone could just read how it has been done for over a decade. This is all well traveled ground. I see people now repeating things I said days ago. The DDS should be designed to generate a top frequency over a 2:1 range. This is easy stuff, with good accuracy and very low jitter if properly designed (use of a long phase word). A programmable divider then divides by 2**N by counting up to the set value. A final FF buffer register of your favorite technology will provide the actual pulse output with an appropriate jitter. These two units can both be changed on a single clock cycle by writing to a buffer register and updating the actual operational registers simultaneously on a cue. The DDS will continue from the present phase, so will produce one clock pulse that is an intermediate period. The programmable divider will continue from the current count, either triggering right away, or continuing to count from the present value. Either way it will always produce an output pulse that is within the range of the two settings, the prior setting and the new setting. -- Rick C. +- Get 1,000 miles of free Supercharging +- Tesla referral code - https://ts.la/richard11209
Reply by ●August 16, 20222022-08-16
On Wednesday, August 17, 2022 at 4:32:22 AM UTC+10, John Larkin wrote:> On Tue, 16 Aug 2022 13:46:32 -0400, Joe Gwinn <joeg...@comcast.net> > wrote: > > >On Mon, 15 Aug 2022 19:26:28 -0700, jla...@highlandsniptechnology.com > >wrote: > > > >>On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>wrote: > >> > >>>On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: > >>>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>>> wrote: > >>>> > >>>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: > >>>>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > >>>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>>>>>> wrote: > >>>>>>> > >>>>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >>>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen > >>>>>>>>> <lang...@fonz.dk> wrote: > >>>>>>>>> > >>>>>>>>>> sųndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > >>>>>>>>>>> It strikes me that John Larkin's original idea of synthesising > >>>>>>>>>>> trapezoids can be made to work. > >>>>>>>>>>> > >>>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you > >>>>>>>>>>> fed into your comparator would be made up of four sequential > >>>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary > >>>>>>>>>>> length, a falling edge, a low segment, and a risng edge > >>>>>>>>>>> > >>>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind > >>>>>>>>>>> > >>>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf > >>>>>>>>>>> > >>>>>>>>>>> > >>>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as > >>>>>>>>>>> 16-successive steps of a staircase waveform. > >>>>>>>>>> > >>>>>>>>>> since it is for a trigger and the falling edge probably doesn't > >>>>>>>>>> matter, why not a single variable voltage step into a filter, sorta > >>>>>>>>>> like a time-to-amplitude in reverse > >>>>>>>>> > >>>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform > >>>>>>>>> to make a faster edge into a filter and comparator, to get better time > >>>>>>>>> resolution, less jitter, at low frequencies. > >>>>>>>> > >>>>>>>> I am only curious if I understand what you are after - is it some sort > >>>>>>>> of "the larger the step the less low pass I want applied to it"? > >>>>>>> > >>>>>>> When synthesizing a low frequency DDS sine wave, we step slowly > >>>>>>> through the waveform lookup table and a fixed filter doesn't > >>>>>>> interpolate waveform steps any more; it settles every step. > >>>>>>> > >>>>>>> So, is there a better waveform to use at low frequencies? > >>>>>>> > >>>>>> > >>>>>> Hmmm. I get it now (though I don't get why this is a problem, > >>>>>> likely specific to your application). I don't know how one > >>>>>> waveform would be better for you that another, don't know > >>>>>> what it is you are doing (perhaps you said and I missed it, > >>>>>> I am not following closely). > >>>>>> A pretty complex way of dealing with the steps at low frequencies > >>>>>> is perhaps to have two DACs, one of them making the output filter > >>>>>> programmable so you can dynamically change it, based on step, > >>>>>> with some preemption etc., you get the idea - and I am not sure > >>>>>> it is practical, not only because it is complex but also because > >>>>>> I have never done this, I am just musing. > >>>>> > >>>>> I missed the "we step slowly" in your post, now I get it. > >>>>> Well, the simplest way out is to step at a constant rate all the > >>>>> time. > >>>> > >>>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > >>>> needs a sine lookup table with about 50 billion entries. And an > >>>> equally impossible DAC and comparator. > >>>> > >>>> We'll probably wind up synthesizing the high range, an octave or so, > >>>> and divide down as needed. The trick will be to make the gear shifts > >>>> appear to be seamless. > >>>> > >>>> That could get interesting. > >>>> > >>> > >>>I still don't understand what you are trying to do. Periodic sine > >>>wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > >>>wave lookup table for the slowest case. If you want to switch by > >>>operator action you have milliseconds of time to recalculate the table. > >>>If you want to switch by some external gating you only need two > >>>tables to switch between, this makes up to 200 entries. > >>>This is all way too simple and obvious so you must be after something > >>>more than that - which I haven't got yet. > >> > >>I just want a programmable-frequency trigger generator that changes > >>frequency on demand and doesn't stop for reprogramming and doesn't > >>blow up someone's laser by generating any goofy triggers. In other > >>words, goes smoothly from F1 to F2. > >> > >>With low period jitter from, say, 1 mHz to 15 Mhz. > >> > >>mHz resolution is good too. > > > >I guess I'm not seeing the problem. Ordinary DDS units with 48-bit > >accumulators can do just this, with phase continuity between the two > >frequencies, so no glitches. People implement arbitrary > >frequency-keyed waveforms this way. > > > >The phase to trig converter typically uses only the upper 10 to 14 > >bits of the 48-bit accumulator. Converter implementations vary: > >table-lookup and CORDIC being very common approaches. > > > One problem is that, at low frequencies, the LSB of that 10 to 14 bits > changes infrequently and the lowpass filter doesn't interpolate > multiple points any more. So one gets a lot of period jitter.But you can solve that by synthesising a trapezium wave rather than a sine wave, and sticking to a constant slope for the sloped bits of the trapezium wave.> >Perhaps it's time to bring the various discussion threads together and re-focus by restating the problem to be solved. > > I've stated it a few times: We want a perfect, programmable, > glitch-free, always right, low period jitter trigger clock.Not to mention motherhood and apple pie. A trigger clock that is always right can never be reprogrammed, because it's going to be wrong until the newly programmed frequency has been established, You don't want to think about what you are asking for.> It's an interesting problem.In the same sense as the sound of one hand clapping. -- Bill Sloman, Sydney
Reply by ●August 17, 20222022-08-17
On Tue, 16 Aug 2022 11:50:57 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>tirsdag den 16. august 2022 kl. 19.46.45 UTC+2 skrev Joe Gwinn: >> On Mon, 15 Aug 2022 19:26:28 -0700, jla...@highlandsniptechnology.com >> wrote: >> >> >On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <d...@tgi-sci.com> >> >wrote: >> > >> >>On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: >> >>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> >> >>> wrote: >> >>> >> >>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: >> >>>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: >> >>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> >> >>>>>> wrote: >> >>>>>> >> >>>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: >> >>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >> >>>>>>>> <lang...@fonz.dk> wrote: >> >>>>>>>> >> >>>>>>>>> s?ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >> >>>>>>>>>> It strikes me that John Larkin's original idea of synthesising >> >>>>>>>>>> trapezoids can be made to work. >> >>>>>>>>>> >> >>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you >> >>>>>>>>>> fed into your comparator would be made up of four sequential >> >>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary >> >>>>>>>>>> length, a falling edge, a low segment, and a risng edge >> >>>>>>>>>> >> >>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind >> >>>>>>>>>> >> >>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >> >>>>>>>>>> >> >>>>>>>>>> >> >>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as >> >>>>>>>>>> 16-successive steps of a staircase waveform. >> >>>>>>>>> >> >>>>>>>>> since it is for a trigger and the falling edge probably doesn't >> >>>>>>>>> matter, why not a single variable voltage step into a filter, sorta >> >>>>>>>>> like a time-to-amplitude in reverse >> >>>>>>>> >> >>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform >> >>>>>>>> to make a faster edge into a filter and comparator, to get better time >> >>>>>>>> resolution, less jitter, at low frequencies. >> >>>>>>> >> >>>>>>> I am only curious if I understand what you are after - is it some sort >> >>>>>>> of "the larger the step the less low pass I want applied to it"? >> >>>>>> >> >>>>>> When synthesizing a low frequency DDS sine wave, we step slowly >> >>>>>> through the waveform lookup table and a fixed filter doesn't >> >>>>>> interpolate waveform steps any more; it settles every step. >> >>>>>> >> >>>>>> So, is there a better waveform to use at low frequencies? >> >>>>>> >> >>>>> >> >>>>> Hmmm. I get it now (though I don't get why this is a problem, >> >>>>> likely specific to your application). I don't know how one >> >>>>> waveform would be better for you that another, don't know >> >>>>> what it is you are doing (perhaps you said and I missed it, >> >>>>> I am not following closely). >> >>>>> A pretty complex way of dealing with the steps at low frequencies >> >>>>> is perhaps to have two DACs, one of them making the output filter >> >>>>> programmable so you can dynamically change it, based on step, >> >>>>> with some preemption etc., you get the idea - and I am not sure >> >>>>> it is practical, not only because it is complex but also because >> >>>>> I have never done this, I am just musing. >> >>>> >> >>>> I missed the "we step slowly" in your post, now I get it. >> >>>> Well, the simplest way out is to step at a constant rate all the >> >>>> time. >> >>> >> >>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That >> >>> needs a sine lookup table with about 50 billion entries. And an >> >>> equally impossible DAC and comparator. >> >>> >> >>> We'll probably wind up synthesizing the high range, an octave or so, >> >>> and divide down as needed. The trick will be to make the gear shifts >> >>> appear to be seamless. >> >>> >> >>> That could get interesting. >> >>> >> >> >> >>I still don't understand what you are trying to do. Periodic sine >> >>wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >> >>wave lookup table for the slowest case. If you want to switch by >> >>operator action you have milliseconds of time to recalculate the table. >> >>If you want to switch by some external gating you only need two >> >>tables to switch between, this makes up to 200 entries. >> >>This is all way too simple and obvious so you must be after something >> >>more than that - which I haven't got yet. >> > >> >I just want a programmable-frequency trigger generator that changes >> >frequency on demand and doesn't stop for reprogramming and doesn't >> >blow up someone's laser by generating any goofy triggers. In other >> >words, goes smoothly from F1 to F2. >> > >> >With low period jitter from, say, 1 mHz to 15 Mhz. >> > >> >mHz resolution is good too. >> I guess I'm not seeing the problem. Ordinary DDS units with 48-bit >> accumulators can do just this, with phase continuity between the two >> frequencies, so no glitches. People implement arbitrary >> frequency-keyed waveforms this way. >> >> The phase to trig converter typically uses only the upper 10 to 14 >> bits of the 48-bit accumulator. Converter implementations vary: >> table-lookup and CORDIC being very common approaches. >> >> Perhaps it's time to bring the various discussion threads together and >> re-focus by restating the problem to be solved. > >https://imgur.com/GwZ2q8A > >stepping through a sine table at F and 8*F >much exaggerated by short sine table and low resolution > > >One could think of clusters of bits as harmonic terms in a Fourier series. A bit of grouping and scaling and adding could reshape a sine into something more square. That's hard to think about too. Bummer is, a DDS doesn't generally step one tick at a time. In fact, it's a mess. https://www.dropbox.com/s/1xx7sz1e5rg6jsi/JLDDS_100M_4K.jpg?raw=1 and it's very different at low frequencies.
