mandag den 15. august 2022 kl. 17.25.26 UTC+2 skrev bill....@ieee.org:> On Tuesday, August 16, 2022 at 12:17:56 AM UTC+10, jla...@highlandsniptechnology.com wrote: > > On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com wrote: > > >On 8/15/2022 1:41, Dimiter_Popoff wrote: > > >> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > > >>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> wrote: > > >>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > > >>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote: > > >>>>>> søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > <snip> > > I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > > needs a sine lookup table with about 50 billion entries. > Only if you chose to do that way. You could rewrite the look-up table every time you changed the frequency. > > And an equally impossible DAC and comparator. > So think it out again. > > We'll probably wind up synthesizing the high range, an octave or so, > > and divide down as needed. The trick will be to make the gear shifts > > appear to be seamless. > What's difficult about that? It isn't as if there are any moving parts involved. The customer needs to tell you the frequency they want the machine to push out, and you need to be able to reconfigure it so that is the frequency which comes out.but what happens when you change from one frequency to another?
Direct digital synthesis of square waves
Started by ●August 14, 2022
Reply by ●August 15, 20222022-08-15
Reply by ●August 15, 20222022-08-15
On Monday, August 15, 2022 at 10:17:56 AM UTC-4, jla...@highlandsniptechnology.com wrote:> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> > wrote: > > >On 8/15/2022 1:41, Dimiter_Popoff wrote: > >> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > >>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>> wrote: > >>> > >>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen > >>>>> <lang...@fonz.dk> wrote: > >>>>> > >>>>>> søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > >>>>>>> It strikes me that John Larkin's original idea of synthesising > >>>>>>> trapezoids can be made to work. > >>>>>>> > >>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you > >>>>>>> fed into your comparator would be made up of four sequential > >>>>>>> components - all coming out of the DAC - high segment of arbitrary > >>>>>>> length, a falling edge, a low segment, and a risng edge > >>>>>>> > >>>>>>> With a 14-bit DAC - the LTC2000 comes to mind > >>>>>>> > >>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf > >>>>>>> > >>>>>>> > >>>>>>> you'd synthisese the rising and falling edges of the trapezia as > >>>>>>> 16-successive steps of a staircase waveform. > >>>>>> > >>>>>> since it is for a trigger and the falling edge probably doesn't > >>>>>> matter, why not a single variable voltage step into a filter, sorta > >>>>>> like a time-to-amplitude in reverse > >>>>> > >>>>> My question is basically whether one can DDS a non-sinusoidal waveform > >>>>> to make a faster edge into a filter and comparator, to get better time > >>>>> resolution, less jitter, at low frequencies. > >>>> > >>>> I am only curious if I understand what you are after - is it some sort > >>>> of "the larger the step the less low pass I want applied to it"? > >>> > >>> When synthesizing a low frequency DDS sine wave, we step slowly > >>> through the waveform lookup table and a fixed filter doesn't > >>> interpolate waveform steps any more; it settles every step. > >>> > >>> So, is there a better waveform to use at low frequencies? > >>> > >> > >> Hmmm. I get it now (though I don't get why this is a problem, > >> likely specific to your application). I don't know how one > >> waveform would be better for you that another, don't know > >> what it is you are doing (perhaps you said and I missed it, > >> I am not following closely). > >> A pretty complex way of dealing with the steps at low frequencies > >> is perhaps to have two DACs, one of them making the output filter > >> programmable so you can dynamically change it, based on step, > >> with some preemption etc., you get the idea - and I am not sure > >> it is practical, not only because it is complex but also because > >> I have never done this, I am just musing. > > > >I missed the "we step slowly" in your post, now I get it. > >Well, the simplest way out is to step at a constant rate all the > >time. > I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > needs a sine lookup table with about 50 billion entries. And an > equally impossible DAC and comparator. > > We'll probably wind up synthesizing the high range, an octave or so, > and divide down as needed. The trick will be to make the gear shifts > appear to be seamless. > > That could get interesting.A single, large lookup table is not the only way to generate a sine function. This is one of the problems with trying to brain storm a complex task rather than to research it and learn how the problem has been solved in the past. sin (a+b) = sin (a) * cos(b) + cos(a) * sin(b), where a and b are the msbs and lsbs of the phase counter. Because b is always very small, cos(b) is always very close to 1. sin(b) will always be small, so sin(a) is a reasonable approximation to that term. sin(b) * cos(a) can be a table lookup with less than the full value of a used. With two tables, the result can be calculated with a single addition. This was used in a very early device where memory was much more limited than today. Or if you are religious, and don't want to lose any precision, it is not hard to do the full precision math in an FPGA, still with much smaller look up tables. In a DDS, your result will still be limited by the size of your DAC, but 16 bits is not unreasonable. To avoid messiness at the changes, you can construct the DDS in an FPGA and handle the changes so that the octave change is made when the DDS is set to the slower of the two DDS settings. You can also stop the DDS, make all changes, then resume the DDS. If this is done within the FPGA, there will be no glitches. The octave counters can be reset during the process, eliminating any spurious pulse widths. The method that works best for a given frequency transition can be used. It doesn't need to be a one-size-fits-all approach. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
Reply by ●August 15, 20222022-08-15
On Monday, August 15, 2022 at 11:35:21 AM UTC-4, lang...@fonz.dk wrote:> mandag den 15. august 2022 kl. 17.25.26 UTC+2 skrev bill....@ieee.org: > > On Tuesday, August 16, 2022 at 12:17:56 AM UTC+10, jla...@highlandsniptechnology.com wrote: > > > On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com wrote: > > > >On 8/15/2022 1:41, Dimiter_Popoff wrote: > > > >> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > > > >>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> wrote: > > > >>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > > > >>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote: > > > >>>>>> søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > > <snip> > > > I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > > > needs a sine lookup table with about 50 billion entries. > > Only if you chose to do that way. You could rewrite the look-up table every time you changed the frequency. > > > And an equally impossible DAC and comparator. > > So think it out again. > > > We'll probably wind up synthesizing the high range, an octave or so, > > > and divide down as needed. The trick will be to make the gear shifts > > > appear to be seamless. > > What's difficult about that? It isn't as if there are any moving parts involved. The customer needs to tell you the frequency they want the machine to push out, and you need to be able to reconfigure it so that is the frequency which comes out. > but what happens when you change from one frequency to another?Uh, the output frequency changes? -- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209
Reply by ●August 15, 20222022-08-15
On Mon, 15 Aug 2022 08:35:17 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>mandag den 15. august 2022 kl. 17.25.26 UTC+2 skrev bill....@ieee.org: >> On Tuesday, August 16, 2022 at 12:17:56 AM UTC+10, jla...@highlandsniptechnology.com wrote: >> > On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com wrote: >> > >On 8/15/2022 1:41, Dimiter_Popoff wrote: >> > >> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: >> > >>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> wrote: >> > >>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: >> > >>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote: >> > >>>>>> s�ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >> <snip> >> > I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That >> > needs a sine lookup table with about 50 billion entries. >> Only if you chose to do that way. You could rewrite the look-up table every time you changed the frequency. >> > And an equally impossible DAC and comparator. >> So think it out again. >> > We'll probably wind up synthesizing the high range, an octave or so, >> > and divide down as needed. The trick will be to make the gear shifts >> > appear to be seamless. >> What's difficult about that? It isn't as if there are any moving parts involved. The customer needs to tell you the frequency they want the machine to push out, and you need to be able to reconfigure it so that is the frequency which comes out. > >but what happens when you change from one frequency to another? > >There are dilemmas. What exactly do you do when the frequency was 1 mHz, and you are 500 seconds from a trigger, and the user sets the rate to 10 Hz? How about the reverse? What do you do if the requested transition was from 1 Hz to 0.99 Hz?
Reply by ●August 15, 20222022-08-15
On Monday, August 15, 2022 at 1:07:03 PM UTC-4, jla...@highlandsniptechnology.com wrote:> On Mon, 15 Aug 2022 08:35:17 -0700 (PDT), Lasse Langwadt Christensen > <lang...@fonz.dk> wrote: > > >mandag den 15. august 2022 kl. 17.25.26 UTC+2 skrev bill....@ieee.org: > >> On Tuesday, August 16, 2022 at 12:17:56 AM UTC+10, jla...@highlandsniptechnology.com wrote: > >> > On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com wrote: > >> > >On 8/15/2022 1:41, Dimiter_Popoff wrote: > >> > >> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > >> > >>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> wrote: > >> > >>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >> > >>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote: > >> > >>>>>> søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > >> <snip> > >> > I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > >> > needs a sine lookup table with about 50 billion entries. > >> Only if you chose to do that way. You could rewrite the look-up table every time you changed the frequency. > >> > And an equally impossible DAC and comparator. > >> So think it out again. > >> > We'll probably wind up synthesizing the high range, an octave or so, > >> > and divide down as needed. The trick will be to make the gear shifts > >> > appear to be seamless. > >> What's difficult about that? It isn't as if there are any moving parts involved. The customer needs to tell you the frequency they want the machine to push out, and you need to be able to reconfigure it so that is the frequency which comes out. > > > >but what happens when you change from one frequency to another? > > > > > There are dilemmas. What exactly do you do when the frequency was 1 > mHz, and you are 500 seconds from a trigger, and the user sets the > rate to 10 Hz? > > How about the reverse? > > What do you do if the requested transition was from 1 Hz to 0.99 Hz?I would always stop the pulse generation during the settings change. The changeover can happen in one clock cycle of your master clock, so the circuit will resume with very little delay. The filter will be the slow part of the whole thing. The worst case delay from frequency change will be one new period. Are you adding new requirements, that the delay between previous clock output and next clock output must always be within the range of the two settings? If so, then the actual change should be triggered off the output clock. It would result in a delay until the change of up to one old clock period. Have you asked your customer how they would like for these cases to be handled? -- Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209
Reply by ●August 15, 20222022-08-15
On Monday, August 15, 2022 at 1:18:51 PM UTC-4, Ricky wrote:> On Monday, August 15, 2022 at 1:07:03 PM UTC-4, jla...@highlandsniptechnology.com wrote: > > On Mon, 15 Aug 2022 08:35:17 -0700 (PDT), Lasse Langwadt Christensen > > <lang...@fonz.dk> wrote: > > > > >mandag den 15. august 2022 kl. 17.25.26 UTC+2 skrev bill....@ieee.org: > > >> On Tuesday, August 16, 2022 at 12:17:56 AM UTC+10, jla...@highlandsniptechnology.com wrote: > > >> > On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com wrote: > > >> > >On 8/15/2022 1:41, Dimiter_Popoff wrote: > > >> > >> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > > >> > >>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> wrote: > > >> > >>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > > >> > >>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote: > > >> > >>>>>> søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > > >> <snip> > > >> > I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > > >> > needs a sine lookup table with about 50 billion entries. > > >> Only if you chose to do that way. You could rewrite the look-up table every time you changed the frequency. > > >> > And an equally impossible DAC and comparator. > > >> So think it out again. > > >> > We'll probably wind up synthesizing the high range, an octave or so, > > >> > and divide down as needed. The trick will be to make the gear shifts > > >> > appear to be seamless. > > >> What's difficult about that? It isn't as if there are any moving parts involved. The customer needs to tell you the frequency they want the machine to push out, and you need to be able to reconfigure it so that is the frequency which comes out. > > > > > >but what happens when you change from one frequency to another? > > > > > > > > There are dilemmas. What exactly do you do when the frequency was 1 > > mHz, and you are 500 seconds from a trigger, and the user sets the > > rate to 10 Hz? > > > > How about the reverse? > > > > What do you do if the requested transition was from 1 Hz to 0.99 Hz? > I would always stop the pulse generation during the settings change. The changeover can happen in one clock cycle of your master clock, so the circuit will resume with very little delay. The filter will be the slow part of the whole thing. The worst case delay from frequency change will be one new period. > > Are you adding new requirements, that the delay between previous clock output and next clock output must always be within the range of the two settings? If so, then the actual change should be triggered off the output clock. It would result in a delay until the change of up to one old clock period. > > Have you asked your customer how they would like for these cases to be handled?Actually, this is an easy one to solve. I was picturing a fixed counter and selecting taps. But instead, use a programmable counter which is reset to zero and counts up to a threshold. If you change the threshold to a larger value, the counter continues counting up until the new threshold. If you change the threshold to a lower value, the counter will either continue counting up to the new threshold, or if it has already been passed, immediately reset and generate a clock edge. This combination of a DDS and a programmable divider can give very good results as shown in many applications. -- Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209
Reply by ●August 15, 20222022-08-15
On 8/15/2022 17:17, jlarkin@highlandsniptechnology.com wrote:> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <dp@tgi-sci.com> > wrote: > >> On 8/15/2022 1:41, Dimiter_Popoff wrote: >>> On 8/15/2022 1:08, jlarkin@highlandsniptechnology.com wrote: >>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>>> wrote: >>>> >>>>> On 8/14/2022 17:14, jlarkin@highlandsniptechnology.com wrote: >>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >>>>>> <langwadt@fonz.dk> wrote: >>>>>> >>>>>>> søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >>>>>>>> It strikes me that John Larkin's original idea of synthesising >>>>>>>> trapezoids can be made to work. >>>>>>>> >>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you >>>>>>>> fed into your comparator would be made up of four sequential >>>>>>>> components - all coming out of the DAC - high segment of arbitrary >>>>>>>> length, a falling edge, a low segment, and a risng edge >>>>>>>> >>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind >>>>>>>> >>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >>>>>>>> >>>>>>>> >>>>>>>> you'd synthisese the rising and falling edges of the trapezia as >>>>>>>> 16-successive steps of a staircase waveform. >>>>>>> >>>>>>> since it is for a trigger and the falling edge probably doesn't >>>>>>> matter, why not a single variable voltage step into a filter, sorta >>>>>>> like a time-to-amplitude in reverse >>>>>> >>>>>> My question is basically whether one can DDS a non-sinusoidal waveform >>>>>> to make a faster edge into a filter and comparator, to get better time >>>>>> resolution, less jitter, at low frequencies. >>>>> >>>>> I am only curious if I understand what you are after - is it some sort >>>>> of "the larger the step the less low pass I want applied to it"? >>>> >>>> When synthesizing a low frequency DDS sine wave, we step slowly >>>> through the waveform lookup table and a fixed filter doesn't >>>> interpolate waveform steps any more; it settles every step. >>>> >>>> So, is there a better waveform to use at low frequencies? >>>> >>> >>> Hmmm. I get it now (though I don't get why this is a problem, >>> likely specific to your application). I don't know how one >>> waveform would be better for you that another, don't know >>> what it is you are doing (perhaps you said and I missed it, >>> I am not following closely). >>> A pretty complex way of dealing with the steps at low frequencies >>> is perhaps to have two DACs, one of them making the output filter >>> programmable so you can dynamically change it, based on step, >>> with some preemption etc., you get the idea - and I am not sure >>> it is practical, not only because it is complex but also because >>> I have never done this, I am just musing. >> >> I missed the "we step slowly" in your post, now I get it. >> Well, the simplest way out is to step at a constant rate all the >> time. > > I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > needs a sine lookup table with about 50 billion entries. And an > equally impossible DAC and comparator. > > We'll probably wind up synthesizing the high range, an octave or so, > and divide down as needed. The trick will be to make the gear shifts > appear to be seamless. > > That could get interesting. >I still don't understand what you are trying to do. Periodic sine wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine wave lookup table for the slowest case. If you want to switch by operator action you have milliseconds of time to recalculate the table. If you want to switch by some external gating you only need two tables to switch between, this makes up to 200 entries. This is all way too simple and obvious so you must be after something more than that - which I haven't got yet.
Reply by ●August 15, 20222022-08-15
mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff:> On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: > > On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> > > wrote: > > > >> On 8/15/2022 1:41, Dimiter_Popoff wrote: > >>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > >>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>>> wrote: > >>>> > >>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen > >>>>>> <lang...@fonz.dk> wrote: > >>>>>> > >>>>>>> søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > >>>>>>>> It strikes me that John Larkin's original idea of synthesising > >>>>>>>> trapezoids can be made to work. > >>>>>>>> > >>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you > >>>>>>>> fed into your comparator would be made up of four sequential > >>>>>>>> components - all coming out of the DAC - high segment of arbitrary > >>>>>>>> length, a falling edge, a low segment, and a risng edge > >>>>>>>> > >>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind > >>>>>>>> > >>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf > >>>>>>>> > >>>>>>>> > >>>>>>>> you'd synthisese the rising and falling edges of the trapezia as > >>>>>>>> 16-successive steps of a staircase waveform. > >>>>>>> > >>>>>>> since it is for a trigger and the falling edge probably doesn't > >>>>>>> matter, why not a single variable voltage step into a filter, sorta > >>>>>>> like a time-to-amplitude in reverse > >>>>>> > >>>>>> My question is basically whether one can DDS a non-sinusoidal waveform > >>>>>> to make a faster edge into a filter and comparator, to get better time > >>>>>> resolution, less jitter, at low frequencies. > >>>>> > >>>>> I am only curious if I understand what you are after - is it some sort > >>>>> of "the larger the step the less low pass I want applied to it"? > >>>> > >>>> When synthesizing a low frequency DDS sine wave, we step slowly > >>>> through the waveform lookup table and a fixed filter doesn't > >>>> interpolate waveform steps any more; it settles every step. > >>>> > >>>> So, is there a better waveform to use at low frequencies? > >>>> > >>> > >>> Hmmm. I get it now (though I don't get why this is a problem, > >>> likely specific to your application). I don't know how one > >>> waveform would be better for you that another, don't know > >>> what it is you are doing (perhaps you said and I missed it, > >>> I am not following closely). > >>> A pretty complex way of dealing with the steps at low frequencies > >>> is perhaps to have two DACs, one of them making the output filter > >>> programmable so you can dynamically change it, based on step, > >>> with some preemption etc., you get the idea - and I am not sure > >>> it is practical, not only because it is complex but also because > >>> I have never done this, I am just musing. > >> > >> I missed the "we step slowly" in your post, now I get it. > >> Well, the simplest way out is to step at a constant rate all the > >> time. > > > > I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > > needs a sine lookup table with about 50 billion entries. And an > > equally impossible DAC and comparator. > > > > We'll probably wind up synthesizing the high range, an octave or so, > > and divide down as needed. The trick will be to make the gear shifts > > appear to be seamless. > > > > That could get interesting. > > > I still don't understand what you are trying to do. Periodic sine > wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > wave lookup table for the slowest case.only if you want neat frequencies that add up to 100M
Reply by ●August 15, 20222022-08-15
On 8/15/2022 22:56, Lasse Langwadt Christensen wrote:> mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff: >> On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: >>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> >>> wrote: >>> >>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: >>>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: >>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> >>>>>> wrote: >>>>>> >>>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: >>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>> <lang...@fonz.dk> wrote: >>>>>>>> >>>>>>>>> søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >>>>>>>>>> It strikes me that John Larkin's original idea of synthesising >>>>>>>>>> trapezoids can be made to work. >>>>>>>>>> >>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you >>>>>>>>>> fed into your comparator would be made up of four sequential >>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary >>>>>>>>>> length, a falling edge, a low segment, and a risng edge >>>>>>>>>> >>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind >>>>>>>>>> >>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as >>>>>>>>>> 16-successive steps of a staircase waveform. >>>>>>>>> >>>>>>>>> since it is for a trigger and the falling edge probably doesn't >>>>>>>>> matter, why not a single variable voltage step into a filter, sorta >>>>>>>>> like a time-to-amplitude in reverse >>>>>>>> >>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform >>>>>>>> to make a faster edge into a filter and comparator, to get better time >>>>>>>> resolution, less jitter, at low frequencies. >>>>>>> >>>>>>> I am only curious if I understand what you are after - is it some sort >>>>>>> of "the larger the step the less low pass I want applied to it"? >>>>>> >>>>>> When synthesizing a low frequency DDS sine wave, we step slowly >>>>>> through the waveform lookup table and a fixed filter doesn't >>>>>> interpolate waveform steps any more; it settles every step. >>>>>> >>>>>> So, is there a better waveform to use at low frequencies? >>>>>> >>>>> >>>>> Hmmm. I get it now (though I don't get why this is a problem, >>>>> likely specific to your application). I don't know how one >>>>> waveform would be better for you that another, don't know >>>>> what it is you are doing (perhaps you said and I missed it, >>>>> I am not following closely). >>>>> A pretty complex way of dealing with the steps at low frequencies >>>>> is perhaps to have two DACs, one of them making the output filter >>>>> programmable so you can dynamically change it, based on step, >>>>> with some preemption etc., you get the idea - and I am not sure >>>>> it is practical, not only because it is complex but also because >>>>> I have never done this, I am just musing. >>>> >>>> I missed the "we step slowly" in your post, now I get it. >>>> Well, the simplest way out is to step at a constant rate all the >>>> time. >>> >>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That >>> needs a sine lookup table with about 50 billion entries. And an >>> equally impossible DAC and comparator. >>> >>> We'll probably wind up synthesizing the high range, an octave or so, >>> and divide down as needed. The trick will be to make the gear shifts >>> appear to be seamless. >>> >>> That could get interesting. >>> >> I still don't understand what you are trying to do. Periodic sine >> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >> wave lookup table for the slowest case. > > only if you want neat frequencies that add up to 100M >I don't understand what a neat frequency is, either. Any periodic waveform at 1 MHz (the worst case) at 100 Msps update rate takes a 100 entry table.
Reply by ●August 15, 20222022-08-15
On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote:> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: > > mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff:> >> I still don't understand what you are trying to do. Periodic sine > >> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > >> wave lookup table for the slowest case. > > > > only if you want neat frequencies that add up to 100M > > > I don't understand what a neat frequency is, either. Any periodic > waveform at 1 MHz (the worst case) at 100 Msps update rate takes > a 100 entry table.But suppose you adjust to 0.99 MHz; do you now use a 101 entry table? And how about 0.995 MHz? The small-integer ratios for a given frequency don't support a fixed table size, and the 'update rate' might not be fine-adjustable enough. In contrast to a variable-LC tuning scheme, digital synthesis tables require... an exercise in ratios of integers to approximate a real number.
