On Sun, 14 Aug 2022 19:49:27 +0200, Gerhard Hoffmann <dk4xp@arcor.de> wrote:>Am 14.08.22 um 16:14 schrieb jlarkin@highlandsniptechnology.com: >> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >> <langwadt@fonz.dk> wrote: >> >>> s�ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >>>> It strikes me that John Larkin's original idea of synthesising trapezoids can be made to work. >>>> >>>> You would still use a fast 14- or 16 bit DAC, but the waveform you fed into your comparator would be made up of four sequential components - all coming out of the DAC - high segment of arbitrary length, a falling edge, a low segment, and a risng edge >>>> >>>> With a 14-bit DAC - the LTC2000 comes to mind >>>> >>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >>>> >>>> you'd synthisese the rising and falling edges of the trapezia as 16-successive steps of a staircase waveform. >>> >>> since it is for a trigger and the falling edge probably doesn't matter, why not a single variable voltage step into a filter, sorta like a time-to-amplitude in reverse >> >> My question is basically whether one can DDS a non-sinusoidal waveform >> to make a faster edge into a filter and comparator, to get better time >> resolution, less jitter, at low frequencies. >> >> Conventional thinking treats the DDS as the tail end of a Shannon >> sampling system. But that requires that the signal that we're trying >> to make is perfectly bandlimited, which a sine is but a trapezoid >> isn't. So wave goodby to Shannon. >> >> So we need to synthesize a fast edge, much faster than a sine, and >> poke that into an interpolation filter with a short attention span, >> one that sees the smooth part of the slope but forgets the sharp >> transition. Maybe synthesise an s-shaped rising edge to reduce the >> signal bandwidth some. >> >> And of course we need to reach farther right into the phase >> accumulator bits, in real life or maybe by interpolation. >> >> Hmmm, I could put a function, tanh or something, after the sine lookup >> in my DDS sim, to speed up the mid slope. That at least helps the >> comparator. Gotta think about that. > >You can take my VHDL design and have one of your FPGA guys >replace sin(x) by sin(x) * tanh(x) and simulate it in a few >seconds in Modelsim, Questasim or whatever you have. >You get a pseudo-analog output. > >The code that fills the ROM is a single process that feels >like Pascal, no concurrency. The intermediate results are even >files that could be used in Matlab. > >That all does not have much to do with VHDL; I just choose VHDL >because you need it anyway for compiling the chip. It could >just as good have been C or Pascal; that would require more >infrastructure such as gcc or turbo-pascal. It only generates >a text file that is put into the ROM when builing the chip. > > >Cheers, Gerhard > > > >My DDS sim is in Spice. I posted that a few threads above. I've parameterized it and added a sort of jitter computer; I'll post that soon. It's a platform for trying things out. A 5 us run takes about an hour at 1 ps time step.
Direct digital synthesis of square waves
Started by ●August 14, 2022
Reply by ●August 14, 20222022-08-14
Reply by ●August 14, 20222022-08-14
On 8/14/2022 17:14, jlarkin@highlandsniptechnology.com wrote:> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > >> søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >>> It strikes me that John Larkin's original idea of synthesising trapezoids can be made to work. >>> >>> You would still use a fast 14- or 16 bit DAC, but the waveform you fed into your comparator would be made up of four sequential components - all coming out of the DAC - high segment of arbitrary length, a falling edge, a low segment, and a risng edge >>> >>> With a 14-bit DAC - the LTC2000 comes to mind >>> >>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >>> >>> you'd synthisese the rising and falling edges of the trapezia as 16-successive steps of a staircase waveform. >> >> since it is for a trigger and the falling edge probably doesn't matter, why not a single variable voltage step into a filter, sorta like a time-to-amplitude in reverse > > My question is basically whether one can DDS a non-sinusoidal waveform > to make a faster edge into a filter and comparator, to get better time > resolution, less jitter, at low frequencies.I am only curious if I understand what you are after - is it some sort of "the larger the step the less low pass I want applied to it"?
Reply by ●August 14, 20222022-08-14
On 14/08/2022 11.22, Lasse Langwadt Christensen wrote:> søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >> It strikes me that John Larkin's original idea of synthesising trapezoids can be made to work. >> >> You would still use a fast 14- or 16 bit DAC, but the waveform you fed into your comparator would be made up of four sequential components - all coming out of the DAC - high segment of arbitrary length, a falling edge, a low segment, and a risng edge >> >> With a 14-bit DAC - the LTC2000 comes to mind >> >> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >> >> you'd synthisese the rising and falling edges of the trapezia as 16-successive steps of a staircase waveform. > > since it is for a trigger and the falling edge probably doesn't matter, why not a single variable voltage step into a filter, sorta like a time-to-amplitude in reverse > > Version 4 > SHEET 1 3724 680 > WIRE 480 48 432 48 > WIRE 160 64 48 64 > WIRE 272 64 240 64 > WIRE 368 64 272 64 > WIRE 272 80 272 64 > WIRE 48 96 48 64 > FLAG 272 144 0 > FLAG 48 176 0 > SYMBOL voltage 48 80 R0 > WINDOW 3 -363 55 Left 2 > WINDOW 123 0 0 Left 0 > WINDOW 39 0 0 Left 0 > SYMATTR InstName V1 > SYMATTR Value PULSE(0 {v} 10n 1p 1p .1u .2u) > SYMBOL res 256 48 R90 > WINDOW 0 0 56 VBottom 2 > WINDOW 3 32 56 VTop 2 > SYMATTR InstName R1 > SYMATTR Value 100 > SYMBOL cap 256 80 R0 > SYMATTR InstName C1 > SYMATTR Value 200p > SYMBOL Digital\\buf 368 0 R0 > SYMATTR InstName A1 > TEXT -394 -48 Left 2 !.tran 0 40n 0 .1n > TEXT -56 -96 Left 2 !.step param v list 0.79061 0.80014 0.81067 0.82231 0.83517 0.84939 0.86510 0.88246 0.90165 0.92286 0.94630 0.97221 1.00083 1.03247 1.06744 1.10608 1.14879 1.19599 1.24815 1.30580 1.36952 1.43993 1.51775 1.60375 1.69880 1.80385 1.91994 2.04824 2.19004 2.34675 2.51994 > >That's a really clever idea One could perhaps instead use a variable cap?
Reply by ●August 14, 20222022-08-14
On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <dp@tgi-sci.com> wrote:>On 8/14/2022 17:14, jlarkin@highlandsniptechnology.com wrote: >> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >> <langwadt@fonz.dk> wrote: >> >>> s�ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >>>> It strikes me that John Larkin's original idea of synthesising trapezoids can be made to work. >>>> >>>> You would still use a fast 14- or 16 bit DAC, but the waveform you fed into your comparator would be made up of four sequential components - all coming out of the DAC - high segment of arbitrary length, a falling edge, a low segment, and a risng edge >>>> >>>> With a 14-bit DAC - the LTC2000 comes to mind >>>> >>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >>>> >>>> you'd synthisese the rising and falling edges of the trapezia as 16-successive steps of a staircase waveform. >>> >>> since it is for a trigger and the falling edge probably doesn't matter, why not a single variable voltage step into a filter, sorta like a time-to-amplitude in reverse >> >> My question is basically whether one can DDS a non-sinusoidal waveform >> to make a faster edge into a filter and comparator, to get better time >> resolution, less jitter, at low frequencies. > >I am only curious if I understand what you are after - is it some sort >of "the larger the step the less low pass I want applied to it"?When synthesizing a low frequency DDS sine wave, we step slowly through the waveform lookup table and a fixed filter doesn't interpolate waveform steps any more; it settles every step. So, is there a better waveform to use at low frequencies?
Reply by ●August 14, 20222022-08-14
On 8/15/2022 1:08, jlarkin@highlandsniptechnology.com wrote:> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <dp@tgi-sci.com> > wrote: > >> On 8/14/2022 17:14, jlarkin@highlandsniptechnology.com wrote: >>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >>> <langwadt@fonz.dk> wrote: >>> >>>> søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >>>>> It strikes me that John Larkin's original idea of synthesising trapezoids can be made to work. >>>>> >>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you fed into your comparator would be made up of four sequential components - all coming out of the DAC - high segment of arbitrary length, a falling edge, a low segment, and a risng edge >>>>> >>>>> With a 14-bit DAC - the LTC2000 comes to mind >>>>> >>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >>>>> >>>>> you'd synthisese the rising and falling edges of the trapezia as 16-successive steps of a staircase waveform. >>>> >>>> since it is for a trigger and the falling edge probably doesn't matter, why not a single variable voltage step into a filter, sorta like a time-to-amplitude in reverse >>> >>> My question is basically whether one can DDS a non-sinusoidal waveform >>> to make a faster edge into a filter and comparator, to get better time >>> resolution, less jitter, at low frequencies. >> >> I am only curious if I understand what you are after - is it some sort >> of "the larger the step the less low pass I want applied to it"? > > When synthesizing a low frequency DDS sine wave, we step slowly > through the waveform lookup table and a fixed filter doesn't > interpolate waveform steps any more; it settles every step. > > So, is there a better waveform to use at low frequencies? >Hmmm. I get it now (though I don't get why this is a problem, likely specific to your application). I don't know how one waveform would be better for you that another, don't know what it is you are doing (perhaps you said and I missed it, I am not following closely). A pretty complex way of dealing with the steps at low frequencies is perhaps to have two DACs, one of them making the output filter programmable so you can dynamically change it, based on step, with some preemption etc., you get the idea - and I am not sure it is practical, not only because it is complex but also because I have never done this, I am just musing.
Reply by ●August 14, 20222022-08-14
Mike Monett VE3BTI <spamme@not.com> wrote:> I have zipped the original and uploaded it to Google Drive. Please > download it at https://tinyurl.com/3x256eej and see if it runs better.It also runs fine if you replace the three spaces between the parameters with a single space. Something is seriously wrong with sending LTspice files to the newsgroup. We also run into problems with line wrap and ASC files. From now on, I will zip the files and upload them to Google Drive. -- MRM
Reply by ●August 14, 20222022-08-14
On Monday, August 15, 2022 at 8:08:46 AM UTC+10, jla...@highlandsniptechnology.com wrote:> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> > wrote: > >On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen > >> <lang...@fonz.dk> wrote: > >> > >>> sųndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > >>>> It strikes me that John Larkin's original idea of synthesising trapezoids can be made to work. > >>>> > >>>> You would still use a fast 14- or 16 bit DAC, but the waveform you fed into your comparator would be made up of four sequential components - all coming out of the DAC - high segment of arbitrary length, a falling edge, a low segment, and a risng edge > >>>> > >>>> With a 14-bit DAC - the LTC2000 comes to mind > >>>> > >>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf > >>>> > >>>> you'd synthisese the rising and falling edges of the trapezia as 16-successive steps of a staircase waveform. > >>> > >>> since it is for a trigger and the falling edge probably doesn't matter, why not a single variable voltage step into a filter, sorta like a time-to-amplitude in reverse > >> > >> My question is basically whether one can DDS a non-sinusoidal waveform > >> to make a faster edge into a filter and comparator, to get better time > >> resolution, less jitter, at low frequencies. > > > >I am only curious if I understand what you are after - is it some sort > >of "the larger the step the less low pass I want applied to it"? > When synthesizing a low frequency DDS sine wave, we step slowly > through the waveform lookup table and a fixed filter doesn't > interpolate waveform steps any more; it settles every step. > > So, is there a better waveform to use at low frequencies?Your original idea was that a trapezium would would be better than a sine wave. If you keep the slope of the sloped bits constant, you can stick to the same the low pass filter time constant to smooth out the steps in the stair-case approximation to the sloped segments. I just proposed a DAC based scheme for doing that. -- Bill Sloman, Sydney
Reply by ●August 15, 20222022-08-15
On 8/15/2022 1:41, Dimiter_Popoff wrote:> On 8/15/2022 1:08, jlarkin@highlandsniptechnology.com wrote: >> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <dp@tgi-sci.com> >> wrote: >> >>> On 8/14/2022 17:14, jlarkin@highlandsniptechnology.com wrote: >>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >>>> <langwadt@fonz.dk> wrote: >>>> >>>>> søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >>>>>> It strikes me that John Larkin's original idea of synthesising >>>>>> trapezoids can be made to work. >>>>>> >>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you >>>>>> fed into your comparator would be made up of four sequential >>>>>> components - all coming out of the DAC - high segment of arbitrary >>>>>> length, a falling edge, a low segment, and a risng edge >>>>>> >>>>>> With a 14-bit DAC - the LTC2000 comes to mind >>>>>> >>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >>>>>> >>>>>> >>>>>> you'd synthisese the rising and falling edges of the trapezia as >>>>>> 16-successive steps of a staircase waveform. >>>>> >>>>> since it is for a trigger and the falling edge probably doesn't >>>>> matter, why not a single variable voltage step into a filter, sorta >>>>> like a time-to-amplitude in reverse >>>> >>>> My question is basically whether one can DDS a non-sinusoidal waveform >>>> to make a faster edge into a filter and comparator, to get better time >>>> resolution, less jitter, at low frequencies. >>> >>> I am only curious if I understand what you are after - is it some sort >>> of "the larger the step the less low pass I want applied to it"? >> >> When synthesizing a low frequency DDS sine wave, we step slowly >> through the waveform lookup table and a fixed filter doesn't >> interpolate waveform steps any more; it settles every step. >> >> So, is there a better waveform to use at low frequencies? >> > > Hmmm. I get it now (though I don't get why this is a problem, > likely specific to your application). I don't know how one > waveform would be better for you that another, don't know > what it is you are doing (perhaps you said and I missed it, > I am not following closely). > A pretty complex way of dealing with the steps at low frequencies > is perhaps to have two DACs, one of them making the output filter > programmable so you can dynamically change it, based on step, > with some preemption etc., you get the idea - and I am not sure > it is practical, not only because it is complex but also because > I have never done this, I am just musing.I missed the "we step slowly" in your post, now I get it. Well, the simplest way out is to step at a constant rate all the time. It will probably mean adding memory of course. Obviously you know all that and this is what you a re trying to wrestle, I don't think there is a better way to do it though (better than adding memory so your update rate remains constant).
Reply by ●August 15, 20222022-08-15
On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <dp@tgi-sci.com> wrote:>On 8/15/2022 1:41, Dimiter_Popoff wrote: >> On 8/15/2022 1:08, jlarkin@highlandsniptechnology.com wrote: >>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>> wrote: >>> >>>> On 8/14/2022 17:14, jlarkin@highlandsniptechnology.com wrote: >>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >>>>> <langwadt@fonz.dk> wrote: >>>>> >>>>>> s�ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >>>>>>> It strikes me that John Larkin's original idea of synthesising >>>>>>> trapezoids can be made to work. >>>>>>> >>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you >>>>>>> fed into your comparator would be made up of four sequential >>>>>>> components - all coming out of the DAC - high segment of arbitrary >>>>>>> length, a falling edge, a low segment, and a risng edge >>>>>>> >>>>>>> With a 14-bit DAC - the LTC2000 comes to mind >>>>>>> >>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >>>>>>> >>>>>>> >>>>>>> you'd synthisese the rising and falling edges of the trapezia as >>>>>>> 16-successive steps of a staircase waveform. >>>>>> >>>>>> since it is for a trigger and the falling edge probably doesn't >>>>>> matter, why not a single variable voltage step into a filter, sorta >>>>>> like a time-to-amplitude in reverse >>>>> >>>>> My question is basically whether one can DDS a non-sinusoidal waveform >>>>> to make a faster edge into a filter and comparator, to get better time >>>>> resolution, less jitter, at low frequencies. >>>> >>>> I am only curious if I understand what you are after - is it some sort >>>> of "the larger the step the less low pass I want applied to it"? >>> >>> When synthesizing a low frequency DDS sine wave, we step slowly >>> through the waveform lookup table and a fixed filter doesn't >>> interpolate waveform steps any more; it settles every step. >>> >>> So, is there a better waveform to use at low frequencies? >>> >> >> Hmmm. I get it now (though I don't get why this is a problem, >> likely specific to your application). I don't know how one >> waveform would be better for you that another, don't know >> what it is you are doing (perhaps you said and I missed it, >> I am not following closely). >> A pretty complex way of dealing with the steps at low frequencies >> is perhaps to have two DACs, one of them making the output filter >> programmable so you can dynamically change it, based on step, >> with some preemption etc., you get the idea - and I am not sure >> it is practical, not only because it is complex but also because >> I have never done this, I am just musing. > >I missed the "we step slowly" in your post, now I get it. >Well, the simplest way out is to step at a constant rate all the >time.I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That needs a sine lookup table with about 50 billion entries. And an equally impossible DAC and comparator. We'll probably wind up synthesizing the high range, an octave or so, and divide down as needed. The trick will be to make the gear shifts appear to be seamless. That could get interesting.
Reply by ●August 15, 20222022-08-15
On Tuesday, August 16, 2022 at 12:17:56 AM UTC+10, jla...@highlandsniptechnology.com wrote:> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com wrote: > >On 8/15/2022 1:41, Dimiter_Popoff wrote: > >> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > >>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> wrote: > >>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote: > >>>>>> søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org:<snip>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > needs a sine lookup table with about 50 billion entries.Only if you chose to do that way. You could rewrite the look-up table every time you changed the frequency.> And an equally impossible DAC and comparator.So think it out again.> We'll probably wind up synthesizing the high range, an octave or so, > and divide down as needed. The trick will be to make the gear shifts > appear to be seamless.What's difficult about that? It isn't as if there are any moving parts involved. The customer needs to tell you the frequency they want the machine to push out, and you need to be able to reconfigure it so that is the frequency which comes out.> That could get interesting.Only if if you make life difficult for yourself by failing to tear up your original idea when it started looking half-baked. -- Bill Sloman, Sydney
