On 8/16/2022 2:45, whit3rd wrote:> On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote: >> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: >>> mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff: > >>>> I still don't understand what you are trying to do. Periodic sine >>>> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >>>> wave lookup table for the slowest case. >>> >>> only if you want neat frequencies that add up to 100M >>> >> I don't understand what a neat frequency is, either. Any periodic >> waveform at 1 MHz (the worst case) at 100 Msps update rate takes >> a 100 entry table. > > But suppose you adjust to 0.99 MHz; do you now use a 101 entry table? > And how about 0.995 MHz? > The small-integer ratios for a given frequency don't support a fixed table > size, and the 'update rate' might not be fine-adjustable enough. In contrast > to a variable-LC tuning scheme, digital synthesis tables require... an exercise > in ratios of integers to approximate a real number.No, of course not :-). Of course it will take some "oversampling" etc., but it is still trivial. All it takes is say (for simplicity) a 2^16 long waveform lookup table, a factor being the quotient period/max. period normalized such that adding it to a sum each sample the sum it will be the offset to the next table entry to take. Obviously the sum is kept anded to $ffff and is never altered by other means; if we want to change the output frequency we only recalculate the quotient and keep adding.
Direct digital synthesis of square waves
Started by ●August 14, 2022
Reply by ●August 15, 20222022-08-15
Reply by ●August 15, 20222022-08-15
On Mon, 15 Aug 2022 16:45:18 -0700 (PDT), whit3rd <whit3rd@gmail.com> wrote:>On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote: >> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: >> > mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff: > >> >> I still don't understand what you are trying to do. Periodic sine >> >> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >> >> wave lookup table for the slowest case. >> > >> > only if you want neat frequencies that add up to 100M >> > >> I don't understand what a neat frequency is, either. Any periodic >> waveform at 1 MHz (the worst case) at 100 Msps update rate takes >> a 100 entry table. > >But suppose you adjust to 0.99 MHz; do you now use a 101 entry table? >And how about 0.995 MHz? >The small-integer ratios for a given frequency don't support a fixed table >size, and the 'update rate' might not be fine-adjustable enough. In contrast >to a variable-LC tuning scheme, digital synthesis tables require... an exercise >in ratios of integers to approximate a real number.With a DDS phase accumulator, the output frequency is Fxo * N / M where Fxo is the 100 MHz xtal oscillator N is the frequency set word M is the accumulator max count, say 2^48. Frequency set resolution would be below 1 uHz in this case. Just load N. The sine lookup table is addressed by some number of MSBs of the phase accumulator, 10 to 16 typically. It doesn't change in a given system.
Reply by ●August 15, 20222022-08-15
On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <dp@tgi-sci.com> wrote:>On 8/15/2022 17:17, jlarkin@highlandsniptechnology.com wrote: >> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <dp@tgi-sci.com> >> wrote: >> >>> On 8/15/2022 1:41, Dimiter_Popoff wrote: >>>> On 8/15/2022 1:08, jlarkin@highlandsniptechnology.com wrote: >>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>>>> wrote: >>>>> >>>>>> On 8/14/2022 17:14, jlarkin@highlandsniptechnology.com wrote: >>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >>>>>>> <langwadt@fonz.dk> wrote: >>>>>>> >>>>>>>> s�ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >>>>>>>>> It strikes me that John Larkin's original idea of synthesising >>>>>>>>> trapezoids can be made to work. >>>>>>>>> >>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you >>>>>>>>> fed into your comparator would be made up of four sequential >>>>>>>>> components - all coming out of the DAC - high segment of arbitrary >>>>>>>>> length, a falling edge, a low segment, and a risng edge >>>>>>>>> >>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind >>>>>>>>> >>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >>>>>>>>> >>>>>>>>> >>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as >>>>>>>>> 16-successive steps of a staircase waveform. >>>>>>>> >>>>>>>> since it is for a trigger and the falling edge probably doesn't >>>>>>>> matter, why not a single variable voltage step into a filter, sorta >>>>>>>> like a time-to-amplitude in reverse >>>>>>> >>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform >>>>>>> to make a faster edge into a filter and comparator, to get better time >>>>>>> resolution, less jitter, at low frequencies. >>>>>> >>>>>> I am only curious if I understand what you are after - is it some sort >>>>>> of "the larger the step the less low pass I want applied to it"? >>>>> >>>>> When synthesizing a low frequency DDS sine wave, we step slowly >>>>> through the waveform lookup table and a fixed filter doesn't >>>>> interpolate waveform steps any more; it settles every step. >>>>> >>>>> So, is there a better waveform to use at low frequencies? >>>>> >>>> >>>> Hmmm. I get it now (though I don't get why this is a problem, >>>> likely specific to your application). I don't know how one >>>> waveform would be better for you that another, don't know >>>> what it is you are doing (perhaps you said and I missed it, >>>> I am not following closely). >>>> A pretty complex way of dealing with the steps at low frequencies >>>> is perhaps to have two DACs, one of them making the output filter >>>> programmable so you can dynamically change it, based on step, >>>> with some preemption etc., you get the idea - and I am not sure >>>> it is practical, not only because it is complex but also because >>>> I have never done this, I am just musing. >>> >>> I missed the "we step slowly" in your post, now I get it. >>> Well, the simplest way out is to step at a constant rate all the >>> time. >> >> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That >> needs a sine lookup table with about 50 billion entries. And an >> equally impossible DAC and comparator. >> >> We'll probably wind up synthesizing the high range, an octave or so, >> and divide down as needed. The trick will be to make the gear shifts >> appear to be seamless. >> >> That could get interesting. >> > >I still don't understand what you are trying to do. Periodic sine >wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >wave lookup table for the slowest case. If you want to switch by >operator action you have milliseconds of time to recalculate the table. >If you want to switch by some external gating you only need two >tables to switch between, this makes up to 200 entries. >This is all way too simple and obvious so you must be after something >more than that - which I haven't got yet.I just want a programmable-frequency trigger generator that changes frequency on demand and doesn't stop for reprogramming and doesn't blow up someone's laser by generating any goofy triggers. In other words, goes smoothly from F1 to F2. With low period jitter from, say, 1 mHz to 15 Mhz. mHz resolution is good too.
Reply by ●August 16, 20222022-08-16
On Tuesday, August 16, 2022 at 12:26:40 PM UTC+10, jla...@highlandsniptechnology.com wrote:> On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <d...@tgi-sci.com>> wrote: > >On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: > >> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> wrote: > >>> On 8/15/2022 1:41, Dimiter_Popoff wrote: > >>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > >>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> wrote: > >>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen > >>>>>>> <lang...@fonz.dk> wrote: > >>>>>>>> sųndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org:<snip>> I just want a programmable-frequency trigger generator that changes > frequency on demand and doesn't stop for reprogramming and doesn't > blow up someone's laser by generating any goofy triggers. In other > words, goes smoothly from F1 to F2. > > With low period jitter from, say, 1 mHz to 15 Mhz. > > mHz resolution is good too.The period difference between 15 MHz and 14,999,999.999 Hz is 4.44E-15 seconds. That would be demanding. 0.1% frequency setability should be impressive enough, and that would only demand a 70 psec increment in period at 15MHz. You could get that out of an MC 100EP195 https://www.onsemi.com/pdf/datasheet/mc100ep195-d.pdf John Larkin needs to start thinking about what his specifications mean. -- Bill Sloman, Sydney
Reply by ●August 16, 20222022-08-16
On a sunny day (Mon, 15 Aug 2022 19:26:28 -0700) it happened jlarkin@highlandsniptechnology.com wrote in <npvlfhtkcnupjs4ndt8petfffkqkjghi7b@4ax.com>:>I just want a programmable-frequency trigger generator that changes >frequency on demand and doesn't stop for reprogramming and doesn't >blow up someone's laser by generating any goofy triggers. In other >words, goes smoothly from F1 to F2. > >With low period jitter from, say, 1 mHz to 15 Mhz. > >mHz resolution is good too.Well the antique way would be to mix 2 carriers. Say 100 MHz and 100 MHz mix and low pass the differnce. Now FM modulate one, from 100 MHz down to 90 MHz. (100 MHz just for example) Kids stuff.
Reply by ●August 16, 20222022-08-16
On 8/16/2022 5:26, jlarkin@highlandsniptechnology.com wrote:> On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <dp@tgi-sci.com> > wrote: > >> On 8/15/2022 17:17, jlarkin@highlandsniptechnology.com wrote: >>> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>> wrote: >>> >>>> On 8/15/2022 1:41, Dimiter_Popoff wrote: >>>>> On 8/15/2022 1:08, jlarkin@highlandsniptechnology.com wrote: >>>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>>>>> wrote: >>>>>> >>>>>>> On 8/14/2022 17:14, jlarkin@highlandsniptechnology.com wrote: >>>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>> <langwadt@fonz.dk> wrote: >>>>>>>> >>>>>>>>> søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >>>>>>>>>> It strikes me that John Larkin's original idea of synthesising >>>>>>>>>> trapezoids can be made to work. >>>>>>>>>> >>>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you >>>>>>>>>> fed into your comparator would be made up of four sequential >>>>>>>>>> components - all coming out of the DAC - high segment of arbitrary >>>>>>>>>> length, a falling edge, a low segment, and a risng edge >>>>>>>>>> >>>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind >>>>>>>>>> >>>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as >>>>>>>>>> 16-successive steps of a staircase waveform. >>>>>>>>> >>>>>>>>> since it is for a trigger and the falling edge probably doesn't >>>>>>>>> matter, why not a single variable voltage step into a filter, sorta >>>>>>>>> like a time-to-amplitude in reverse >>>>>>>> >>>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform >>>>>>>> to make a faster edge into a filter and comparator, to get better time >>>>>>>> resolution, less jitter, at low frequencies. >>>>>>> >>>>>>> I am only curious if I understand what you are after - is it some sort >>>>>>> of "the larger the step the less low pass I want applied to it"? >>>>>> >>>>>> When synthesizing a low frequency DDS sine wave, we step slowly >>>>>> through the waveform lookup table and a fixed filter doesn't >>>>>> interpolate waveform steps any more; it settles every step. >>>>>> >>>>>> So, is there a better waveform to use at low frequencies? >>>>>> >>>>> >>>>> Hmmm. I get it now (though I don't get why this is a problem, >>>>> likely specific to your application). I don't know how one >>>>> waveform would be better for you that another, don't know >>>>> what it is you are doing (perhaps you said and I missed it, >>>>> I am not following closely). >>>>> A pretty complex way of dealing with the steps at low frequencies >>>>> is perhaps to have two DACs, one of them making the output filter >>>>> programmable so you can dynamically change it, based on step, >>>>> with some preemption etc., you get the idea - and I am not sure >>>>> it is practical, not only because it is complex but also because >>>>> I have never done this, I am just musing. >>>> >>>> I missed the "we step slowly" in your post, now I get it. >>>> Well, the simplest way out is to step at a constant rate all the >>>> time. >>> >>> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That >>> needs a sine lookup table with about 50 billion entries. And an >>> equally impossible DAC and comparator. >>> >>> We'll probably wind up synthesizing the high range, an octave or so, >>> and divide down as needed. The trick will be to make the gear shifts >>> appear to be seamless. >>> >>> That could get interesting. >>> >> >> I still don't understand what you are trying to do. Periodic sine >> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >> wave lookup table for the slowest case. If you want to switch by >> operator action you have milliseconds of time to recalculate the table. >> If you want to switch by some external gating you only need two >> tables to switch between, this makes up to 200 entries. >> This is all way too simple and obvious so you must be after something >> more than that - which I haven't got yet. > > I just want a programmable-frequency trigger generator that changes > frequency on demand and doesn't stop for reprogramming and doesn't > blow up someone's laser by generating any goofy triggers. In other > words, goes smoothly from F1 to F2. > > With low period jitter from, say, 1 mHz to 15 Mhz. > > mHz resolution is good too. >Now I get it. I had misread mHz as MHz.... :D.
Reply by ●August 16, 20222022-08-16
On 8/16/2022 3:23, John Larkin wrote:> On Mon, 15 Aug 2022 16:45:18 -0700 (PDT), whit3rd <whit3rd@gmail.com> > wrote: > >> On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote: >>> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: >>>> mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff: >> >>>>> I still don't understand what you are trying to do. Periodic sine >>>>> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >>>>> wave lookup table for the slowest case. >>>> >>>> only if you want neat frequencies that add up to 100M >>>> >>> I don't understand what a neat frequency is, either. Any periodic >>> waveform at 1 MHz (the worst case) at 100 Msps update rate takes >>> a 100 entry table. >> >> But suppose you adjust to 0.99 MHz; do you now use a 101 entry table? >> And how about 0.995 MHz? >> The small-integer ratios for a given frequency don't support a fixed table >> size, and the 'update rate' might not be fine-adjustable enough. In contrast >> to a variable-LC tuning scheme, digital synthesis tables require... an exercise >> in ratios of integers to approximate a real number. > > With a DDS phase accumulator, the output frequency is > > Fxo * N / M > > where Fxo is the 100 MHz xtal oscillator > > N is the frequency set word > > M is the accumulator max count, say 2^48. > > Frequency set resolution would be below 1 uHz in this case. Just load > N. > > The sine lookup table is addressed by some number of MSBs of the phase > accumulator, 10 to 16 typically. It doesn't change in a given system. > > >Perhaps you could shorten the lookup table to some manageable size if you do lookup-and-interpolate. Will still be huge... And division at 100 Msps may well be prohibitive.
Reply by ●August 16, 20222022-08-16
tirsdag den 16. august 2022 kl. 04.26.40 UTC+2 skrev jla...@highlandsniptechnology.com:> On Mon, 15 Aug 2022 22:42:11 +0300, Dimiter_Popoff <d...@tgi-sci.com> > wrote: > > >On 8/15/2022 17:17, jla...@highlandsniptechnology.com wrote: > >> On Mon, 15 Aug 2022 12:54:56 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >> wrote: > >> > >>> On 8/15/2022 1:41, Dimiter_Popoff wrote: > >>>> On 8/15/2022 1:08, jla...@highlandsniptechnology.com wrote: > >>>>> On Mon, 15 Aug 2022 00:46:15 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>>>> wrote: > >>>>> > >>>>>> On 8/14/2022 17:14, jla...@highlandsniptechnology.com wrote: > >>>>>>> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen > >>>>>>> <lang...@fonz.dk> wrote: > >>>>>>> > >>>>>>>> sųndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: > >>>>>>>>> It strikes me that John Larkin's original idea of synthesising > >>>>>>>>> trapezoids can be made to work. > >>>>>>>>> > >>>>>>>>> You would still use a fast 14- or 16 bit DAC, but the waveform you > >>>>>>>>> fed into your comparator would be made up of four sequential > >>>>>>>>> components - all coming out of the DAC - high segment of arbitrary > >>>>>>>>> length, a falling edge, a low segment, and a risng edge > >>>>>>>>> > >>>>>>>>> With a 14-bit DAC - the LTC2000 comes to mind > >>>>>>>>> > >>>>>>>>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf > >>>>>>>>> > >>>>>>>>> > >>>>>>>>> you'd synthisese the rising and falling edges of the trapezia as > >>>>>>>>> 16-successive steps of a staircase waveform. > >>>>>>>> > >>>>>>>> since it is for a trigger and the falling edge probably doesn't > >>>>>>>> matter, why not a single variable voltage step into a filter, sorta > >>>>>>>> like a time-to-amplitude in reverse > >>>>>>> > >>>>>>> My question is basically whether one can DDS a non-sinusoidal waveform > >>>>>>> to make a faster edge into a filter and comparator, to get better time > >>>>>>> resolution, less jitter, at low frequencies. > >>>>>> > >>>>>> I am only curious if I understand what you are after - is it some sort > >>>>>> of "the larger the step the less low pass I want applied to it"? > >>>>> > >>>>> When synthesizing a low frequency DDS sine wave, we step slowly > >>>>> through the waveform lookup table and a fixed filter doesn't > >>>>> interpolate waveform steps any more; it settles every step. > >>>>> > >>>>> So, is there a better waveform to use at low frequencies? > >>>>> > >>>> > >>>> Hmmm. I get it now (though I don't get why this is a problem, > >>>> likely specific to your application). I don't know how one > >>>> waveform would be better for you that another, don't know > >>>> what it is you are doing (perhaps you said and I missed it, > >>>> I am not following closely). > >>>> A pretty complex way of dealing with the steps at low frequencies > >>>> is perhaps to have two DACs, one of them making the output filter > >>>> programmable so you can dynamically change it, based on step, > >>>> with some preemption etc., you get the idea - and I am not sure > >>>> it is practical, not only because it is complex but also because > >>>> I have never done this, I am just musing. > >>> > >>> I missed the "we step slowly" in your post, now I get it. > >>> Well, the simplest way out is to step at a constant rate all the > >>> time. > >> > >> I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That > >> needs a sine lookup table with about 50 billion entries. And an > >> equally impossible DAC and comparator. > >> > >> We'll probably wind up synthesizing the high range, an octave or so, > >> and divide down as needed. The trick will be to make the gear shifts > >> appear to be seamless. > >> > >> That could get interesting. > >> > > > >I still don't understand what you are trying to do. Periodic sine > >wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > >wave lookup table for the slowest case. If you want to switch by > >operator action you have milliseconds of time to recalculate the table. > >If you want to switch by some external gating you only need two > >tables to switch between, this makes up to 200 entries. > >This is all way too simple and obvious so you must be after something > >more than that - which I haven't got yet. > I just want a programmable-frequency trigger generator that changes > frequency on demand and doesn't stop for reprogramming and doesn't > blow up someone's laser by generating any goofy triggers. In other > words, goes smoothly from F1 to F2. > > With low period jitter from, say, 1 mHz to 15 Mhz. > > mHz resolution is good too.add a frequency dependent gain and clamp to the sine to keep a reasonable slew rate? possibly to the triangular wave input to the lookup table so you get sine edges with flat tops
Reply by ●August 16, 20222022-08-16
On Tue, 16 Aug 2022 15:44:27 +0300, Dimiter_Popoff <dp@tgi-sci.com> wrote:>On 8/16/2022 3:23, John Larkin wrote: >> On Mon, 15 Aug 2022 16:45:18 -0700 (PDT), whit3rd <whit3rd@gmail.com> >> wrote: >> >>> On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote: >>>> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: >>>>> mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff: >>> >>>>>> I still don't understand what you are trying to do. Periodic sine >>>>>> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine >>>>>> wave lookup table for the slowest case. >>>>> >>>>> only if you want neat frequencies that add up to 100M >>>>> >>>> I don't understand what a neat frequency is, either. Any periodic >>>> waveform at 1 MHz (the worst case) at 100 Msps update rate takes >>>> a 100 entry table. >>> >>> But suppose you adjust to 0.99 MHz; do you now use a 101 entry table? >>> And how about 0.995 MHz? >>> The small-integer ratios for a given frequency don't support a fixed table >>> size, and the 'update rate' might not be fine-adjustable enough. In contrast >>> to a variable-LC tuning scheme, digital synthesis tables require... an exercise >>> in ratios of integers to approximate a real number. >> >> With a DDS phase accumulator, the output frequency is >> >> Fxo * N / M >> >> where Fxo is the 100 MHz xtal oscillator >> >> N is the frequency set word >> >> M is the accumulator max count, say 2^48. >> >> Frequency set resolution would be below 1 uHz in this case. Just load >> N. >> >> The sine lookup table is addressed by some number of MSBs of the phase >> accumulator, 10 to 16 typically. It doesn't change in a given system. >> >> >> > >Perhaps you could shorten the lookup table to some manageable size if >you do lookup-and-interpolate. Will still be huge... And division >at 100 Msps may well be prohibitive.Our FPGA will have at least a megabit of ram if we use the efinix, lots more if we use the Zynq. A sine table can be folded 2:1 or 4:1, so we can easily do 64K points of 16 bit data. One of my guys proposed an architecture that uses more bits of the phase accumulator. A group of MS bits becomes the gate for a cluster of LS bits. Envision a spinner dial that mostly parks at 0 degrees and once in a while makes a single fast rotation. That essentially puts a divisor *before* a cosine lookup table and DAC. Gotta simulate that somehow.
Reply by ●August 16, 20222022-08-16
tirsdag den 16. august 2022 kl. 16.03.01 UTC+2 skrev jla...@highlandsniptechnology.com:> On Tue, 16 Aug 2022 15:44:27 +0300, Dimiter_Popoff <d...@tgi-sci.com> > wrote: > >On 8/16/2022 3:23, John Larkin wrote: > >> On Mon, 15 Aug 2022 16:45:18 -0700 (PDT), whit3rd <whi...@gmail.com> > >> wrote: > >> > >>> On Monday, August 15, 2022 at 2:03:21 PM UTC-7, Dimiter Popoff wrote: > >>>> On 8/15/2022 22:56, Lasse Langwadt Christensen wrote: > >>>>> mandag den 15. august 2022 kl. 21.42.18 UTC+2 skrev Dimiter Popoff: > >>> > >>>>>> I still don't understand what you are trying to do. Periodic sine > >>>>>> wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine > >>>>>> wave lookup table for the slowest case. > >>>>> > >>>>> only if you want neat frequencies that add up to 100M > >>>>> > >>>> I don't understand what a neat frequency is, either. Any periodic > >>>> waveform at 1 MHz (the worst case) at 100 Msps update rate takes > >>>> a 100 entry table. > >>> > >>> But suppose you adjust to 0.99 MHz; do you now use a 101 entry table? > >>> And how about 0.995 MHz? > >>> The small-integer ratios for a given frequency don't support a fixed table > >>> size, and the 'update rate' might not be fine-adjustable enough. In contrast > >>> to a variable-LC tuning scheme, digital synthesis tables require... an exercise > >>> in ratios of integers to approximate a real number. > >> > >> With a DDS phase accumulator, the output frequency is > >> > >> Fxo * N / M > >> > >> where Fxo is the 100 MHz xtal oscillator > >> > >> N is the frequency set word > >> > >> M is the accumulator max count, say 2^48. > >> > >> Frequency set resolution would be below 1 uHz in this case. Just load > >> N. > >> > >> The sine lookup table is addressed by some number of MSBs of the phase > >> accumulator, 10 to 16 typically. It doesn't change in a given system. > >> > >> > >> > > > >Perhaps you could shorten the lookup table to some manageable size if > >you do lookup-and-interpolate. Will still be huge... And division > >at 100 Msps may well be prohibitive. > Our FPGA will have at least a megabit of ram if we use the efinix, > lots more if we use the Zynq. A sine table can be folded 2:1 or 4:1, > so we can easily do 64K points of 16 bit data. > > One of my guys proposed an architecture that uses more bits of the > phase accumulator. A group of MS bits becomes the gate for a cluster > of LS bits. Envision a spinner dial that mostly parks at 0 degrees and > once in a while makes a single fast rotation. That essentially puts a > divisor *before* a cosine lookup table and DAC. > > Gotta simulate that somehow.take you favorite programming language (or a spreadsheet) make a textfile with two columns time and value, a voltage source can load that as a pwl file
