It strikes me that John Larkin's original idea of synthesising trapezoids can be made to work. You would still use a fast 14- or 16 bit DAC, but the waveform you fed into your comparator would be made up of four sequential components - all coming out of the DAC - high segment of arbitrary length, a falling edge, a low segment, and a risng edge With a 14-bit DAC - the LTC2000 comes to mind https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf you'd synthisese the rising and falling edges of the trapezia as 16-successive steps of a staircase waveform. The LTC2000 can be clocked at 2.5GHz, so the rising and falling edges could be just 6.4nsec wide, and your maximum full amplitude output frequency would be a 78MHz triangular wave. The trick is that you could have 1024 different rising or falling edges, with all the steps moved up or down in in steps of 0.1% of the full scale swing. Only the first and last steps of the staircase would look different. If you low pass filtered the waveform the zero crossing point would move across the 0.4nsec clock period in steps of 0.4psec. The trick would be to use a Bessel - linear phase - filter which has a little bit of output ripple (figure 2.58 in Williams and Taylor) where the impulse response crosses the zero line, and put that point at the 3.2 nsec zero-crossing point ( picking the filter time constant to be about 0.64nsec, depending on the filter order) which would stop the odd first step from having much effect on the zero crossing point. You could get any frequency less than 78.125 MHz, and you could step the period up in increments of 0.4.psec. 78.123 MHz would be the next one down Because your filter only deals with rising an falling edges, you don't need to change it when you are synthesising much slower square waves. It should work. I'd hate to build it - the LTC2000 comes in a ball grid array package. -- Bill Sloman, Sydney
Direct digital synthesis of square waves
Started by ●August 14, 2022
Reply by ●August 14, 20222022-08-14
søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org:> It strikes me that John Larkin's original idea of synthesising trapezoids can be made to work. > > You would still use a fast 14- or 16 bit DAC, but the waveform you fed into your comparator would be made up of four sequential components - all coming out of the DAC - high segment of arbitrary length, a falling edge, a low segment, and a risng edge > > With a 14-bit DAC - the LTC2000 comes to mind > > https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf > > you'd synthisese the rising and falling edges of the trapezia as 16-successive steps of a staircase waveform.since it is for a trigger and the falling edge probably doesn't matter, why not a single variable voltage step into a filter, sorta like a time-to-amplitude in reverse Version 4 SHEET 1 3724 680 WIRE 480 48 432 48 WIRE 160 64 48 64 WIRE 272 64 240 64 WIRE 368 64 272 64 WIRE 272 80 272 64 WIRE 48 96 48 64 FLAG 272 144 0 FLAG 48 176 0 SYMBOL voltage 48 80 R0 WINDOW 3 -363 55 Left 2 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 {v} 10n 1p 1p .1u .2u) SYMBOL res 256 48 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 100 SYMBOL cap 256 80 R0 SYMATTR InstName C1 SYMATTR Value 200p SYMBOL Digital\\buf 368 0 R0 SYMATTR InstName A1 TEXT -394 -48 Left 2 !.tran 0 40n 0 .1n TEXT -56 -96 Left 2 !.step param v list 0.79061 0.80014 0.81067 0.82231 0.83517 0.84939 0.86510 0.88246 0.90165 0.92286 0.94630 0.97221 1.00083 1.03247 1.06744 1.10608 1.14879 1.19599 1.24815 1.30580 1.36952 1.43993 1.51775 1.60375 1.69880 1.80385 1.91994 2.04824 2.19004 2.34675 2.51994
Reply by ●August 14, 20222022-08-14
On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>s�ndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >> It strikes me that John Larkin's original idea of synthesising trapezoids can be made to work. >> >> You would still use a fast 14- or 16 bit DAC, but the waveform you fed into your comparator would be made up of four sequential components - all coming out of the DAC - high segment of arbitrary length, a falling edge, a low segment, and a risng edge >> >> With a 14-bit DAC - the LTC2000 comes to mind >> >> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >> >> you'd synthisese the rising and falling edges of the trapezia as 16-successive steps of a staircase waveform. > >since it is for a trigger and the falling edge probably doesn't matter, why not a single variable voltage step into a filter, sorta like a time-to-amplitude in reverseMy question is basically whether one can DDS a non-sinusoidal waveform to make a faster edge into a filter and comparator, to get better time resolution, less jitter, at low frequencies. Conventional thinking treats the DDS as the tail end of a Shannon sampling system. But that requires that the signal that we're trying to make is perfectly bandlimited, which a sine is but a trapezoid isn't. So wave goodby to Shannon. So we need to synthesize a fast edge, much faster than a sine, and poke that into an interpolation filter with a short attention span, one that sees the smooth part of the slope but forgets the sharp transition. Maybe synthesise an s-shaped rising edge to reduce the signal bandwidth some. And of course we need to reach farther right into the phase accumulator bits, in real life or maybe by interpolation. Hmmm, I could put a function, tanh or something, after the sine lookup in my DDS sim, to speed up the mid slope. That at least helps the comparator. Gotta think about that.
Reply by ●August 14, 20222022-08-14
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote: [...]> since it is for a trigger and the falling edge probably doesn't matter, > why not a single variable voltage step into a filter, sorta like a > time-to-amplitude in reverseSee if this works to get it on screen: Version 4 SHEET 1 3724 680 WIRE 464 48 432 48 WIRE 480 48 464 48 WIRE 64 64 48 64 WIRE 160 64 64 64 WIRE 272 64 240 64 WIRE 304 64 272 64 WIRE 368 64 304 64 WIRE 272 80 272 64 WIRE 48 96 48 64 WIRE 48 192 48 176 FLAG 272 144 0 FLAG 48 192 0 FLAG 64 64 Pin FLAG 304 64 R1C1 FLAG 464 48 A1O SYMBOL voltage 48 80 R0 WINDOW 3 -30 151 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value PULSE(0 {v} 10n 1p 1p .1u .2u) SYMATTR InstName V1 SYMBOL res 256 48 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 100 SYMBOL cap 256 80 R0 SYMATTR InstName C1 SYMATTR Value 200p SYMBOL Digital\\buf 368 0 R0 SYMATTR InstName A1 TEXT 192 -160 Left 2 !.tran 0 40n 0 0.01n TEXT -56 -96 Left 2 !.step param v list 0.79061 0.80014 0.81067 0.82231 0.83517 0.84939 0.86510\n+0.88246 0.90165 0.92286 0.94630 0.97221 1.00083 1.03247 1.06744\n+1.10608 1.14879 1.19599 1.24815 1.30580 1.36952 1.43993 1.51775\n+1.60375 1.69880 1.80385 1.91994 2.04824 2.19004 2.34675 2.51994 TEXT 200 -200 Left 2 ;'Step Timing -- MRM
Reply by ●August 14, 20222022-08-14
søndag den 14. august 2022 kl. 16.14.43 UTC+2 skrev Mike Monett VE3BTI:> Lasse Langwadt Christensen <lang...@fonz.dk> wrote: > [...] > > since it is for a trigger and the falling edge probably doesn't matter, > > why not a single variable voltage step into a filter, sorta like a > > time-to-amplitude in reverse > See if this works to get it on screen:the step param list needs to be one single long line
Reply by ●August 14, 20222022-08-14
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:> søndag den 14. august 2022 kl. 16.14.43 UTC+2 skrev Mike Monett VE3BTI: >> Lasse Langwadt Christensen <lang...@fonz.dk> wrote: >> [...] >> > since it is for a trigger and the falling edge probably doesn't >> > matter, > >> > why not a single variable voltage step into a filter, sorta like a >> > time-to-amplitude in reverse >> See if this works to get it on screen: > > the step param list needs to be one single long lineNo, it does not need to be one single line. Run the ASC file I posted. It runs fine in LTspice IV and XVII. It is a good idea to label each node as I have done. If you plot an unlabeled node, and make one change to the circuit, all the nodes get renumbered. So you lose the waveform on the node you want, and get some other waveform that you don't want. There is no notice that the nodes have been renumbered, so you will think you have done something to wreck the circuit. This may take a bit of wasted effort trying to figure out what you have done. If you label all the nodes, and make a change, the waveform will stay with the node you want. -- MRM
Reply by ●August 14, 20222022-08-14
søndag den 14. august 2022 kl. 18.19.28 UTC+2 skrev Mike Monett VE3BTI:> Lasse Langwadt Christensen <lang...@fonz.dk> wrote: > > > søndag den 14. august 2022 kl. 16.14.43 UTC+2 skrev Mike Monett VE3BTI: > >> Lasse Langwadt Christensen <lang...@fonz.dk> wrote: > >> [...] > >> > since it is for a trigger and the falling edge probably doesn't > >> > matter, > > > >> > why not a single variable voltage step into a filter, sorta like a > >> > time-to-amplitude in reverse > >> See if this works to get it on screen: > > > > the step param list needs to be one single long line > No, it does not need to be one single line. Run the ASC file I posted. It > runs fine in LTspice IV and XVII.you can use \n to make it multi line the schematic but it still needs to be a single line in the .asc file
Reply by ●August 14, 20222022-08-14
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:> søndag den 14. august 2022 kl. 18.19.28 UTC+2 skrev Mike Monett VE3BTI:[...]>> > the step param list needs to be one single long line >> No, it does not need to be one single line. Run the ASC file I posted. >> It > >> runs fine in LTspice IV and XVII. > > you can use \n to make it multi line the schematic but it still needs to > be a single line in the .asc fileNo it does not. Here is the line in the ASC file: TEXT 192 -160 Left 2 !.tran 0 40n 0 0.01n TEXT -56 -96 Left 2 !.step param v list 0.79061 0.80014 0.81067 0.82231 0.83517 0.84939 0.86510\n+0.88246 0.90165 0.92286 0.94630 0.97221 1.00083 1.03247 1.06744\n+1.10608 1.14879 1.19599 1.24815 1.30580 1.36952 1.43993 1.51775\n+1.60375 1.69880 1.80385 1.91994 2.04824 2.19004 2.34675 2.51994 Those line returns are Windows ASCII OD,OA, not Linux OD -- MRM
Reply by ●August 14, 20222022-08-14
søndag den 14. august 2022 kl. 19.08.50 UTC+2 skrev Mike Monett VE3BTI:> Lasse Langwadt Christensen <lang...@fonz.dk> wrote: > > > søndag den 14. august 2022 kl. 18.19.28 UTC+2 skrev Mike Monett VE3BTI: > [...] > >> > the step param list needs to be one single long line > >> No, it does not need to be one single line. Run the ASC file I posted. > >> It > > > >> runs fine in LTspice IV and XVII. > > > > you can use \n to make it multi line the schematic but it still needs to > > be a single line in the .asc file > No it does not. Here is the line in the ASC file: > TEXT 192 -160 Left 2 !.tran 0 40n 0 0.01n > TEXT -56 -96 Left 2 !.step param v list 0.79061 0.80014 0.81067 > 0.82231 0.83517 0.84939 0.86510\n+0.88246 0.90165 0.92286 > 0.94630 0.97221 1.00083 1.03247 1.06744\n+1.10608 1.14879 > 1.19599 1.24815 1.30580 1.36952 1.43993 1.51775\n+1.60375 > 1.69880 1.80385 1.91994 2.04824 2.19004 2.34675 2.51994 > Those line returns are Windows ASCII OD,OA, not Linux OD >let me spell it out: IT DOES NOT WORK it has to be one line in the .asc file
Reply by ●August 14, 20222022-08-14
Am 14.08.22 um 16:14 schrieb jlarkin@highlandsniptechnology.com:> On Sun, 14 Aug 2022 02:22:50 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > >> søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev bill....@ieee.org: >>> It strikes me that John Larkin's original idea of synthesising trapezoids can be made to work. >>> >>> You would still use a fast 14- or 16 bit DAC, but the waveform you fed into your comparator would be made up of four sequential components - all coming out of the DAC - high segment of arbitrary length, a falling edge, a low segment, and a risng edge >>> >>> With a 14-bit DAC - the LTC2000 comes to mind >>> >>> https://www.analog.com/media/en/technical-documentation/data-sheets/2000fb.pdf >>> >>> you'd synthisese the rising and falling edges of the trapezia as 16-successive steps of a staircase waveform. >> >> since it is for a trigger and the falling edge probably doesn't matter, why not a single variable voltage step into a filter, sorta like a time-to-amplitude in reverse > > My question is basically whether one can DDS a non-sinusoidal waveform > to make a faster edge into a filter and comparator, to get better time > resolution, less jitter, at low frequencies. > > Conventional thinking treats the DDS as the tail end of a Shannon > sampling system. But that requires that the signal that we're trying > to make is perfectly bandlimited, which a sine is but a trapezoid > isn't. So wave goodby to Shannon. > > So we need to synthesize a fast edge, much faster than a sine, and > poke that into an interpolation filter with a short attention span, > one that sees the smooth part of the slope but forgets the sharp > transition. Maybe synthesise an s-shaped rising edge to reduce the > signal bandwidth some. > > And of course we need to reach farther right into the phase > accumulator bits, in real life or maybe by interpolation. > > Hmmm, I could put a function, tanh or something, after the sine lookup > in my DDS sim, to speed up the mid slope. That at least helps the > comparator. Gotta think about that.You can take my VHDL design and have one of your FPGA guys replace sin(x) by sin(x) * tanh(x) and simulate it in a few seconds in Modelsim, Questasim or whatever you have. You get a pseudo-analog output. The code that fills the ROM is a single process that feels like Pascal, no concurrency. The intermediate results are even files that could be used in Matlab. That all does not have much to do with VHDL; I just choose VHDL because you need it anyway for compiling the chip. It could just as good have been C or Pascal; that would require more infrastructure such as gcc or turbo-pascal. It only generates a text file that is put into the ROM when builing the chip. Cheers, Gerhard