On Sun, 28 May 2017 07:46:05 -0500, "Tim Williams" <tiwill@seventransistorlabs.com> wrote:>"whit3rd" <whit3rd@gmail.com> wrote in message >news:d0a99d43-2f87-41b0-8ce2-fcb5b25034a2@googlegroups.com... >> What I'd really like to see, is a good symbol for a Hall effect sensor. >> The one for thermocouple is really a nuisance, it looks too much like >> just a joint in a wire. Which it IS, but it's a SPECIAL joint, and the >> wire >> types matter, and they ARE NOT IDENTIFIED in that silly symbol. So, how >> can I get the polarity right? > >Thermocouple could have the wires in different colors. Or for B&W, one >outlined and the other solid.Thermocouple wire colors are standardized. Many times. There is the USA standard, and there are many others. Red is + on one side of the Atlantic, minus on the other. -- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Can we PLEASE stop using these shitty symbols?
Started by ●May 22, 2017
Reply by ●May 28, 20172017-05-28
Reply by ●May 28, 20172017-05-28
On Sun, 28 May 2017 12:26:14 -0700 (PDT), pcdhobbs@gmail.com wrote:>>It's perfectly clear to people who understand the parts. > >I have no interest in legislating how anyone draws schematics, except maybe people who hypothetically might work for me. I'm sure your methods keep blunders under control. For myself, I'd never draw FETs like that, because the trivial extra time investment is repaid by ease of spotting cases of synapse failure, lock-up states, and so on. > >>It would be best to include every mosfet property in every schematic >>symbol: > >Sure--plus maybe a big zener to illustrate avalanche behaviour and a small tank of magic smoke. ;) > >You have to stop someplace--Big- and Little-Endians just disagree about exactly where. > >Cheers > >Phil HobbsAs I previously posted... "Besides, symbols are only there for human consumption, All that matters is how the devices netlist so that simulators (or PCB software) properly perform." So symbolize however it rings your chime. Those of us who have to communicate with non-in-house layout professionals will stick to the generally recognized symbol standards. I note that the LTspice List has degenerated from professional level circuit simulation issues down to virtually all posts being related to that no one can figure out how to associate a Spice device model or subcircuit with a symbol. Tells me a lot about the current state of electrical engineering "education" :-( But they'll all (maybe) be able to paste the "Picking up steam now, maybe our book will push it a bit." symbol >:-} ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | Thinking outside the box... producing elegant solutions. "It is not in doing what you like, but in liking what you do that is the secret of happiness." -James Barrie
Reply by ●May 28, 20172017-05-28
On Sun, 28 May 2017 12:26:14 -0700 (PDT), pcdhobbs@gmail.com wrote:>>It's perfectly clear to people who understand the parts. > >I have no interest in legislating how anyone draws schematics, except maybe people who hypothetically might work for me. I'm sure your methods keep blunders under control. For myself, I'd never draw FETs like that, because the trivial extra time investment is repaid by ease of spotting cases of synapse failure, lock-up states, and so on. > >>It would be best to include every mosfet property in every schematic >>symbol: > >Sure--plus maybe a big zener to illustrate avalanche behaviour and a small tank of magic smoke. ;) > >You have to stop someplace--Big- and Little-Endians just disagree about exactly where. > >Cheers > >Phil HobbsWhat is this endian thing about? -- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by ●May 28, 20172017-05-28
On Sun, 28 May 2017 12:07:35 -0700 (PDT), whit3rd <whit3rd@gmail.com> wrote:>On Sunday, May 28, 2017 at 10:36:47 AM UTC-7, John Larkin wrote: >> On Sun, 28 May 2017 09:59:27 -0700, Jim Thompson >> <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >> >> >On Sun, 28 May 2017 09:49:40 -0700, John Larkin >> ><jjlarkin@highlandtechnology.com> wrote: >> > >> >>On Sun, 28 May 2017 09:44:43 -0700, Jim Thompson >> >><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >> > >> >[snip] >> >>> >> >>>That "diode" representation for the source is just ghastly. >> >> >> >>Do I have to give all the money back? >> > >> >What's that supposed to mean? > >> It means that I've designed about $300e6 worth of gear, critical to >> maybe $60e9 of process, using my mosfet symbol, and it all worked, and >> I got paid. And I don't regret it. > >But, most of us are upset if we have to walk around with a sausage stuck >to our nose. It's not a suitable way to present oneself. Nor is 'source-as-diode' >a proper representation; it, too, gets in the way.Proper? Are you the Miss Manners of electronic design? A lot of gear has been sold, and a lot of books published, using the simplified mosfet symbol. -- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by ●May 28, 20172017-05-28
Den søndag den 28. maj 2017 kl. 22.19.50 UTC+2 skrev John Larkin:> On Sun, 28 May 2017 12:26:14 -0700 (PDT), pcdhobbs@gmail.com wrote: > > >>It's perfectly clear to people who understand the parts. > > > >I have no interest in legislating how anyone draws schematics, except maybe people who hypothetically might work for me. I'm sure your methods keep blunders under control. For myself, I'd never draw FETs like that, because the trivial extra time investment is repaid by ease of spotting cases of synapse failure, lock-up states, and so on. > > > >>It would be best to include every mosfet property in every schematic > >>symbol: > > > >Sure--plus maybe a big zener to illustrate avalanche behaviour and a small tank of magic smoke. ;) > > > >You have to stop someplace--Big- and Little-Endians just disagree about exactly where. > > > >Cheers > > > >Phil Hobbs > > What is this endian thing about? >I assume that it the discussion is about as silly as the original source of the term little-endian/big-endian "the "endian" names were drawn from Jonathan Swift's 1726 satire, Gulliver's Travels, in which civil war erupts over whether the big end or the little end of a boiled egg is the proper end to crack open"
Reply by ●May 28, 20172017-05-28
On Sun, 28 May 2017 13:44:54 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>Den s�ndag den 28. maj 2017 kl. 22.19.50 UTC+2 skrev John Larkin: >> On Sun, 28 May 2017 12:26:14 -0700 (PDT), pcdhobbs@gmail.com wrote: >> >> >>It's perfectly clear to people who understand the parts. >> > >> >I have no interest in legislating how anyone draws schematics, except maybe people who hypothetically might work for me. I'm sure your methods keep blunders under control. For myself, I'd never draw FETs like that, because the trivial extra time investment is repaid by ease of spotting cases of synapse failure, lock-up states, and so on. >> > >> >>It would be best to include every mosfet property in every schematic >> >>symbol: >> > >> >Sure--plus maybe a big zener to illustrate avalanche behaviour and a small tank of magic smoke. ;) >> > >> >You have to stop someplace--Big- and Little-Endians just disagree about exactly where. >> > >> >Cheers >> > >> >Phil Hobbs >> >> What is this endian thing about? >> > >I assume that it the discussion is about as silly as the original source >of the term little-endian/big-endian > >"the "endian" names were drawn from Jonathan Swift's 1726 satire, Gulliver's Travels, in which civil war erupts over whether the big end or the little end of a boiled egg is the proper end to crack open" > > >The "big endian" has the air pocket... devoid of a proper symbol >:-} ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | Thinking outside the box... producing elegant solutions. "It is not in doing what you like, but in liking what you do that is the secret of happiness." -James Barrie
Reply by ●May 28, 20172017-05-28
>I assume that it the discussion is about as silly as the original source >of the term little-endian/big-endianYup. I don't think it's a first-order issue, but I do have views about it. Thus a light touch
Reply by ●May 28, 20172017-05-28
>>I assume that it the discussion is about as silly as the original source >>of the term little-endian/big-endian>Yup. I don't think it's a first-order issue, but I do have views about it. Thus a light touchseems to be the right answer. Swift was good at that. ("Comrade Snowball" is the Trotsky character from George Orwell's "Animal Farm".) Cheers Phil Hobbs
Reply by ●May 28, 20172017-05-28
Jim Thompson wrote...> Winfield Hill wrote: >>pcdhobbs@gmail.com wrote... >>> >>> The PMOS polarity-protection circuit (gate to ground, drain to >>> +VDD, source to load) is perfectly clear using the correct symbol >>> but opaque using the shuffling, heel-dragging Big Endian one. >> >> Yes, that's a good example. But even here, it cries >> out to have the redundant diode explicitly shown. > > Required only for the cut and paste style of designer, > who has no clue how the devices actually work.Sheesh, there are plenty, they're called customers. -- Thanks, - Win
Reply by ●May 28, 20172017-05-28
John Larkin wrote...> > It would be best to include every mosfet property ... > enhancement or depletion properties. ...Now there's an issue, sometimes it's not obvious which kind of part a designer has chosen, and I've been forced to look up the listed part just to find out. Quick, is a BSS126 enhancement or depletion? How about a BSS138 or a BSS159? -- Thanks, - Win
