On Mon, 22 Jun 2020 12:43:32 -0700 (PDT), dagmargoodboat@yahoo.com wrote:>On Monday, June 22, 2020 at 3:31:29 PM UTC-4, John Larkin wrote: >> On Mon, 22 Jun 2020 11:54:30 -0700 (PDT), dagmargoodboat@yahoo.com >> wrote: >> >> >On Monday, June 22, 2020 at 1:34:21 PM UTC-4, Jeroen Belleman wrote: >> >> On 2020-06-22 17:51, jlarkin@highlandsniptechnology.com wrote: >> >> >[...] >> >> > I wasn't happy with my PCBWAY board. Resolution and registration were >> >> > bad, and they didn't read my stackup specs. Their default 4-layer >> >> > stack has *four mils* of dielectric between layers 1 and 2, and >> >> > between 3 and 4. That is really nasty. That stack is common in cheap >> >> > chinese proto houses. >> >> >> >> That's nasty indeed. Who'd use a stackup like that? >> >> >> >> Jeroen Belleman >> > >> >I might! Just two days ago I was calculating how much capacitance I >> >could squeeze out of a PCB pour. Consulting my calculator, 0,1mm spacing >> >and 5 x 5cm gets me 97nF with just 100 layers' stackup :) >> > >> >Cheers, >> >James Arthur >> >> Figure a tempco ballpark +900 PPM. And a lot of nasty DA. > >I need amps at kV in <1 ns, that's the appeal. I like the >DA -- DA = damping, which is a plus. But the '100 layers' >part is admittedly, <cough>, a slight inconvenience. > >Grins, >JamesWait, wait, I have an idea: use capacitors! 1 ns isn't very fast. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
GaN With the Wind
Started by ●June 21, 2020
Reply by ●June 22, 20202020-06-22
Reply by ●June 22, 20202020-06-22
On Monday, June 22, 2020 at 5:31:59 PM UTC-4, John Larkin wrote:> On Mon, 22 Jun 2020 12:43:32 -0700 (PDT), dagmargoodboat@yahoo.com > wrote: > > >On Monday, June 22, 2020 at 3:31:29 PM UTC-4, John Larkin wrote: > >> On Mon, 22 Jun 2020 11:54:30 -0700 (PDT), dagmargoodboat@yahoo.com > >> wrote: > >> > >> >On Monday, June 22, 2020 at 1:34:21 PM UTC-4, Jeroen Belleman wrote: > >> >> On 2020-06-22 17:51, jlarkin@highlandsniptechnology.com wrote: > >> >> >[...] > >> >> > I wasn't happy with my PCBWAY board. Resolution and registration were > >> >> > bad, and they didn't read my stackup specs. Their default 4-layer > >> >> > stack has *four mils* of dielectric between layers 1 and 2, and > >> >> > between 3 and 4. That is really nasty. That stack is common in cheap > >> >> > chinese proto houses. > >> >> > >> >> That's nasty indeed. Who'd use a stackup like that? > >> >> > >> >> Jeroen Belleman > >> > > >> >I might! Just two days ago I was calculating how much capacitance I > >> >could squeeze out of a PCB pour. Consulting my calculator, 0,1mm spacing > >> >and 5 x 5cm gets me 97nF with just 100 layers' stackup :) > >> > > >> >Cheers, > >> >James Arthur > >> > >> Figure a tempco ballpark +900 PPM. And a lot of nasty DA. > > > >I need amps at kV in <1 ns, that's the appeal. I like the > >DA -- DA = damping, which is a plus. But the '100 layers' > >part is admittedly, <cough>, a slight inconvenience. > > > >Grins, > >James > > Wait, wait, I have an idea: use capacitors!With all their nasty inductance? Whoddathunk that? :) (I've been wanting to use a PCB cap ever since a 1974 Scientific American 'Amateur Scientist' column describing an FR-4 traveling-wave spark-gap-excited nitrogen laser.) (Yeah, I know--sideways caps, lots of them, etc. etc.)> 1 ns isn't very fast.Slewing a kV in a couple ns may not impress the Lords of Picoseconds as much of a big deal, but the amps/ns sure makes big impressions on PCB traces everywhere! Grins, James Arthur
Reply by ●June 22, 20202020-06-22
dagmargoodboat@yahoo.com wrote:> As I design yet another little switcher, I notice it's getting > more and more tempting to swap ye olde MOS FET for a shiny > new GaN-speck.And SiC at the upper voltage end. Even the reasonably cheap ones have 800mOhm at 1700V -- what kind of magic is that?!> Electrically superior in almost every respect, the GaN FETs' > drawbacks are thermal (not a problem in this case), and their > tee-nine-sie .9x.9mm bare-chip packages.There is no such problems with the SiC parts, but asymetric HV gate drive is. I have just completed a 117-900VDC input 47W PSR flyback based on a SiC part and 3C95 planar ferrites. At low line and full load the converter is not even warm. This is insane. Best regards, Piotr
Reply by ●June 22, 20202020-06-22
On Mon, 22 Jun 2020 15:43:10 -0700 (PDT), dagmargoodboat@yahoo.com wrote:>On Monday, June 22, 2020 at 5:31:59 PM UTC-4, John Larkin wrote: >> On Mon, 22 Jun 2020 12:43:32 -0700 (PDT), dagmargoodboat@yahoo.com >> wrote: >> >> >On Monday, June 22, 2020 at 3:31:29 PM UTC-4, John Larkin wrote: >> >> On Mon, 22 Jun 2020 11:54:30 -0700 (PDT), dagmargoodboat@yahoo.com >> >> wrote: >> >> >> >> >On Monday, June 22, 2020 at 1:34:21 PM UTC-4, Jeroen Belleman wrote: >> >> >> On 2020-06-22 17:51, jlarkin@highlandsniptechnology.com wrote: >> >> >> >[...] >> >> >> > I wasn't happy with my PCBWAY board. Resolution and registration were >> >> >> > bad, and they didn't read my stackup specs. Their default 4-layer >> >> >> > stack has *four mils* of dielectric between layers 1 and 2, and >> >> >> > between 3 and 4. That is really nasty. That stack is common in cheap >> >> >> > chinese proto houses. >> >> >> >> >> >> That's nasty indeed. Who'd use a stackup like that? >> >> >> >> >> >> Jeroen Belleman >> >> > >> >> >I might! Just two days ago I was calculating how much capacitance I >> >> >could squeeze out of a PCB pour. Consulting my calculator, 0,1mm spacing >> >> >and 5 x 5cm gets me 97nF with just 100 layers' stackup :) >> >> > >> >> >Cheers, >> >> >James Arthur >> >> >> >> Figure a tempco ballpark +900 PPM. And a lot of nasty DA. >> > >> >I need amps at kV in <1 ns, that's the appeal. I like the >> >DA -- DA = damping, which is a plus. But the '100 layers' >> >part is admittedly, <cough>, a slight inconvenience. >> > >> >Grins, >> >James >> >> Wait, wait, I have an idea: use capacitors! > >With all their nasty inductance? Whoddathunk that? :) >(I've been wanting to use a PCB cap ever since a 1974 Scientific >American 'Amateur Scientist' column describing an FR-4 traveling-wave >spark-gap-excited nitrogen laser.) > >(Yeah, I know--sideways caps, lots of them, etc. etc.) > >> 1 ns isn't very fast. > >Slewing a kV in a couple ns may not impress the Lords of Picoseconds as >much of a big deal, but the amps/ns sure makes big impressions on PCB >traces everywhere! > >Grins, >James Arthur1 amp/ns is 1 volt into 1 nH. You'd never miss that. I could tell my drift-step-recovery diode story again. My Pockels Cell driver ain't bad: http://www.highlandtechnology.com/DSS/T850DS.shtml The Pockels cells don't like long-term DC, so the AC coupling option is a couple of caps in parallel. The real problem was toasting the Phoenix terminal block from dielectric losses. The green gunk they use has worse losses than FR4! -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by ●June 22, 20202020-06-22
On Tue, 23 Jun 2020 01:32:40 +0200, Piotr Wyderski <peter.pan@neverland.mil> wrote:>dagmargoodboat@yahoo.com wrote: > >> As I design yet another little switcher, I notice it's getting >> more and more tempting to swap ye olde MOS FET for a shiny >> new GaN-speck. > >And SiC at the upper voltage end. Even the reasonably cheap ones have >800mOhm at 1700V -- what kind of magic is that?! > >> Electrically superior in almost every respect, the GaN FETs' >> drawbacks are thermal (not a problem in this case), and their >> tee-nine-sie .9x.9mm bare-chip packages. > >There is no such problems with the SiC parts, but asymetric HV gate >drive is. > >I have just completed a 117-900VDC input 47W PSR flyback based on a SiC >part and 3C95 planar ferrites. At low line and full load the converter >is not even warm. This is insane. > > Best regards, PiotrI had to make my own GaN gate driver, to drive a Cree SiC fet. -5 to +18 in about a nanosecond. That took a few tries to get right. Tiny logic >> GaN >> SiC. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by ●June 23, 20202020-06-23
On Monday, June 22, 2020 at 8:48:44 PM UTC-4, John Larkin wrote:> On Mon, 22 Jun 2020 15:43:10 -0700 (PDT), dagmargoodboat@yahoo.com > wrote: > > >On Monday, June 22, 2020 at 5:31:59 PM UTC-4, John Larkin wrote: > >> On Mon, 22 Jun 2020 12:43:32 -0700 (PDT), dagmargoodboat@yahoo.com > >> wrote: > >> > >> >On Monday, June 22, 2020 at 3:31:29 PM UTC-4, John Larkin wrote: > >> >> On Mon, 22 Jun 2020 11:54:30 -0700 (PDT), dagmargoodboat@yahoo.com > >> >> wrote: > >> >> > >> >> >On Monday, June 22, 2020 at 1:34:21 PM UTC-4, Jeroen Belleman wrote: > >> >> >> On 2020-06-22 17:51, jlarkin@highlandsniptechnology.com wrote: > >> >> >> >[...] > >> >> >> > I wasn't happy with my PCBWAY board. Resolution and registration were > >> >> >> > bad, and they didn't read my stackup specs. Their default 4-layer > >> >> >> > stack has *four mils* of dielectric between layers 1 and 2, and > >> >> >> > between 3 and 4. That is really nasty. That stack is common in cheap > >> >> >> > chinese proto houses. > >> >> >> > >> >> >> That's nasty indeed. Who'd use a stackup like that? > >> >> >> > >> >> >> Jeroen Belleman > >> >> > > >> >> >I might! Just two days ago I was calculating how much capacitance I > >> >> >could squeeze out of a PCB pour. Consulting my calculator, 0,1mm spacing > >> >> >and 5 x 5cm gets me 97nF with just 100 layers' stackup :) > >> >> > > >> >> >Cheers, > >> >> >James Arthur > >> >> > >> >> Figure a tempco ballpark +900 PPM. And a lot of nasty DA. > >> > > >> >I need amps at kV in <1 ns, that's the appeal. I like the > >> >DA -- DA = damping, which is a plus. But the '100 layers' > >> >part is admittedly, <cough>, a slight inconvenience. > >> > > >> >Grins, > >> >James > >> > >> Wait, wait, I have an idea: use capacitors! > > > >With all their nasty inductance? Whoddathunk that? :) > >(I've been wanting to use a PCB cap ever since a 1974 Scientific > >American 'Amateur Scientist' column describing an FR-4 traveling-wave > >spark-gap-excited nitrogen laser.) > > > >(Yeah, I know--sideways caps, lots of them, etc. etc.) > > > >> 1 ns isn't very fast. > > > >Slewing a kV in a couple ns may not impress the Lords of Picoseconds as > >much of a big deal, but the amps/ns sure makes big impressions on PCB > >traces everywhere! > > > >Grins, > >James Arthur > > 1 amp/ns is 1 volt into 1 nH. You'd never miss that.I'm pulling about 10A/ns from the cap. Since I need both lots of bulk storage *and* a precision voltage step, that means I'm stuck with using combinations of caps to get the overall desired effect. A 2012 1uF x 2kV cap with 10pH ESL sure would be handy.> I could tell my drift-step-recovery diode story again. > > My Pockels Cell driver ain't bad: > > http://www.highlandtechnology.com/DSS/T850DS.shtml > > The Pockels cells don't like long-term DC, so the AC coupling option > is a couple of caps in parallel. The real problem was toasting the > Phoenix terminal block from dielectric losses. The green gunk they use > has worse losses than FR4!Now *that's* a cool story. But then you're always burning things up and tormenting innocent electronic parts, aren't you? (You've inspired some of that in me, too!) Brute! I've still got to do the overvoltage-the-MOSFET-gate-for-a-ns trick some time. But I think GaN has made that project moot. Cheers, James Arthur
Reply by ●June 23, 20202020-06-23
On Mon, 22 Jun 2020 20:04:18 -0700 (PDT), dagmargoodboat@yahoo.com wrote:>On Monday, June 22, 2020 at 8:48:44 PM UTC-4, John Larkin wrote: >> On Mon, 22 Jun 2020 15:43:10 -0700 (PDT), dagmargoodboat@yahoo.com >> wrote: >> >> >On Monday, June 22, 2020 at 5:31:59 PM UTC-4, John Larkin wrote: >> >> On Mon, 22 Jun 2020 12:43:32 -0700 (PDT), dagmargoodboat@yahoo.com >> >> wrote: >> >> >> >> >On Monday, June 22, 2020 at 3:31:29 PM UTC-4, John Larkin wrote: >> >> >> On Mon, 22 Jun 2020 11:54:30 -0700 (PDT), dagmargoodboat@yahoo.com >> >> >> wrote: >> >> >> >> >> >> >On Monday, June 22, 2020 at 1:34:21 PM UTC-4, Jeroen Belleman wrote: >> >> >> >> On 2020-06-22 17:51, jlarkin@highlandsniptechnology.com wrote: >> >> >> >> >[...] >> >> >> >> > I wasn't happy with my PCBWAY board. Resolution and registration were >> >> >> >> > bad, and they didn't read my stackup specs. Their default 4-layer >> >> >> >> > stack has *four mils* of dielectric between layers 1 and 2, and >> >> >> >> > between 3 and 4. That is really nasty. That stack is common in cheap >> >> >> >> > chinese proto houses. >> >> >> >> >> >> >> >> That's nasty indeed. Who'd use a stackup like that? >> >> >> >> >> >> >> >> Jeroen Belleman >> >> >> > >> >> >> >I might! Just two days ago I was calculating how much capacitance I >> >> >> >could squeeze out of a PCB pour. Consulting my calculator, 0,1mm spacing >> >> >> >and 5 x 5cm gets me 97nF with just 100 layers' stackup :) >> >> >> > >> >> >> >Cheers, >> >> >> >James Arthur >> >> >> >> >> >> Figure a tempco ballpark +900 PPM. And a lot of nasty DA. >> >> > >> >> >I need amps at kV in <1 ns, that's the appeal. I like the >> >> >DA -- DA = damping, which is a plus. But the '100 layers' >> >> >part is admittedly, <cough>, a slight inconvenience. >> >> > >> >> >Grins, >> >> >James >> >> >> >> Wait, wait, I have an idea: use capacitors! >> > >> >With all their nasty inductance? Whoddathunk that? :) >> >(I've been wanting to use a PCB cap ever since a 1974 Scientific >> >American 'Amateur Scientist' column describing an FR-4 traveling-wave >> >spark-gap-excited nitrogen laser.) >> > >> >(Yeah, I know--sideways caps, lots of them, etc. etc.) >> > >> >> 1 ns isn't very fast. >> > >> >Slewing a kV in a couple ns may not impress the Lords of Picoseconds as >> >much of a big deal, but the amps/ns sure makes big impressions on PCB >> >traces everywhere! >> > >> >Grins, >> >James Arthur >> >> 1 amp/ns is 1 volt into 1 nH. You'd never miss that. > >I'm pulling about 10A/ns from the cap. Since I need both lots of >bulk storage *and* a precision voltage step, that means I'm stuck >with using combinations of caps to get the overall desired effect. >A 2012 1uF x 2kV cap with 10pH ESL sure would be handy. > >> I could tell my drift-step-recovery diode story again. >> >> My Pockels Cell driver ain't bad: >> >> http://www.highlandtechnology.com/DSS/T850DS.shtml >> >> The Pockels cells don't like long-term DC, so the AC coupling option >> is a couple of caps in parallel. The real problem was toasting the >> Phoenix terminal block from dielectric losses. The green gunk they use >> has worse losses than FR4! > >Now *that's* a cool story. But then you're always burning things up >and tormenting innocent electronic parts, aren't you? (You've inspired >some of that in me, too!) Brute!Fireworks are illegal in California. Gotta have fun somehow.> >I've still got to do the overvoltage-the-MOSFET-gate-for-a-ns trick >some time. But I think GaN has made that project moot.I found that adding a small inductor in series with a SiC gate helped a lot. SiC fets have a lot of internal gate series resistance (some, a very lot) so a little L makes the internal/actual gate voltage, hidden behind that resistance, a lot snappier. C2M0280120D, 27 nH. -- John Larkin Highland Technology, Inc Science teaches us to doubt. Claude Bernard
Reply by ●June 23, 20202020-06-23
On Monday, June 22, 2020 at 7:32:44 PM UTC-4, Piotr Wyderski wrote:> dagmargoodboat@yahoo.com wrote: > > > As I design yet another little switcher, I notice it's getting > > more and more tempting to swap ye olde MOS FET for a shiny > > new GaN-speck. > > And SiC at the upper voltage end. Even the reasonably cheap ones have > 800mOhm at 1700V -- what kind of magic is that?! > > > Electrically superior in almost every respect, the GaN FETs' > > drawbacks are thermal (not a problem in this case), and their > > tee-nine-sie .9x.9mm bare-chip packages. > > There is no such problems with the SiC parts, but asymetric HV gate > drive is. > > I have just completed a 117-900VDC input 47W PSR flyback based on a SiC > part and 3C95 planar ferrites. At low line and full load the converter > is not even warm. This is insane. > > Best regards, PiotrThe Wolfspeed/Cree C2M1000170J is my all-time favorite FET, a real workhorse. Magnificent package, too. Cheers, James Arthur
Reply by ●June 23, 20202020-06-23
On Mon, 22 Jun 2020 20:47:12 -0700 (PDT), dagmargoodboat@yahoo.com wrote:>On Monday, June 22, 2020 at 7:32:44 PM UTC-4, Piotr Wyderski wrote: >> dagmargoodboat@yahoo.com wrote: >> >> > As I design yet another little switcher, I notice it's getting >> > more and more tempting to swap ye olde MOS FET for a shiny >> > new GaN-speck. >> >> And SiC at the upper voltage end. Even the reasonably cheap ones have >> 800mOhm at 1700V -- what kind of magic is that?! >> >> > Electrically superior in almost every respect, the GaN FETs' >> > drawbacks are thermal (not a problem in this case), and their >> > tee-nine-sie .9x.9mm bare-chip packages. >> >> There is no such problems with the SiC parts, but asymetric HV gate >> drive is. >> >> I have just completed a 117-900VDC input 47W PSR flyback based on a SiC >> part and 3C95 planar ferrites. At low line and full load the converter >> is not even warm. This is insane. >> >> Best regards, Piotr > >The Wolfspeed/Cree C2M1000170J is my all-time favorite FET, a real >workhorse. Magnificent package, too. > >Cheers, >James ArthurI'm using a C2M0280120D (TO247, 1200V, 280 mOhm on) part on a water-cooled plate with an aluminum nitride insulator. The actual chip inside is tiny, so that huge package is just a heat spreader. -- John Larkin Highland Technology, Inc Science teaches us to doubt. Claude Bernard
Reply by ●June 23, 20202020-06-23
dagmargoodboat@yahoo.com wrote:> The Wolfspeed/Cree C2M1000170J is my all-time favorite FET, a real > workhorse. Magnificent package, too.Yes, I have ended up with exactly this part. Started with SCT2750, but the Cree part is smaller and has the Kelvin gate drive pins, which improves reliability. Best regards, Piotr
