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GaN With the Wind

Started by Unknown June 21, 2020
As I design yet another little switcher, I notice it's getting
more and more tempting to swap ye olde MOS FET for a shiny
new GaN-speck.

Electrically superior in almost every respect, the GaN FETs'
drawbacks are thermal (not a problem in this case), and their
tee-nine-sie .9x.9mm bare-chip packages.

e.g.
  T.I. CSD19831Q3: 100V, Rds(on)=50mohm, Cin=350pF, Coss=70pF, Crss=13pF
  EPC EPC2036: 100V, Rds(on)~=60mohm, Cin=43pF, Coss=25pF, Crss<1pF

I re-worked a chip-scale part with hot air and a hot plate by hand.
Took me a zillion tries to get it done--that was a nuisance.


Cheers,
James Arthur

dagmargoodboat@yahoo.com wrote in
news:21cd1627-d5b6-437c-9ad8-2bbc2ac628fao@googlegroups.com: 

> As I design yet another little switcher, I notice it's getting > more and more tempting to swap ye olde MOS FET for a shiny > new GaN-speck. > > Electrically superior in almost every respect, the GaN FETs' > drawbacks are thermal (not a problem in this case), and their > tee-nine-sie .9x.9mm bare-chip packages. > > e.g. > T.I. CSD19831Q3: 100V, Rds(on)=50mohm, Cin=350pF, Coss=70pF, > Crss=13pF EPC EPC2036: 100V, Rds(on)~=60mohm, Cin=43pF, > Coss=25pF, Crss<1pF > > I re-worked a chip-scale part with hot air and a hot plate by > hand. Took me a zillion tries to get it done--that was a nuisance. > > > Cheers, > James Arthur > >
Looks like you've GaN fishin' for performance. You're a real GaNer. We'll never get you back.
On Sunday, June 21, 2020 at 7:32:35 PM UTC-4, dagmarg...@yahoo.com wrote:
> As I design yet another little switcher, I notice it's getting > more and more tempting to swap ye olde MOS FET for a shiny > new GaN-speck. > > Electrically superior in almost every respect, the GaN FETs' > drawbacks are thermal (not a problem in this case), and their > tee-nine-sie .9x.9mm bare-chip packages. > > e.g. > T.I. CSD19831Q3: 100V, Rds(on)=50mohm, Cin=350pF, Coss=70pF, Crss=13pF > EPC EPC2036: 100V, Rds(on)~=60mohm, Cin=43pF, Coss=25pF, Crss<1pF > > I re-worked a chip-scale part with hot air and a hot plate by hand. > Took me a zillion tries to get it done--that was a nuisance.
I assume you have a good microscope/ viewer. Is the problem needing tiny tools/ manipulators? George H.
> > > Cheers, > James Arthur
On Sun, 21 Jun 2020 16:32:31 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

>As I design yet another little switcher, I notice it's getting >more and more tempting to swap ye olde MOS FET for a shiny >new GaN-speck. > >Electrically superior in almost every respect, the GaN FETs' >drawbacks are thermal (not a problem in this case), and their >tee-nine-sie .9x.9mm bare-chip packages. > >e.g. > T.I. CSD19831Q3: 100V, Rds(on)=50mohm, Cin=350pF, Coss=70pF, Crss=13pF
> EPC EPC2036: 100V, Rds(on)~=60mohm, Cin=43pF, Coss=25pF, Crss<1pF
The near-zero Miller capacitance is a miracle to work with. You can get away with circuits that would be hopelessly naiive with mosfets. But there are novel ways to destroy an EPC part. They prefer to die than avalanche, and a bit too much gate drive does strange things.
> >I re-worked a chip-scale part with hot air and a hot plate by hand. >Took me a zillion tries to get it done--that was a nuisance. > > >Cheers, >James Arthur
I love the EPC parts, but I can't solder or replace them myself. I have experts that can do that. We use solder-mask-defined pads, which some board houses can do right https://www.dropbox.com/s/5xwy909yns4tjae/T577C_pcb_3.png?raw=1 and some not so right. https://www.dropbox.com/s/v6isv7k1t3fre0w/PCBWAY_Mask.jpg?raw=1 These are for the tiniest 4-ball parts, same size as the 2036. The tiny BGA parts are mechanically fragile, so I glop them with drops of Bondic first thing. Here's a 50 volt pulse, 25v into a 50 ohm load: https://www.dropbox.com/s/s51w4tntlep6lp1/T577_50V.JPG?raw=1 with < $2 worth of GaN fets. The circuit can do 100v. That pulse is lowpass filtered for beauty. It's natively faster but kind of ratty looking. -- John Larkin Highland Technology, Inc Science teaches us to doubt. Claude Bernard
On Sunday, June 21, 2020 at 9:28:28 PM UTC-4, George Herold wrote:
> On Sunday, June 21, 2020 at 7:32:35 PM UTC-4, dagmarg...@yahoo.com wrote: > > As I design yet another little switcher, I notice it's getting > > more and more tempting to swap ye olde MOS FET for a shiny > > new GaN-speck. > > > > Electrically superior in almost every respect, the GaN FETs' > > drawbacks are thermal (not a problem in this case), and their > > tee-nine-sie .9x.9mm bare-chip packages. > > > > e.g. > > T.I. CSD19831Q3: 100V, Rds(on)=50mohm, Cin=350pF, Coss=70pF, Crss=13pF > > EPC EPC2036: 100V, Rds(on)~=60mohm, Cin=43pF, Coss=25pF, Crss<1pF > > > > I re-worked a chip-scale part with hot air and a hot plate by hand. > > Took me a zillion tries to get it done--that was a nuisance. > I assume you have a good microscope/ viewer. > Is the problem needing tiny tools/ manipulators? > > George H.
I don't have a microscope & haven't needed one. I just did it caveman-style. (Are we still allowed to say 'caveman'?) The difficulties were many, ranging from seeing any markings on the mirror-shiny silver die's back surface, to applying tiny bits of solder to refresh the super-close balls, not blowing the part off with the hot air, getting all the balls to solder, not shorting, not having the die shift off the lands, etc. Just about every problem you could have, I had. But eventually, it worked. Cheers, James Arthur
On Sunday, June 21, 2020 at 9:50:37 PM UTC-4, jla...@highlandsniptechnology.com wrote:
> On Sun, 21 Jun 2020 16:32:31 -0700 (PDT), dagmargoodboat@yahoo.com > wrote: > > >As I design yet another little switcher, I notice it's getting > >more and more tempting to swap ye olde MOS FET for a shiny > >new GaN-speck. > > > >Electrically superior in almost every respect, the GaN FETs' > >drawbacks are thermal (not a problem in this case), and their > >tee-nine-sie .9x.9mm bare-chip packages. > > > >e.g. > > T.I. CSD19831Q3: 100V, Rds(on)=50mohm, Cin=350pF, Coss=70pF, Crss=13pF > > > > > EPC EPC2036: 100V, Rds(on)~=60mohm, Cin=43pF, Coss=25pF, Crss<1pF > > The near-zero Miller capacitance is a miracle to work with. You can > get away with circuits that would be hopelessly naiive with mosfets. > > But there are novel ways to destroy an EPC part. They prefer to die > than avalanche, and a bit too much gate drive does strange things.
The vendors say GaN FETs don't avalanche, and yes, the gate drive affecting reverse conduction will take a bit of planning when inductances ring. I saw EPC and GaN Systems literature today to the effect that GaN should operate to 300C. EPC's website says GaN theoretically has three orders of magnitude of improvement left in it, whatever that means.
> >I re-worked a chip-scale part with hot air and a hot plate by hand. > >Took me a zillion tries to get it done--that was a nuisance. > > > > > >Cheers, > >James Arthur > > I love the EPC parts, but I can't solder or replace them myself. I > have experts that can do that. > > We use solder-mask-defined pads, which some board houses can do right > > https://www.dropbox.com/s/5xwy909yns4tjae/T577C_pcb_3.png?raw=1 > > and some not so right. > > https://www.dropbox.com/s/v6isv7k1t3fre0w/PCBWAY_Mask.jpg?raw=1 > > These are for the tiniest 4-ball parts, same size as the 2036. The > tiny BGA parts are mechanically fragile, so I glop them with drops of > Bondic first thing.
Glopping 'em seems smart. The 1x1mm CSP I re-worked was amazingly fragile--the pads are so tiny, a little sideways accidental tap rips them right off. I like the back-door thermal access. That might make up for the poor pads-to-board path.
> Here's a 50 volt pulse, 25v into a 50 ohm load: > > https://www.dropbox.com/s/s51w4tntlep6lp1/T577_50V.JPG?raw=1 > > with < $2 worth of GaN fets. The circuit can do 100v. > > That pulse is lowpass filtered for beauty. It's natively faster but > kind of ratty looking.
That's pretty. Cheers, James
On Sunday, June 21, 2020 at 9:58:56 PM UTC-4, dagmarg...@yahoo.com wrote:
> On Sunday, June 21, 2020 at 9:28:28 PM UTC-4, George Herold wrote: > > On Sunday, June 21, 2020 at 7:32:35 PM UTC-4, dagmarg...@yahoo.com wrote: > > > As I design yet another little switcher, I notice it's getting > > > more and more tempting to swap ye olde MOS FET for a shiny > > > new GaN-speck. > > > > > > Electrically superior in almost every respect, the GaN FETs' > > > drawbacks are thermal (not a problem in this case), and their > > > tee-nine-sie .9x.9mm bare-chip packages. > > > > > > e.g. > > > T.I. CSD19831Q3: 100V, Rds(on)=50mohm, Cin=350pF, Coss=70pF, Crss=13pF > > > EPC EPC2036: 100V, Rds(on)~=60mohm, Cin=43pF, Coss=25pF, Crss<1pF > > > > > > I re-worked a chip-scale part with hot air and a hot plate by hand. > > > Took me a zillion tries to get it done--that was a nuisance. > > I assume you have a good microscope/ viewer. > > Is the problem needing tiny tools/ manipulators? > > > > George H. > > I don't have a microscope & haven't needed one. I just did it > caveman-style. (Are we still allowed to say 'caveman'?)
Oh! James on someones advice here, I bought a ~$70 dollar chinese 'viewer' single fairly long range microscope and lcd view screen above. I tried some fine (for me) soldering with blue wire wrap wire (30 mil?) Anyway it's totally worth it. At maximum focus there's about a 1" working distance. (max focus is reported to be x1k... I measured around that (with big error bars.. too lazy to get calipers from shop.) I'll have to look back to find the brand name if you have interest. I only says 'microscope' on the outside and when I turn it on. (I can give you the version number :^) George H. If I search SED for tardigrade, I can probably find it.
> > The difficulties were many, ranging from seeing any markings on the > mirror-shiny silver die's back surface, to applying tiny bits of > solder to refresh the super-close balls, not blowing the part off > with the hot air, getting all the balls to solder, not shorting, > not having the die shift off the lands, etc. > > Just about every problem you could have, I had. > > But eventually, it worked. > > Cheers, > James Arthur
Am 22.06.20 um 01:32 schrieb dagmargoodboat@yahoo.com:
> As I design yet another little switcher, I notice it's getting > more and more tempting to swap ye olde MOS FET for a shiny > new GaN-speck. > > Electrically superior in almost every respect, the GaN FETs' > drawbacks are thermal (not a problem in this case), and their > tee-nine-sie .9x.9mm bare-chip packages. > > e.g. > T.I. CSD19831Q3: 100V, Rds(on)=50mohm, Cin=350pF, Coss=70pF, Crss=13pF > EPC EPC2036: 100V, Rds(on)~=60mohm, Cin=43pF, Coss=25pF, Crss<1pF > > I re-worked a chip-scale part with hot air and a hot plate by hand. > Took me a zillion tries to get it done--that was a nuisance.
I was more lucky. My first 2 tries worked immediately with just a little bit of hot air. Very little, or they fly away. That was a test structure from a corner of a larger board made by PCBWAY. HAL, I removed the excess tin with some unsolder braid and used paste then. PCBWAY spotted the mask on the pad as designed by EPC's Altium example. Worked after declaring it OK. < https://www.flickr.com/photos/137684711@N07/50032925082/in/dateposted-public/ > between the 4 1210 caps and the 2 fat vias. cheers, Gerhard
On Mon, 22 Jun 2020 10:12:30 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:

>Am 22.06.20 um 01:32 schrieb dagmargoodboat@yahoo.com: >> As I design yet another little switcher, I notice it's getting >> more and more tempting to swap ye olde MOS FET for a shiny >> new GaN-speck. >> >> Electrically superior in almost every respect, the GaN FETs' >> drawbacks are thermal (not a problem in this case), and their >> tee-nine-sie .9x.9mm bare-chip packages. >> >> e.g. >> T.I. CSD19831Q3: 100V, Rds(on)=50mohm, Cin=350pF, Coss=70pF, Crss=13pF >> EPC EPC2036: 100V, Rds(on)~=60mohm, Cin=43pF, Coss=25pF, Crss<1pF >> >> I re-worked a chip-scale part with hot air and a hot plate by hand. >> Took me a zillion tries to get it done--that was a nuisance. > > >I was more lucky. My first 2 tries worked immediately with just a >little bit of hot air. Very little, or they fly away. >That was a test structure from a corner of a larger board made >by PCBWAY. HAL, I removed the excess tin with some unsolder braid >and used paste then. >PCBWAY spotted the mask on the pad as designed by EPC's Altium example. >Worked after declaring it OK. > > >< >https://www.flickr.com/photos/137684711@N07/50032925082/in/dateposted-public/ > > >between the 4 1210 caps and the 2 fat vias. > > >cheers, Gerhard
I wasn't happy with my PCBWAY board. Resolution and registration were bad, and they didn't read my stackup specs. Their default 4-layer stack has *four mils* of dielectric between layers 1 and 2, and between 3 and 4. That is really nasty. That stack is common in cheap chinese proto houses. https://www.dropbox.com/s/p3vpbaofzqurebz/Z462_PCB_Way_2.png?raw=1 https://www.dropbox.com/s/v6isv7k1t3fre0w/PCBWAY_Mask.jpg?raw=1 That would be OK for slow, not very demanding stuff. We always buy gold flash, ENIG boards, whicg are nice and planar and solder very well. -- John Larkin Highland Technology, Inc Science teaches us to doubt. Claude Bernard
On 2020-06-22 17:51, jlarkin@highlandsniptechnology.com wrote:
>[...] > I wasn't happy with my PCBWAY board. Resolution and registration were > bad, and they didn't read my stackup specs. Their default 4-layer > stack has *four mils* of dielectric between layers 1 and 2, and > between 3 and 4. That is really nasty. That stack is common in cheap > chinese proto houses.
That's nasty indeed. Who'd use a stackup like that? Jeroen Belleman