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GaN With the Wind

Started by Unknown June 21, 2020
> (Yeah, I know--sideways caps, lots of them, etc. etc.) > > > 1 ns isn't very fast. > > Slewing a kV in a couple ns may not impress the Lords of Picoseconds as > much of a big deal, but the amps/ns sure makes big impressions on PCB > traces everywhere! > > Grins, > James Arthur
just a side comment... 1 ps is pretty fast for ESD switching. I recall seeing a photo <10ps being measured on ESD. Look up Toepler's Law. https://duckduckgo.com/?q=max+Toepler+law&t=ffcm&ia=web https://ieeexplore.ieee.org/document/4783473?section=abstract - you know that ionization like SCR's is an avalanche-effect or "Townsend Discharge" or negative incremental ESR . - slow trigger, and conduction in __ picosecond time. It might cause some EMI issues if radiated in a SMPS design. ;)
> I have just completed a 117-900VDC input 47W PSR flyback based on a SiC
part and 3C95 planar ferrites. At low line and full load the converter is not even warm. This is insane. Best regards, Piotr Good work Tony
On Monday, June 22, 2020 at 11:40:10 PM UTC-4, jla...@highlandsniptechnology.com wrote:
> On Mon, 22 Jun 2020 20:04:18 -0700 (PDT), dagmargoodboat@yahoo.com > wrote: > > >On Monday, June 22, 2020 at 8:48:44 PM UTC-4, John Larkin wrote: > >> On Mon, 22 Jun 2020 15:43:10 -0700 (PDT), dagmargoodboat@yahoo.com > >> wrote: > >> > >> >On Monday, June 22, 2020 at 5:31:59 PM UTC-4, John Larkin wrote: > >> >> On Mon, 22 Jun 2020 12:43:32 -0700 (PDT), dagmargoodboat@yahoo.com > >> >> wrote: > >> >> > >> >> >On Monday, June 22, 2020 at 3:31:29 PM UTC-4, John Larkin wrote: > >> >> >> On Mon, 22 Jun 2020 11:54:30 -0700 (PDT), dagmargoodboat@yahoo.com > >> >> >> wrote: > >> >> >> > >> >> >> >On Monday, June 22, 2020 at 1:34:21 PM UTC-4, Jeroen Belleman wrote: > >> >> >> >> On 2020-06-22 17:51, jlarkin@highlandsniptechnology.com wrote: > >> >> >> >> >[...] > >> >> >> >> > I wasn't happy with my PCBWAY board. Resolution and registration were > >> >> >> >> > bad, and they didn't read my stackup specs. Their default 4-layer > >> >> >> >> > stack has *four mils* of dielectric between layers 1 and 2, and > >> >> >> >> > between 3 and 4. That is really nasty. That stack is common in cheap > >> >> >> >> > chinese proto houses. > >> >> >> >> > >> >> >> >> That's nasty indeed. Who'd use a stackup like that? > >> >> >> >> > >> >> >> >> Jeroen Belleman > >> >> >> > > >> >> >> >I might! Just two days ago I was calculating how much capacitance I > >> >> >> >could squeeze out of a PCB pour. Consulting my calculator, 0,1mm spacing > >> >> >> >and 5 x 5cm gets me 97nF with just 100 layers' stackup :) > >> >> >> > > >> >> >> >Cheers, > >> >> >> >James Arthur > >> >> >> > >> >> >> Figure a tempco ballpark +900 PPM. And a lot of nasty DA. > >> >> > > >> >> >I need amps at kV in <1 ns, that's the appeal. I like the > >> >> >DA -- DA = damping, which is a plus. But the '100 layers' > >> >> >part is admittedly, <cough>, a slight inconvenience. > >> >> > > >> >> >Grins, > >> >> >James > >> >> > >> >> Wait, wait, I have an idea: use capacitors! > >> > > >> >With all their nasty inductance? Whoddathunk that? :) > >> >(I've been wanting to use a PCB cap ever since a 1974 Scientific > >> >American 'Amateur Scientist' column describing an FR-4 traveling-wave > >> >spark-gap-excited nitrogen laser.) > >> > > >> >(Yeah, I know--sideways caps, lots of them, etc. etc.) > >> > > >> >> 1 ns isn't very fast. > >> > > >> >Slewing a kV in a couple ns may not impress the Lords of Picoseconds as > >> >much of a big deal, but the amps/ns sure makes big impressions on PCB > >> >traces everywhere! > >> > > >> >Grins, > >> >James Arthur > >> > >> 1 amp/ns is 1 volt into 1 nH. You'd never miss that. > > > >I'm pulling about 10A/ns from the cap. Since I need both lots of > >bulk storage *and* a precision voltage step, that means I'm stuck > >with using combinations of caps to get the overall desired effect. > >A 2012 1uF x 2kV cap with 10pH ESL sure would be handy. > > > >> I could tell my drift-step-recovery diode story again. > >> > >> My Pockels Cell driver ain't bad: > >> > >> http://www.highlandtechnology.com/DSS/T850DS.shtml > >> > >> The Pockels cells don't like long-term DC, so the AC coupling option > >> is a couple of caps in parallel. The real problem was toasting the > >> Phoenix terminal block from dielectric losses. The green gunk they use > >> has worse losses than FR4! > > > >Now *that's* a cool story. But then you're always burning things up > >and tormenting innocent electronic parts, aren't you? (You've inspired > >some of that in me, too!) Brute! > > Fireworks are illegal in California. Gotta have fun somehow. > > > > >I've still got to do the overvoltage-the-MOSFET-gate-for-a-ns trick > >some time. But I think GaN has made that project moot. > > I found that adding a small inductor in series with a SiC gate helped > a lot. SiC fets have a lot of internal gate series resistance (some, a > very lot) so a little L makes the internal/actual gate voltage, hidden > behind that resistance, a lot snappier. > > C2M0280120D, 27 nH.
I spent many hours doing similar things, but with Rg=25 ohms there's only so much a boy can do before frying the die. Lower Rg would sure help -- both native speed, and for extreme over-the-top measures. Cheers, James
On Tue, 23 Jun 2020 15:08:06 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

>On Monday, June 22, 2020 at 11:40:10 PM UTC-4, jla...@highlandsniptechnology.com wrote: >> On Mon, 22 Jun 2020 20:04:18 -0700 (PDT), dagmargoodboat@yahoo.com >> wrote: >> >> >On Monday, June 22, 2020 at 8:48:44 PM UTC-4, John Larkin wrote: >> >> On Mon, 22 Jun 2020 15:43:10 -0700 (PDT), dagmargoodboat@yahoo.com >> >> wrote: >> >> >> >> >On Monday, June 22, 2020 at 5:31:59 PM UTC-4, John Larkin wrote: >> >> >> On Mon, 22 Jun 2020 12:43:32 -0700 (PDT), dagmargoodboat@yahoo.com >> >> >> wrote: >> >> >> >> >> >> >On Monday, June 22, 2020 at 3:31:29 PM UTC-4, John Larkin wrote: >> >> >> >> On Mon, 22 Jun 2020 11:54:30 -0700 (PDT), dagmargoodboat@yahoo.com >> >> >> >> wrote: >> >> >> >> >> >> >> >> >On Monday, June 22, 2020 at 1:34:21 PM UTC-4, Jeroen Belleman wrote: >> >> >> >> >> On 2020-06-22 17:51, jlarkin@highlandsniptechnology.com wrote: >> >> >> >> >> >[...] >> >> >> >> >> > I wasn't happy with my PCBWAY board. Resolution and registration were >> >> >> >> >> > bad, and they didn't read my stackup specs. Their default 4-layer >> >> >> >> >> > stack has *four mils* of dielectric between layers 1 and 2, and >> >> >> >> >> > between 3 and 4. That is really nasty. That stack is common in cheap >> >> >> >> >> > chinese proto houses. >> >> >> >> >> >> >> >> >> >> That's nasty indeed. Who'd use a stackup like that? >> >> >> >> >> >> >> >> >> >> Jeroen Belleman >> >> >> >> > >> >> >> >> >I might! Just two days ago I was calculating how much capacitance I >> >> >> >> >could squeeze out of a PCB pour. Consulting my calculator, 0,1mm spacing >> >> >> >> >and 5 x 5cm gets me 97nF with just 100 layers' stackup :) >> >> >> >> > >> >> >> >> >Cheers, >> >> >> >> >James Arthur >> >> >> >> >> >> >> >> Figure a tempco ballpark +900 PPM. And a lot of nasty DA. >> >> >> > >> >> >> >I need amps at kV in <1 ns, that's the appeal. I like the >> >> >> >DA -- DA = damping, which is a plus. But the '100 layers' >> >> >> >part is admittedly, <cough>, a slight inconvenience. >> >> >> > >> >> >> >Grins, >> >> >> >James >> >> >> >> >> >> Wait, wait, I have an idea: use capacitors! >> >> > >> >> >With all their nasty inductance? Whoddathunk that? :) >> >> >(I've been wanting to use a PCB cap ever since a 1974 Scientific >> >> >American 'Amateur Scientist' column describing an FR-4 traveling-wave >> >> >spark-gap-excited nitrogen laser.) >> >> > >> >> >(Yeah, I know--sideways caps, lots of them, etc. etc.) >> >> > >> >> >> 1 ns isn't very fast. >> >> > >> >> >Slewing a kV in a couple ns may not impress the Lords of Picoseconds as >> >> >much of a big deal, but the amps/ns sure makes big impressions on PCB >> >> >traces everywhere! >> >> > >> >> >Grins, >> >> >James Arthur >> >> >> >> 1 amp/ns is 1 volt into 1 nH. You'd never miss that. >> > >> >I'm pulling about 10A/ns from the cap. Since I need both lots of >> >bulk storage *and* a precision voltage step, that means I'm stuck >> >with using combinations of caps to get the overall desired effect. >> >A 2012 1uF x 2kV cap with 10pH ESL sure would be handy. >> > >> >> I could tell my drift-step-recovery diode story again. >> >> >> >> My Pockels Cell driver ain't bad: >> >> >> >> http://www.highlandtechnology.com/DSS/T850DS.shtml >> >> >> >> The Pockels cells don't like long-term DC, so the AC coupling option >> >> is a couple of caps in parallel. The real problem was toasting the >> >> Phoenix terminal block from dielectric losses. The green gunk they use >> >> has worse losses than FR4! >> > >> >Now *that's* a cool story. But then you're always burning things up >> >and tormenting innocent electronic parts, aren't you? (You've inspired >> >some of that in me, too!) Brute! >> >> Fireworks are illegal in California. Gotta have fun somehow. >> >> > >> >I've still got to do the overvoltage-the-MOSFET-gate-for-a-ns trick >> >some time. But I think GaN has made that project moot. >> >> I found that adding a small inductor in series with a SiC gate helped >> a lot. SiC fets have a lot of internal gate series resistance (some, a >> very lot) so a little L makes the internal/actual gate voltage, hidden >> behind that resistance, a lot snappier. >> >> C2M0280120D, 27 nH. > >I spent many hours doing similar things, but with Rg=25 ohms there's >only so much a boy can do before frying the die. > >Lower Rg would sure help -- both native speed, and for extreme over-the-top >measures. > >Cheers, >James
Cree specs the internal gate resistance of my C2M0280120D as 11 ohms, an outrageous figure for fast switching. I've seen other SiC fets that were much higher. Cree's Spice models look reasonable (except for the substrate diode) and the inductive peaking advantage is similar in simulation and in real life. I truly believe that if an RC time constant slows down the edge of the actual gate structure on the chip, and I add an inductor to peak it up, no harm is done. I have destroyed a very modest number of fets to confirm that. 3 pF of Crss sounds pretty small, until you swing 1200 volts in a few ns. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Mon, 22 Jun 2020 17:48:34 -0700, John Larkin
<jlarkin@highland_atwork_technology.com> wrote:

>On Mon, 22 Jun 2020 15:43:10 -0700 (PDT), dagmargoodboat@yahoo.com >wrote: > >>On Monday, June 22, 2020 at 5:31:59 PM UTC-4, John Larkin wrote: >>> On Mon, 22 Jun 2020 12:43:32 -0700 (PDT), dagmargoodboat@yahoo.com >>> wrote: >>> >>> >On Monday, June 22, 2020 at 3:31:29 PM UTC-4, John Larkin wrote: >>> >> On Mon, 22 Jun 2020 11:54:30 -0700 (PDT), dagmargoodboat@yahoo.com >>> >> wrote: >>> >> >>> >> >On Monday, June 22, 2020 at 1:34:21 PM UTC-4, Jeroen Belleman wrote: >>> >> >> On 2020-06-22 17:51, jlarkin@highlandsniptechnology.com wrote: >>> >> >> >[...] >>> >> >> > I wasn't happy with my PCBWAY board. Resolution and registration were >>> >> >> > bad, and they didn't read my stackup specs. Their default 4-layer >>> >> >> > stack has *four mils* of dielectric between layers 1 and 2, and >>> >> >> > between 3 and 4. That is really nasty. That stack is common in cheap >>> >> >> > chinese proto houses. >>> >> >> >>> >> >> That's nasty indeed. Who'd use a stackup like that? >>> >> >> >>> >> >> Jeroen Belleman >>> >> > >>> >> >I might! Just two days ago I was calculating how much capacitance I >>> >> >could squeeze out of a PCB pour. Consulting my calculator, 0,1mm spacing >>> >> >and 5 x 5cm gets me 97nF with just 100 layers' stackup :) >>> >> > >>> >> >Cheers, >>> >> >James Arthur >>> >> >>> >> Figure a tempco ballpark +900 PPM. And a lot of nasty DA. >>> > >>> >I need amps at kV in <1 ns, that's the appeal. I like the >>> >DA -- DA = damping, which is a plus. But the '100 layers' >>> >part is admittedly, <cough>, a slight inconvenience. >>> > >>> >Grins, >>> >James >>> >>> Wait, wait, I have an idea: use capacitors! >> >>With all their nasty inductance? Whoddathunk that? :) >>(I've been wanting to use a PCB cap ever since a 1974 Scientific >>American 'Amateur Scientist' column describing an FR-4 traveling-wave >>spark-gap-excited nitrogen laser.) >> >>(Yeah, I know--sideways caps, lots of them, etc. etc.) >> >>> 1 ns isn't very fast. >> >>Slewing a kV in a couple ns may not impress the Lords of Picoseconds as >>much of a big deal, but the amps/ns sure makes big impressions on PCB >>traces everywhere! >> >>Grins, >>James Arthur > >1 amp/ns is 1 volt into 1 nH. You'd never miss that. > >I could tell my drift-step-recovery diode story again. > >My Pockels Cell driver ain't bad: > >http://www.highlandtechnology.com/DSS/T850DS.shtml > >The Pockels cells don't like long-term DC, so the AC coupling option >is a couple of caps in parallel. The real problem was toasting the >Phoenix terminal block from dielectric losses. The green gunk they use >has worse losses than FR4!
Diallyl phthalate? Joe Gwinn
On Wed, 24 Jun 2020 21:42:30 -0400, Joe Gwinn <joegwinn@comcast.net>
wrote:

>On Mon, 22 Jun 2020 17:48:34 -0700, John Larkin ><jlarkin@highland_atwork_technology.com> wrote: > >>On Mon, 22 Jun 2020 15:43:10 -0700 (PDT), dagmargoodboat@yahoo.com >>wrote: >> >>>On Monday, June 22, 2020 at 5:31:59 PM UTC-4, John Larkin wrote: >>>> On Mon, 22 Jun 2020 12:43:32 -0700 (PDT), dagmargoodboat@yahoo.com >>>> wrote: >>>> >>>> >On Monday, June 22, 2020 at 3:31:29 PM UTC-4, John Larkin wrote: >>>> >> On Mon, 22 Jun 2020 11:54:30 -0700 (PDT), dagmargoodboat@yahoo.com >>>> >> wrote: >>>> >> >>>> >> >On Monday, June 22, 2020 at 1:34:21 PM UTC-4, Jeroen Belleman wrote: >>>> >> >> On 2020-06-22 17:51, jlarkin@highlandsniptechnology.com wrote: >>>> >> >> >[...] >>>> >> >> > I wasn't happy with my PCBWAY board. Resolution and registration were >>>> >> >> > bad, and they didn't read my stackup specs. Their default 4-layer >>>> >> >> > stack has *four mils* of dielectric between layers 1 and 2, and >>>> >> >> > between 3 and 4. That is really nasty. That stack is common in cheap >>>> >> >> > chinese proto houses. >>>> >> >> >>>> >> >> That's nasty indeed. Who'd use a stackup like that? >>>> >> >> >>>> >> >> Jeroen Belleman >>>> >> > >>>> >> >I might! Just two days ago I was calculating how much capacitance I >>>> >> >could squeeze out of a PCB pour. Consulting my calculator, 0,1mm spacing >>>> >> >and 5 x 5cm gets me 97nF with just 100 layers' stackup :) >>>> >> > >>>> >> >Cheers, >>>> >> >James Arthur >>>> >> >>>> >> Figure a tempco ballpark +900 PPM. And a lot of nasty DA. >>>> > >>>> >I need amps at kV in <1 ns, that's the appeal. I like the >>>> >DA -- DA = damping, which is a plus. But the '100 layers' >>>> >part is admittedly, <cough>, a slight inconvenience. >>>> > >>>> >Grins, >>>> >James >>>> >>>> Wait, wait, I have an idea: use capacitors! >>> >>>With all their nasty inductance? Whoddathunk that? :) >>>(I've been wanting to use a PCB cap ever since a 1974 Scientific >>>American 'Amateur Scientist' column describing an FR-4 traveling-wave >>>spark-gap-excited nitrogen laser.) >>> >>>(Yeah, I know--sideways caps, lots of them, etc. etc.) >>> >>>> 1 ns isn't very fast. >>> >>>Slewing a kV in a couple ns may not impress the Lords of Picoseconds as >>>much of a big deal, but the amps/ns sure makes big impressions on PCB >>>traces everywhere! >>> >>>Grins, >>>James Arthur >> >>1 amp/ns is 1 volt into 1 nH. You'd never miss that. >> >>I could tell my drift-step-recovery diode story again. >> >>My Pockels Cell driver ain't bad: >> >>http://www.highlandtechnology.com/DSS/T850DS.shtml >> >>The Pockels cells don't like long-term DC, so the AC coupling option >>is a couple of caps in parallel. The real problem was toasting the >>Phoenix terminal block from dielectric losses. The green gunk they use >>has worse losses than FR4! > >Diallyl phthalate? > >Joe Gwinn
Looks like it. Lossy! -- John Larkin Highland Technology, Inc Science teaches us to doubt. Claude Bernard
On Sunday, June 21, 2020 at 9:58:56 PM UTC-4, dagmarg...@yahoo.com wrote:
> > I don't have a microscope & haven't needed one. I just did it > caveman-style. (Are we still allowed to say 'caveman'?)
I don't think so: <https://en.wikipedia.org/wiki/GEICO_Cavemen> <https://en.wikipedia.org/wiki/Cavemen_(TV_series)>
On Monday, June 22, 2020 at 5:51:14 PM UTC+2, jla...@highlandsniptechnology.com wrote:
> On Mon, 22 Jun 2020 10:12:30 +0200, Gerhard Hoffmann <dk4xp@arcor.de> > wrote: > > >Am 22.06.20 um 01:32 schrieb dagmargoodboat@yahoo.com: > >> As I design yet another little switcher, I notice it's getting > >> more and more tempting to swap ye olde MOS FET for a shiny > >> new GaN-speck. > >> > >> Electrically superior in almost every respect, the GaN FETs' > >> drawbacks are thermal (not a problem in this case), and their > >> tee-nine-sie .9x.9mm bare-chip packages. > >> > >> e.g. > >> T.I. CSD19831Q3: 100V, Rds(on)=50mohm, Cin=350pF, Coss=70pF, Crss=13pF > >> EPC EPC2036: 100V, Rds(on)~=60mohm, Cin=43pF, Coss=25pF, Crss<1pF > >> > >> I re-worked a chip-scale part with hot air and a hot plate by hand. > >> Took me a zillion tries to get it done--that was a nuisance. > > > > > >I was more lucky. My first 2 tries worked immediately with just a > >little bit of hot air. Very little, or they fly away. > >That was a test structure from a corner of a larger board made > >by PCBWAY. HAL, I removed the excess tin with some unsolder braid > >and used paste then. > >PCBWAY spotted the mask on the pad as designed by EPC's Altium example. > >Worked after declaring it OK. > > > > > >< > >https://www.flickr.com/photos/137684711@N07/50032925082/in/dateposted-public/ > > > > >between the 4 1210 caps and the 2 fat vias. > > > > > >cheers, Gerhard > > I wasn't happy with my PCBWAY board. Resolution and registration were > bad, and they didn't read my stackup specs. Their default 4-layer > stack has *four mils* of dielectric between layers 1 and 2, and > between 3 and 4. That is really nasty. That stack is common in cheap > chinese proto houses. > > https://www.dropbox.com/s/p3vpbaofzqurebz/Z462_PCB_Way_2.png?raw=1 > > https://www.dropbox.com/s/v6isv7k1t3fre0w/PCBWAY_Mask.jpg?raw=1 > > That would be OK for slow, not very demanding stuff. >
Our max frequencies are normally 2-300 MHz from fast edges in inverter drives, so from that point, that is really not so bad, I guess, if we were to use such a stackup We also do some BLE, that gets trickier Cheers Klaus
I've got the fabricated board on Friday. :-(
Fabricated here in .de. 10 minutes of drive between my
customer and the board house.

All I wanted was 0.635mm of Rogers TMM6 between Layer1 and 2
because on layer 1 there live the coplanar waveguides.

Rest of the stack was don't care: 2, 3 are gnd, 4 is just
the lowpass of the synthesizer PLL. The rest could be FR4
of because TMM6 is mechanically stable like candle wax.

They succeeded to put the Rogers layer between layer 3 & 4
which carries just some AF.

AAARGHHHH!


I have cracked the first sample of the 10 GHz puck oscillator
board which is only 0.65mm TMM6 when I fastened the first SMA
connector. OK, my fault. TMM6 is like wax.

I have TDRed the longish coplanar WG output line of the 2nd sample.
No difference to the internal 50 Ohm line of the Agilent
54754A. ADS line calc seems to work as promised.
Just the SMA laucher needs a smaller footprint and less tin.
Dips down to 40 Ohms over some mm.

Gerhard



Am 22.06.20 um 20:26 schrieb Gerhard Hoffmann:
> Am 22.06.20 um 19:34 schrieb Jeroen Belleman: >> On 2020-06-22 17:51, jlarkin@highlandsniptechnology.com wrote: >>> [...] >>> I wasn't happy with my PCBWAY board. Resolution and registration were >>> bad, and they didn't read my stackup specs. Their default 4-layer >>> stack has *four mils* of dielectric between layers 1 and 2, and >>> between 3 and 4. That is really nasty. That stack is common in cheap >>> chinese proto houses. >> >> That's nasty indeed. Who'd use a stackup like that? >> >> Jeroen Belleman > > Someone who wants narrow microstrips on the top level? > > In fact, I'm just asking a local board maker for sth. similar, > with the middle of the stack made from thick FR4 for stability > and on the outside thin Rogers 4003 or whatever for thin micro- > strips and low radiation loss at 10 GHz. > > It looks like the eval board of the ADF5356 has a similar stack, > just from visually inspecting the milled sides. > > Up to now I had no single problem with PCBWAY other than that they > use DHL express which leads to some fee f*cking here in .de and > constant trouble with the customs in Leipzig. > I did not let them make multilayers up to now. > > I made a test run with JLCPCB, they have now a proxy man here > in .de. That adds theoretically 2 days or so, but the proxy > handles the customs which may result in an speedup over all. > The proxy gets a pack with the daily production for the EU and > relays it per local mail with a new tracking number. > > It is now technically an inland buy, they collect the local VAT > in advance. Works nicely. > > Gerhard > >
On Mon, 10 Aug 2020 00:28:49 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:

>I've got the fabricated board on Friday. :-( >Fabricated here in .de. 10 minutes of drive between my >customer and the board house. > >All I wanted was 0.635mm of Rogers TMM6 between Layer1 and 2 >because on layer 1 there live the coplanar waveguides. > >Rest of the stack was don't care: 2, 3 are gnd, 4 is just >the lowpass of the synthesizer PLL. The rest could be FR4 >of because TMM6 is mechanically stable like candle wax. > >They succeeded to put the Rogers layer between layer 3 & 4 >which carries just some AF. > >AAARGHHHH! > > >I have cracked the first sample of the 10 GHz puck oscillator >board which is only 0.65mm TMM6 when I fastened the first SMA >connector. OK, my fault. TMM6 is like wax. > >I have TDRed the longish coplanar WG output line of the 2nd sample. >No difference to the internal 50 Ohm line of the Agilent >54754A. ADS line calc seems to work as promised. >Just the SMA laucher needs a smaller footprint and less tin. >Dips down to 40 Ohms over some mm. > >Gerhard > > > >Am 22.06.20 um 20:26 schrieb Gerhard Hoffmann: >> Am 22.06.20 um 19:34 schrieb Jeroen Belleman: >>> On 2020-06-22 17:51, jlarkin@highlandsniptechnology.com wrote: >>>> [...] >>>> I wasn't happy with my PCBWAY board. Resolution and registration were >>>> bad, and they didn't read my stackup specs. Their default 4-layer >>>> stack has *four mils* of dielectric between layers 1 and 2, and >>>> between 3 and 4. That is really nasty. That stack is common in cheap >>>> chinese proto houses. >>> >>> That's nasty indeed. Who'd use a stackup like that? >>> >>> Jeroen Belleman >> >> Someone who wants narrow microstrips on the top level? >> >> In fact, I'm just asking a local board maker for sth. similar, >> with the middle of the stack made from thick FR4 for stability >> and on the outside thin Rogers 4003 or whatever for thin micro- >> strips and low radiation loss at 10 GHz. >> >> It looks like the eval board of the ADF5356 has a similar stack, >> just from visually inspecting the milled sides. >> >> Up to now I had no single problem with PCBWAY other than that they >> use DHL express which leads to some fee f*cking here in .de and >> constant trouble with the customs in Leipzig. >> I did not let them make multilayers up to now. >> >> I made a test run with JLCPCB, they have now a proxy man here >> in .de. That adds theoretically 2 days or so, but the proxy >> handles the customs which may result in an speedup over all. >> The proxy gets a pack with the daily production for the EU and >> relays it per local mail with a new tracking number. >> >> It is now technically an inland buy, they collect the local VAT >> in advance. Works nicely. >> >> Gerhard >> >>
I made some boards with microwave lam in just the top layer. They came curled up like potato chips. https://www.dropbox.com/s/yibz36f0ex7z1sp/MOV02429.MPG?dl=0