On Tue, 23 Jun 2020 15:08:06 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:
>On Monday, June 22, 2020 at 11:40:10 PM UTC-4, jla...@highlandsniptechnology.com wrote:
>> On Mon, 22 Jun 2020 20:04:18 -0700 (PDT), dagmargoodboat@yahoo.com
>> wrote:
>>
>> >On Monday, June 22, 2020 at 8:48:44 PM UTC-4, John Larkin wrote:
>> >> On Mon, 22 Jun 2020 15:43:10 -0700 (PDT), dagmargoodboat@yahoo.com
>> >> wrote:
>> >>
>> >> >On Monday, June 22, 2020 at 5:31:59 PM UTC-4, John Larkin wrote:
>> >> >> On Mon, 22 Jun 2020 12:43:32 -0700 (PDT), dagmargoodboat@yahoo.com
>> >> >> wrote:
>> >> >>
>> >> >> >On Monday, June 22, 2020 at 3:31:29 PM UTC-4, John Larkin wrote:
>> >> >> >> On Mon, 22 Jun 2020 11:54:30 -0700 (PDT), dagmargoodboat@yahoo.com
>> >> >> >> wrote:
>> >> >> >>
>> >> >> >> >On Monday, June 22, 2020 at 1:34:21 PM UTC-4, Jeroen Belleman wrote:
>> >> >> >> >> On 2020-06-22 17:51, jlarkin@highlandsniptechnology.com wrote:
>> >> >> >> >> >[...]
>> >> >> >> >> > I wasn't happy with my PCBWAY board. Resolution and registration were
>> >> >> >> >> > bad, and they didn't read my stackup specs. Their default 4-layer
>> >> >> >> >> > stack has *four mils* of dielectric between layers 1 and 2, and
>> >> >> >> >> > between 3 and 4. That is really nasty. That stack is common in cheap
>> >> >> >> >> > chinese proto houses.
>> >> >> >> >>
>> >> >> >> >> That's nasty indeed. Who'd use a stackup like that?
>> >> >> >> >>
>> >> >> >> >> Jeroen Belleman
>> >> >> >> >
>> >> >> >> >I might! Just two days ago I was calculating how much capacitance I
>> >> >> >> >could squeeze out of a PCB pour. Consulting my calculator, 0,1mm spacing
>> >> >> >> >and 5 x 5cm gets me 97nF with just 100 layers' stackup :)
>> >> >> >> >
>> >> >> >> >Cheers,
>> >> >> >> >James Arthur
>> >> >> >>
>> >> >> >> Figure a tempco ballpark +900 PPM. And a lot of nasty DA.
>> >> >> >
>> >> >> >I need amps at kV in <1 ns, that's the appeal. I like the
>> >> >> >DA -- DA = damping, which is a plus. But the '100 layers'
>> >> >> >part is admittedly, <cough>, a slight inconvenience.
>> >> >> >
>> >> >> >Grins,
>> >> >> >James
>> >> >>
>> >> >> Wait, wait, I have an idea: use capacitors!
>> >> >
>> >> >With all their nasty inductance? Whoddathunk that? :)
>> >> >(I've been wanting to use a PCB cap ever since a 1974 Scientific
>> >> >American 'Amateur Scientist' column describing an FR-4 traveling-wave
>> >> >spark-gap-excited nitrogen laser.)
>> >> >
>> >> >(Yeah, I know--sideways caps, lots of them, etc. etc.)
>> >> >
>> >> >> 1 ns isn't very fast.
>> >> >
>> >> >Slewing a kV in a couple ns may not impress the Lords of Picoseconds as
>> >> >much of a big deal, but the amps/ns sure makes big impressions on PCB
>> >> >traces everywhere!
>> >> >
>> >> >Grins,
>> >> >James Arthur
>> >>
>> >> 1 amp/ns is 1 volt into 1 nH. You'd never miss that.
>> >
>> >I'm pulling about 10A/ns from the cap. Since I need both lots of
>> >bulk storage *and* a precision voltage step, that means I'm stuck
>> >with using combinations of caps to get the overall desired effect.
>> >A 2012 1uF x 2kV cap with 10pH ESL sure would be handy.
>> >
>> >> I could tell my drift-step-recovery diode story again.
>> >>
>> >> My Pockels Cell driver ain't bad:
>> >>
>> >> http://www.highlandtechnology.com/DSS/T850DS.shtml
>> >>
>> >> The Pockels cells don't like long-term DC, so the AC coupling option
>> >> is a couple of caps in parallel. The real problem was toasting the
>> >> Phoenix terminal block from dielectric losses. The green gunk they use
>> >> has worse losses than FR4!
>> >
>> >Now *that's* a cool story. But then you're always burning things up
>> >and tormenting innocent electronic parts, aren't you? (You've inspired
>> >some of that in me, too!) Brute!
>>
>> Fireworks are illegal in California. Gotta have fun somehow.
>>
>> >
>> >I've still got to do the overvoltage-the-MOSFET-gate-for-a-ns trick
>> >some time. But I think GaN has made that project moot.
>>
>> I found that adding a small inductor in series with a SiC gate helped
>> a lot. SiC fets have a lot of internal gate series resistance (some, a
>> very lot) so a little L makes the internal/actual gate voltage, hidden
>> behind that resistance, a lot snappier.
>>
>> C2M0280120D, 27 nH.
>
>I spent many hours doing similar things, but with Rg=25 ohms there's
>only so much a boy can do before frying the die.
>
>Lower Rg would sure help -- both native speed, and for extreme over-the-top
>measures.
>
>Cheers,
>James
Cree specs the internal gate resistance of my C2M0280120D as 11 ohms,
an outrageous figure for fast switching. I've seen other SiC fets that
were much higher.
Cree's Spice models look reasonable (except for the substrate diode)
and the inductive peaking advantage is similar in simulation and in
real life.
I truly believe that if an RC time constant slows down the edge of the
actual gate structure on the chip, and I add an inductor to peak it
up, no harm is done. I have destroyed a very modest number of fets to
confirm that.
3 pF of Crss sounds pretty small, until you swing 1200 volts in a few
ns.
--
John Larkin Highland Technology, Inc
picosecond timing precision measurement
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com