On Fri, 16 Dec 2022 09:13:02 -0800 (PST), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>fredag den 16. december 2022 kl. 17.02.10 UTC+1 skrev legg: >> On Thu, 15 Dec 2022 08:10:10 -0800 (PST), Lasse Langwadt Christensen >> <lang...@fonz.dk> wrote: >> >torsdag den 15. december 2022 kl. 16.35.42 UTC+1 skrev John Larkin: >> >> On Thu, 15 Dec 2022 15:01:53 +0100, Klaus Vestergaard Kragelund >> >> <klau...@hotmail.com> wrote: >> >> >> >> >On 15-12-2022 05:47, John Miles, KE5FX wrote: >> >> >> On Wednesday, December 14, 2022 at 7:14:33 PM UTC-8, John Larkin wrote: >> >> >>> I'm guessing that the first bridge turn-on pushes hundreds of amps >> >> >>> into the ground plane and makes potentials everywhere. If we make a >> >> >>> square wave into the bridge drive and ramp up the +48 from a bench >> >> >>> supply, it's all nice. >> >> >> >> >> >> But the parts you're using have a frequency response that's not infinite. >> >> >> You can turn them on as slowly as you want by scheduling both the >> >> >> duty cycle and frequency of the pulses. >> >> >> >> >> >> Pulse pairs spaced 5 ns apart aren't going to make it draw hundreds of >> >> >> amps, right? They will never make it through the gate drivers. How about >> >> >> 100 ns apart? Maybe it draws 10 mA now. 1000 ns on, then off? Maybe >> >> >> now it's 500 mA. Etc. >> >> >> >> >> > >> >> >It is possible to do soft start on a bridge configuration like this. >> >> >Like you mention, you need to be able to generate very close matching >> >> >duty cycles to start with ns ON cycles. >> >> > >> >> >Normally you would have an output inductor, since otherwise only leakage >> >> >inductances limits the currents >> >> > >> >> I seems that the gate drivers won't pass very narrow pulses, and we'd >> >> have to tease the fet gate thresholds in some analog manner. We tried >> >> FPGA things that didn't work. >> > >> >so don't use narrow pulses, run both half bridges at 50/50 duty cycle and delay one of them 0-180 degrees >> > >> You're supposed to be able to do anything with the >> FPGA (?) driver. Isn't that the whole idea behind >> direct digital control? > >sure, the 50/50 and phaseshift just gets around the problem of the gate drivers >swallowing short pulses, but it seems the board isn't wired to be able to do thatI don't think there is any way to use digital control to avoid gigantic peak currents at startup. And certainly not worth launching a project to try.
soft-start blunder
Started by ●December 14, 2022
Reply by ●December 16, 20222022-12-16
Reply by ●December 16, 20222022-12-16
torsdag den 15. december 2022 kl. 17.40.46 UTC+1 skrev John Larkin:> On Thu, 15 Dec 2022 08:10:10 -0800 (PST), Lasse Langwadt Christensen > <lang...@fonz.dk> wrote: > > >torsdag den 15. december 2022 kl. 16.35.42 UTC+1 skrev John Larkin: > >> On Thu, 15 Dec 2022 15:01:53 +0100, Klaus Vestergaard Kragelund > >> <klau...@hotmail.com> wrote: > >> > >> >On 15-12-2022 05:47, John Miles, KE5FX wrote: > >> >> On Wednesday, December 14, 2022 at 7:14:33 PM UTC-8, John Larkin wrote: > >> >>> I'm guessing that the first bridge turn-on pushes hundreds of amps > >> >>> into the ground plane and makes potentials everywhere. If we make a > >> >>> square wave into the bridge drive and ramp up the +48 from a bench > >> >>> supply, it's all nice. > >> >> > >> >> But the parts you're using have a frequency response that's not infinite. > >> >> You can turn them on as slowly as you want by scheduling both the > >> >> duty cycle and frequency of the pulses. > >> >> > >> >> Pulse pairs spaced 5 ns apart aren't going to make it draw hundreds of > >> >> amps, right? They will never make it through the gate drivers. How about > >> >> 100 ns apart? Maybe it draws 10 mA now. 1000 ns on, then off? Maybe > >> >> now it's 500 mA. Etc. > >> >> > >> > > >> >It is possible to do soft start on a bridge configuration like this. > >> >Like you mention, you need to be able to generate very close matching > >> >duty cycles to start with ns ON cycles. > >> > > >> >Normally you would have an output inductor, since otherwise only leakage > >> >inductances limits the currents > >> > > >> I seems that the gate drivers won't pass very narrow pulses, and we'd > >> have to tease the fet gate thresholds in some analog manner. We tried > >> FPGA things that didn't work. > > > >so don't use narrow pulses, run both half bridges at 50/50 duty cycle and delay one of them 0-180 degrees > > > That is morally equivalent to starting with narrow pulses.but avoids the issue if the gatedrivers swalloving short pules> The way the drivers are wired, we can't do that anyhow.it think if you disconnect the BINPs on both drivers and a hardwire them high, you could
Reply by ●December 17, 20222022-12-17
On a sunny day (Fri, 16 Dec 2022 07:54:44 -0800) it happened John Larkin <jlarkin@highlandSNIPMEtechnology.com> wrote in <kk4pphl0722gaetibmk8t55tirpa57upqu@4ax.com>:>On Fri, 16 Dec 2022 06:08:23 GMT, Jan Panteltje ><pNaonStpealmtje@yahoo.com> wrote: > >>On a sunny day (Wed, 14 Dec 2022 22:45:39 -0800) it happened John Larkin >><jlarkin@highlandSNIPMEtechnology.com> wrote in >><t8glph139gjr602hqd7oc43691q0gi9r2d@4ax.com>: >> >>>On Thu, 15 Dec 2022 05:45:45 GMT, Jan Panteltje >>><pNaonStpealmtje@yahoo.com> wrote: >>> >>>>On a sunny day (Wed, 14 Dec 2022 09:01:50 -0800) it happened John Larkin >>>><jlarkin@highlandSNIPMEtechnology.com> wrote in >>>><cmvjphpgkb4sf3s7to9c8di0ph70um8f6q@4ax.com>: >>>> >>>>> >>>>>This is a 200 watt isolating dc/dc converter: >>>>> >>>>>https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 >>>>> >>>>>Some idiot who shall not be named figured that we could start it up by >>>>>ramping up the drive pulse widths from the FPGA, starting very small >>>>>and eventually making square waves. But even small pulses pull >>>>>hundreds of amps and have side effects like deconfiguring the FPGA. >>>>> >>>>>The fix is to hack in a small board to ramp up the +48 supply, and >>>>>leave the drive a square wave. >>>>> >>>>>https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 >>>>> >>>>>https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0 >>>> >>>>Cannot read ASCII but small series inductor shorted after power-up before secondary >>>>rectifier capacitor? >>>>Only takes one power MOSFET? >>> >>> >>>Here's an improved version. >>> >>>https://www.dropbox.com/s/yv8wvzxya26bm5o/Z544_SoftStart_3.jpg?raw=1 >>> >>> >>>The FPGA will start up the 250 KHz square wave into the h-bridge >>>drivers, and then enable the 48 volt linear ramp. That should start up >>>nice and smooth. >>> >>>My weekend assignment is to lay out the kluge board. >>> >> >>This was what I thought of: >> http://panteltje.com/pub/startup__impuse_reducer_IXIMG_0906.JPG >>as the output voltage increases the inductor is shorted by the power MOSFET. >>Sorry for bad drawing here in zero graffiti >>Doing things low power is easier of course. > >I don't think the inductor would be a practical size.Resistor?>Here's my soft-start board. > >https://www.dropbox.com/s/hoicw55p91d9muc/99S544A1.pdf?dl=0Says item was deleted>https://www.dropbox.com/s/rllue2bl0dl0ve5/Z544_SoftStart_A1.jpg?raw=1OK>It bolts onto the power supply board where the fuseholder used to be. >It replicates the fuse and adds the soft start, under FPGA control. > >I like to lay out a small board now and then.Most things I do these days are hobby related on veroboard stuff... Even giggle Hertz stuff..
Reply by ●December 17, 20222022-12-17
On Fri, 16 Dec 2022 08:39:35 -0800, John Larkin <jlarkin@highlandSNIPMEtechnology.com> wrote:>On Fri, 16 Dec 2022 10:59:20 -0500, legg <legg@nospam.magma.ca> wrote: > >>On Wed, 14 Dec 2022 09:01:50 -0800, John Larkin >><jlarkin@highlandSNIPMEtechnology.com> wrote: >> >>> >>>This is a 200 watt isolating dc/dc converter: >>> >>>https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 >>> >>>Some idiot who shall not be named figured that we could start it up by >>>ramping up the drive pulse widths from the FPGA, starting very small >>>and eventually making square waves. But even small pulses pull >>>hundreds of amps and have side effects like deconfiguring the FPGA. >>> >>>The fix is to hack in a small board to ramp up the +48 supply, and >>>leave the drive a square wave. >>> >>>https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 >>> >>>https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0 >>> >> >>Linear slow-start can be lossy. Your simulation doesn't show the >>dc-dc downstream load, so only mA are being supplied. > >Downstream of each dc/dc converter is a half-bridge PWM-programmable >DC power supply. But it's off during startup. The startup energy >dissipation is tiny, and the soft-start fet is under 20 mohms when >things are operating. > >> >>The DC-DC has to be running during slow-start, to be effective. > >Yes. We will turn on the square wave drive and start the DC voltage >ramp simultaneously. The power supply to the inverter will ramp >linearly from 0 to 48 in about 200 ms. > > >> >>You need to calculate the joules, depending on total reflected DC >>load current plus rail capacitance dv/dt. > >Did that of course. The only startup load is the isolated side caps. > >> >>RLYou'll need a ball park capacitive load anyhoo. I=C dv/dt. Different dv/dts set the fet current, or vice-versa, depending on what's being controlled during the inrush limit event. All I noticed in the sim was ~20mA of fet current. er . . .don't swot the fet gate at turn-off. RL
Reply by ●December 17, 20222022-12-17
On Fri, 16 Dec 2022 08:39:35 -0800, John Larkin <jlarkin@highlandSNIPMEtechnology.com> wrote:>On Fri, 16 Dec 2022 10:59:20 -0500, legg <legg@nospam.magma.ca> wrote: > >>On Wed, 14 Dec 2022 09:01:50 -0800, John Larkin >><jlarkin@highlandSNIPMEtechnology.com> wrote: >> >>> >>>This is a 200 watt isolating dc/dc converter: >>> >>>https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 >>> >>>Some idiot who shall not be named figured that we could start it up by >>>ramping up the drive pulse widths from the FPGA, starting very small >>>and eventually making square waves. But even small pulses pull >>>hundreds of amps and have side effects like deconfiguring the FPGA. >>> >>>The fix is to hack in a small board to ramp up the +48 supply, and >>>leave the drive a square wave. >>> >>>https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 >>> >>>https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0 >>> >> >>Linear slow-start can be lossy. Your simulation doesn't show the >>dc-dc downstream load, so only mA are being supplied. > >Downstream of each dc/dc converter is a half-bridge PWM-programmable >DC power supply. But it's off during startup. The startup energy >dissipation is tiny, and the soft-start fet is under 20 mohms when >things are operating. > >> >>The DC-DC has to be running during slow-start, to be effective. > >Yes. We will turn on the square wave drive and start the DC voltage >ramp simultaneously. The power supply to the inverter will ramp >linearly from 0 to 48 in about 200 ms. > > >> >>You need to calculate the joules, depending on total reflected DC >>load current plus rail capacitance dv/dt. > >Did that of course. The only startup load is the isolated side caps. > >> >>RLLove the 48V+ gate enhancement. I want one of those two terminal current generators. RL
Reply by ●December 17, 20222022-12-17
On Sat, 17 Dec 2022 05:46:35 GMT, Jan Panteltje <pNaonStpealmtje@yahoo.com> wrote:>On a sunny day (Fri, 16 Dec 2022 07:54:44 -0800) it happened John Larkin ><jlarkin@highlandSNIPMEtechnology.com> wrote in ><kk4pphl0722gaetibmk8t55tirpa57upqu@4ax.com>: > >>On Fri, 16 Dec 2022 06:08:23 GMT, Jan Panteltje >><pNaonStpealmtje@yahoo.com> wrote: >> >>>On a sunny day (Wed, 14 Dec 2022 22:45:39 -0800) it happened John Larkin >>><jlarkin@highlandSNIPMEtechnology.com> wrote in >>><t8glph139gjr602hqd7oc43691q0gi9r2d@4ax.com>: >>> >>>>On Thu, 15 Dec 2022 05:45:45 GMT, Jan Panteltje >>>><pNaonStpealmtje@yahoo.com> wrote: >>>> >>>>>On a sunny day (Wed, 14 Dec 2022 09:01:50 -0800) it happened John Larkin >>>>><jlarkin@highlandSNIPMEtechnology.com> wrote in >>>>><cmvjphpgkb4sf3s7to9c8di0ph70um8f6q@4ax.com>: >>>>> >>>>>> >>>>>>This is a 200 watt isolating dc/dc converter: >>>>>> >>>>>>https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 >>>>>> >>>>>>Some idiot who shall not be named figured that we could start it up by >>>>>>ramping up the drive pulse widths from the FPGA, starting very small >>>>>>and eventually making square waves. But even small pulses pull >>>>>>hundreds of amps and have side effects like deconfiguring the FPGA. >>>>>> >>>>>>The fix is to hack in a small board to ramp up the +48 supply, and >>>>>>leave the drive a square wave. >>>>>> >>>>>>https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 >>>>>> >>>>>>https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0 >>>>> >>>>>Cannot read ASCII but small series inductor shorted after power-up before secondary >>>>>rectifier capacitor? >>>>>Only takes one power MOSFET? >>>> >>>> >>>>Here's an improved version. >>>> >>>>https://www.dropbox.com/s/yv8wvzxya26bm5o/Z544_SoftStart_3.jpg?raw=1 >>>> >>>> >>>>The FPGA will start up the 250 KHz square wave into the h-bridge >>>>drivers, and then enable the 48 volt linear ramp. That should start up >>>>nice and smooth. >>>> >>>>My weekend assignment is to lay out the kluge board. >>>> >>> >>>This was what I thought of: >>> http://panteltje.com/pub/startup__impuse_reducer_IXIMG_0906.JPG >>>as the output voltage increases the inductor is shorted by the power MOSFET. >>>Sorry for bad drawing here in zero graffiti >>>Doing things low power is easier of course. >> >>I don't think the inductor would be a practical size. > >Resistor? > > >>Here's my soft-start board. >> >>https://www.dropbox.com/s/hoicw55p91d9muc/99S544A1.pdf?dl=0 >Says item was deletedTry this: https://www.dropbox.com/sh/96adbwr9utgwom0/AACHgFwNj9MKWIxDHAZi-KYNa?dl=0 Another recent discovery is that we need schottky diodes in parallel with the mosfet substate diodes in the h-bridges. Weird things were happening during the anti-shoot-through times of the LTC4444 driver chips. I've seen mosfet substrate diodes decide to act like high-power step-recovery diodes.> >>It bolts onto the power supply board where the fuseholder used to be. >>It replicates the fuse and adds the soft start, under FPGA control. >> >>I like to lay out a small board now and then. > >Most things I do these days are hobby related on veroboard stuff... >Even giggle Hertz stuff..Dremel! https://www.dropbox.com/s/pa9mu4ehtrjei8m/Z384_1.JPG?raw=1 Has anyone tried the Digikey pc boards? https://www.digikey.com/en/resources/dkred
Reply by ●December 17, 20222022-12-17
On Sat, 17 Dec 2022 09:03:31 -0500, legg <legg@nospam.magma.ca> wrote:>On Fri, 16 Dec 2022 08:39:35 -0800, John Larkin ><jlarkin@highlandSNIPMEtechnology.com> wrote: > >>On Fri, 16 Dec 2022 10:59:20 -0500, legg <legg@nospam.magma.ca> wrote: >> >>>On Wed, 14 Dec 2022 09:01:50 -0800, John Larkin >>><jlarkin@highlandSNIPMEtechnology.com> wrote: >>> >>>> >>>>This is a 200 watt isolating dc/dc converter: >>>> >>>>https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 >>>> >>>>Some idiot who shall not be named figured that we could start it up by >>>>ramping up the drive pulse widths from the FPGA, starting very small >>>>and eventually making square waves. But even small pulses pull >>>>hundreds of amps and have side effects like deconfiguring the FPGA. >>>> >>>>The fix is to hack in a small board to ramp up the +48 supply, and >>>>leave the drive a square wave. >>>> >>>>https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 >>>> >>>>https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0 >>>> >>> >>>Linear slow-start can be lossy. Your simulation doesn't show the >>>dc-dc downstream load, so only mA are being supplied. >> >>Downstream of each dc/dc converter is a half-bridge PWM-programmable >>DC power supply. But it's off during startup. The startup energy >>dissipation is tiny, and the soft-start fet is under 20 mohms when >>things are operating. >> >>> >>>The DC-DC has to be running during slow-start, to be effective. >> >>Yes. We will turn on the square wave drive and start the DC voltage >>ramp simultaneously. The power supply to the inverter will ramp >>linearly from 0 to 48 in about 200 ms. >> >> >>> >>>You need to calculate the joules, depending on total reflected DC >>>load current plus rail capacitance dv/dt. >> >>Did that of course. The only startup load is the isolated side caps. >> >>> >>>RL > >Love the 48V+ gate enhancement. > >I want one of those two terminal current generators. > >RLIt's a TLP191 pv optocoupler, essentially a floating 7 volt 25 uA power supply.
Reply by ●December 18, 20222022-12-18
On a sunny day (Sat, 17 Dec 2022 09:32:51 -0800) it happened John Larkin <jlarkin@highlandSNIPMEtechnology.com> wrote in <nitrph9i9g3ervse2edkt6321bfth4lmn5@4ax.com>:>On Sat, 17 Dec 2022 05:46:35 GMT, Jan Panteltje ><pNaonStpealmtje@yahoo.com> wrote: >>>I don't think the inductor would be a practical size. >> >>Resistor? >> >> >>>Here's my soft-start board. >>> >>>https://www.dropbox.com/s/hoicw55p91d9muc/99S544A1.pdf?dl=0 >>Says item was deleted > > >Try this: > >https://www.dropbox.com/sh/96adbwr9utgwom0/AACHgFwNj9MKWIxDHAZi-KYNa?dl=0OK, that will work, short dissipation in the MOSFET during the ramp. When switching in a resistro during filter capacitor charge would work too. I understood from your posting that at startup there is no other load?> >Another recent discovery is that we need schottky diodes in parallel >with the mosfet substate diodes in the h-bridges. Weird things were >happening during the anti-shoot-through times of the LTC4444 driver >chips. I've seen mosfet substrate diodes decide to act like high-power >step-recovery diodes. > >> >>>It bolts onto the power supply board where the fuseholder used to be. >>>It replicates the fuse and adds the soft start, under FPGA control. >>> >>>I like to lay out a small board now and then. >> >>Most things I do these days are hobby related on veroboard stuff... >>Even giggle Hertz stuff.. > >Dremel! > >https://www.dropbox.com/s/pa9mu4ehtrjei8m/Z384_1.JPG?raw=1Yes, nice, and gold! http://panteltje.com/panteltje/raspberry_pi_dvb-s_transmitter/ scroll down for board, the GHz stuff is bottom right, In those boards the SMDs fit exactly between 2 isles, many here, and you can make your 'waveguides' in 3 D... http://panteltje.com/pub/2.4GHz_SWR_reflected_with_directional_coupler_IMG_5102.JPG http://panteltje.com/pub/2.4_GHz_to_1.5_GHz_down_converter_closeup_IMG_4660.JPG http://panteltje.com/pub/added_2.4_GHz_VCO_IMG_4620.JPG http://panteltje.com/pub/2.4_GHz_VCO_via_coax_IMG_4624.JPG http://panteltje.com/pub/GPS_jammer_board_twisted_wire_1.57GHz_oscillator_IMG_3622.GIF>Has anyone tried the Digikey pc boards? > >https://www.digikey.com/en/resources/dkredInteresting
Reply by ●December 18, 20222022-12-18
On Sat, 17 Dec 2022 09:37:26 -0800, John Larkin <jlarkin@highlandSNIPMEtechnology.com> wrote:>On Sat, 17 Dec 2022 09:03:31 -0500, legg <legg@nospam.magma.ca> wrote: > >>On Fri, 16 Dec 2022 08:39:35 -0800, John Larkin >><jlarkin@highlandSNIPMEtechnology.com> wrote: >> >>>On Fri, 16 Dec 2022 10:59:20 -0500, legg <legg@nospam.magma.ca> wrote: >>> >>>>On Wed, 14 Dec 2022 09:01:50 -0800, John Larkin >>>><jlarkin@highlandSNIPMEtechnology.com> wrote: >>>> >>>>> >>>>>This is a 200 watt isolating dc/dc converter: >>>>> >>>>>https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 >>>>> >>>>>Some idiot who shall not be named figured that we could start it up by >>>>>ramping up the drive pulse widths from the FPGA, starting very small >>>>>and eventually making square waves. But even small pulses pull >>>>>hundreds of amps and have side effects like deconfiguring the FPGA. >>>>> >>>>>The fix is to hack in a small board to ramp up the +48 supply, and >>>>>leave the drive a square wave. >>>>> >>>>>https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 >>>>> >>>>>https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0 >>>>> >>>> >>>>Linear slow-start can be lossy. Your simulation doesn't show the >>>>dc-dc downstream load, so only mA are being supplied. >>> >>>Downstream of each dc/dc converter is a half-bridge PWM-programmable >>>DC power supply. But it's off during startup. The startup energy >>>dissipation is tiny, and the soft-start fet is under 20 mohms when >>>things are operating. >>> >>>> >>>>The DC-DC has to be running during slow-start, to be effective. >>> >>>Yes. We will turn on the square wave drive and start the DC voltage >>>ramp simultaneously. The power supply to the inverter will ramp >>>linearly from 0 to 48 in about 200 ms. >>> >>> >>>> >>>>You need to calculate the joules, depending on total reflected DC >>>>load current plus rail capacitance dv/dt. >>> >>>Did that of course. The only startup load is the isolated side caps. >>> >>>> >>>>RL >> >>Love the 48V+ gate enhancement. >> >>I want one of those two terminal current generators. >> >>RL > >It's a TLP191 pv optocoupler, essentially a floating 7 volt 25 uA >power supply.With a high-z gate circuit, there may be issues when the 48V rail is first applied. A conventional fet inrush limiter trys to use Cgd as a dv/dt limiter. In your case this would require a pmos element - the conventional circuitry sticks inrush limiting in the negative rail per telecom practise. RL RL
Reply by ●December 18, 20222022-12-18
On Sun, 18 Dec 2022 07:14:23 GMT, Jan Panteltje <pNaonStpealmtje@yahoo.com> wrote:>On a sunny day (Sat, 17 Dec 2022 09:32:51 -0800) it happened John Larkin ><jlarkin@highlandSNIPMEtechnology.com> wrote in ><nitrph9i9g3ervse2edkt6321bfth4lmn5@4ax.com>: > >>On Sat, 17 Dec 2022 05:46:35 GMT, Jan Panteltje >><pNaonStpealmtje@yahoo.com> wrote: >>>>I don't think the inductor would be a practical size. >>> >>>Resistor? >>> >>> >>>>Here's my soft-start board. >>>> >>>>https://www.dropbox.com/s/hoicw55p91d9muc/99S544A1.pdf?dl=0 >>>Says item was deleted >> >> >>Try this: >> >>https://www.dropbox.com/sh/96adbwr9utgwom0/AACHgFwNj9MKWIxDHAZi-KYNa?dl=0 > >OK, that will work, short dissipation in the MOSFET during the ramp. >When switching in a resistro during filter capacitor charge would work too. >I understood from your posting that at startup there is no other load? > >200 uF of capacitance and maybe 100 mA of stuff on the load side, power for some isolators and a bit of logic. Yes, we could charge up the loads through a power resistor that is shorted by a fet after a second or so. That would be simpler than my cicuit. I'd still need an over-48-volt supply if I use an n-channel fet, or buy a really low Ron p-fet.>> >>Another recent discovery is that we need schottky diodes in parallel >>with the mosfet substate diodes in the h-bridges. Weird things were >>happening during the anti-shoot-through times of the LTC4444 driver >>chips. I've seen mosfet substrate diodes decide to act like high-power >>step-recovery diodes. >> >>> >>>>It bolts onto the power supply board where the fuseholder used to be. >>>>It replicates the fuse and adds the soft start, under FPGA control. >>>> >>>>I like to lay out a small board now and then. >>> >>>Most things I do these days are hobby related on veroboard stuff... >>>Even giggle Hertz stuff.. >> >>Dremel! >> >>https://www.dropbox.com/s/pa9mu4ehtrjei8m/Z384_1.JPG?raw=1 > >Yes, nice, and gold! > >http://panteltje.com/panteltje/raspberry_pi_dvb-s_transmitter/ >scroll down for board, the GHz stuff is bottom right, >In those boards the SMDs fit exactly between 2 isles, many here, >and you can make your 'waveguides' in 3 D... > >http://panteltje.com/pub/2.4GHz_SWR_reflected_with_directional_coupler_IMG_5102.JPG >http://panteltje.com/pub/2.4_GHz_to_1.5_GHz_down_converter_closeup_IMG_4660.JPG >http://panteltje.com/pub/added_2.4_GHz_VCO_IMG_4620.JPG >http://panteltje.com/pub/2.4_GHz_VCO_via_coax_IMG_4624.JPGThat style of construction confuses me. Dead bug confuses me too. I prefer https://www.dropbox.com/s/9av93ul8148zdjm/Z356_SN2.JPG?raw=1 I lost a weekend building two of those for ASML. It's technically "Manhattan Style", little FR4 platforms. You can make nice 50 ohm transmission lines that way, about 120 mils wide using 0.062 thick FR4. https://www.dropbox.com/s/yur6uuhytc7cfcn/D200_BB_4.JPG?raw=1 https://www.dropbox.com/s/5nlhqy7c8mt2xv3/LDP2.JPG?raw=1 I just got some 3M Z-axis conductive tape to play with.>http://panteltje.com/pub/GPS_jammer_board_twisted_wire_1.57GHz_oscillator_IMG_3622.GIF > >I'm planning a product line using the Pi Pico as the compute core. There is an amazing culture around the Pi, a zillion maker-type kids and school courses. It's sometimed dismissed as a toy but serious people are making products around Pi's. Every other uP that we have used has gone EOL anyhow (except, surprisingly, the 68332.)> >>Has anyone tried the Digikey pc boards? >> >>https://www.digikey.com/en/resources/dkred > >InterestingLooks like a few clicks and a zip file upload will get us cheap boards in 5 days. I'll try it.
