torsdag den 15. december 2022 kl. 16.35.42 UTC+1 skrev John Larkin:> On Thu, 15 Dec 2022 15:01:53 +0100, Klaus Vestergaard Kragelund > <klau...@hotmail.com> wrote: > > >On 15-12-2022 05:47, John Miles, KE5FX wrote: > >> On Wednesday, December 14, 2022 at 7:14:33 PM UTC-8, John Larkin wrote: > >>> I'm guessing that the first bridge turn-on pushes hundreds of amps > >>> into the ground plane and makes potentials everywhere. If we make a > >>> square wave into the bridge drive and ramp up the +48 from a bench > >>> supply, it's all nice. > >> > >> But the parts you're using have a frequency response that's not infinite. > >> You can turn them on as slowly as you want by scheduling both the > >> duty cycle and frequency of the pulses. > >> > >> Pulse pairs spaced 5 ns apart aren't going to make it draw hundreds of > >> amps, right? They will never make it through the gate drivers. How about > >> 100 ns apart? Maybe it draws 10 mA now. 1000 ns on, then off? Maybe > >> now it's 500 mA. Etc. > >> > > > >It is possible to do soft start on a bridge configuration like this. > >Like you mention, you need to be able to generate very close matching > >duty cycles to start with ns ON cycles. > > > >Normally you would have an output inductor, since otherwise only leakage > >inductances limits the currents > > > I seems that the gate drivers won't pass very narrow pulses, and we'd > have to tease the fet gate thresholds in some analog manner. We tried > FPGA things that didn't work.so don't use narrow pulses, run both half bridges at 50/50 duty cycle and delay one of them 0-180 degrees
soft-start blunder
Started by ●December 14, 2022
Reply by ●December 15, 20222022-12-15
Reply by ●December 15, 20222022-12-15
On Thu, 15 Dec 2022 08:10:10 -0800 (PST), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>torsdag den 15. december 2022 kl. 16.35.42 UTC+1 skrev John Larkin: >> On Thu, 15 Dec 2022 15:01:53 +0100, Klaus Vestergaard Kragelund >> <klau...@hotmail.com> wrote: >> >> >On 15-12-2022 05:47, John Miles, KE5FX wrote: >> >> On Wednesday, December 14, 2022 at 7:14:33 PM UTC-8, John Larkin wrote: >> >>> I'm guessing that the first bridge turn-on pushes hundreds of amps >> >>> into the ground plane and makes potentials everywhere. If we make a >> >>> square wave into the bridge drive and ramp up the +48 from a bench >> >>> supply, it's all nice. >> >> >> >> But the parts you're using have a frequency response that's not infinite. >> >> You can turn them on as slowly as you want by scheduling both the >> >> duty cycle and frequency of the pulses. >> >> >> >> Pulse pairs spaced 5 ns apart aren't going to make it draw hundreds of >> >> amps, right? They will never make it through the gate drivers. How about >> >> 100 ns apart? Maybe it draws 10 mA now. 1000 ns on, then off? Maybe >> >> now it's 500 mA. Etc. >> >> >> > >> >It is possible to do soft start on a bridge configuration like this. >> >Like you mention, you need to be able to generate very close matching >> >duty cycles to start with ns ON cycles. >> > >> >Normally you would have an output inductor, since otherwise only leakage >> >inductances limits the currents >> > >> I seems that the gate drivers won't pass very narrow pulses, and we'd >> have to tease the fet gate thresholds in some analog manner. We tried >> FPGA things that didn't work. > >so don't use narrow pulses, run both half bridges at 50/50 duty cycle and delay one of them 0-180 degrees >That is morally equivalent to starting with narrow pulses. The way the drivers are wired, we can't do that anyhow.
Reply by ●December 15, 20222022-12-15
On 15-12-2022 17:10, Lasse Langwadt Christensen wrote:> torsdag den 15. december 2022 kl. 16.35.42 UTC+1 skrev John Larkin: >> On Thu, 15 Dec 2022 15:01:53 +0100, Klaus Vestergaard Kragelund >> <klau...@hotmail.com> wrote: >> >>> On 15-12-2022 05:47, John Miles, KE5FX wrote: >>>> On Wednesday, December 14, 2022 at 7:14:33 PM UTC-8, John Larkin wrote: >>>>> I'm guessing that the first bridge turn-on pushes hundreds of amps >>>>> into the ground plane and makes potentials everywhere. If we make a >>>>> square wave into the bridge drive and ramp up the +48 from a bench >>>>> supply, it's all nice. >>>> >>>> But the parts you're using have a frequency response that's not infinite. >>>> You can turn them on as slowly as you want by scheduling both the >>>> duty cycle and frequency of the pulses. >>>> >>>> Pulse pairs spaced 5 ns apart aren't going to make it draw hundreds of >>>> amps, right? They will never make it through the gate drivers. How about >>>> 100 ns apart? Maybe it draws 10 mA now. 1000 ns on, then off? Maybe >>>> now it's 500 mA. Etc. >>>> >>> >>> It is possible to do soft start on a bridge configuration like this. >>> Like you mention, you need to be able to generate very close matching >>> duty cycles to start with ns ON cycles. >>> >>> Normally you would have an output inductor, since otherwise only leakage >>> inductances limits the currents >>> >> I seems that the gate drivers won't pass very narrow pulses, and we'd >> have to tease the fet gate thresholds in some analog manner. We tried >> FPGA things that didn't work. > > so don't use narrow pulses, run both half bridges at 50/50 duty cycle and delay one of them 0-180 degrees > >Yes, that was actually what I suggested also :-)
Reply by ●December 16, 20222022-12-16
On a sunny day (Wed, 14 Dec 2022 22:45:39 -0800) it happened John Larkin <jlarkin@highlandSNIPMEtechnology.com> wrote in <t8glph139gjr602hqd7oc43691q0gi9r2d@4ax.com>:>On Thu, 15 Dec 2022 05:45:45 GMT, Jan Panteltje ><pNaonStpealmtje@yahoo.com> wrote: > >>On a sunny day (Wed, 14 Dec 2022 09:01:50 -0800) it happened John Larkin >><jlarkin@highlandSNIPMEtechnology.com> wrote in >><cmvjphpgkb4sf3s7to9c8di0ph70um8f6q@4ax.com>: >> >>> >>>This is a 200 watt isolating dc/dc converter: >>> >>>https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 >>> >>>Some idiot who shall not be named figured that we could start it up by >>>ramping up the drive pulse widths from the FPGA, starting very small >>>and eventually making square waves. But even small pulses pull >>>hundreds of amps and have side effects like deconfiguring the FPGA. >>> >>>The fix is to hack in a small board to ramp up the +48 supply, and >>>leave the drive a square wave. >>> >>>https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 >>> >>>https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0 >> >>Cannot read ASCII but small series inductor shorted after power-up before secondary >>rectifier capacitor? >>Only takes one power MOSFET? > > >Here's an improved version. > >https://www.dropbox.com/s/yv8wvzxya26bm5o/Z544_SoftStart_3.jpg?raw=1 > > >The FPGA will start up the 250 KHz square wave into the h-bridge >drivers, and then enable the 48 volt linear ramp. That should start up >nice and smooth. > >My weekend assignment is to lay out the kluge board. >This was what I thought of: http://panteltje.com/pub/startup__impuse_reducer_IXIMG_0906.JPG as the output voltage increases the inductor is shorted by the power MOSFET. Sorry for bad drawing here in zero graffiti Doing things low power is easier of course. Yesterday I fixed a satellite receiver by replacing a STI8035 (LNB power controller). Now that was a fight getting the bad (shorted one) of the board and then also replacing some caps, the old caps were even smaller than the smallest SMDs I have, replaced those by mine connected with wires.. The new sat box I got recently (while waiting for the parts) is even HALF the size of the old one, http://panteltje.com/pub/sat_box_sizes_IXIMG_0907.JPG had a look inside, same circuit and software!! how long will we be able to repair stuff without a microscope?? ebay selller send me some chips from France, really quick. China specified end February or something. The old China made box did leave out the protection diodes suggested in the STI8035 data sheet, so bang... There was space and pads for those on the PCB... Then again what you can get for 25$ is amazing.... I pay more for the box and connectors alone, But of course problem plenty: every Chinese thing has the same remotes these days.. http://panteltje.com/pub/same_remotes_IXIMG_0908.JPG So switch off your sat receiver then your terrestrial TV tuner is off too! The new smaller one has the same remote but seems to use different codes so that fixes that problem.>900 TV channels.... But EU killed the Russian channels.
Reply by ●December 16, 20222022-12-16
On Fri, 16 Dec 2022 06:08:23 GMT, Jan Panteltje <pNaonStpealmtje@yahoo.com> wrote:>On a sunny day (Wed, 14 Dec 2022 22:45:39 -0800) it happened John Larkin ><jlarkin@highlandSNIPMEtechnology.com> wrote in ><t8glph139gjr602hqd7oc43691q0gi9r2d@4ax.com>: > >>On Thu, 15 Dec 2022 05:45:45 GMT, Jan Panteltje >><pNaonStpealmtje@yahoo.com> wrote: >> >>>On a sunny day (Wed, 14 Dec 2022 09:01:50 -0800) it happened John Larkin >>><jlarkin@highlandSNIPMEtechnology.com> wrote in >>><cmvjphpgkb4sf3s7to9c8di0ph70um8f6q@4ax.com>: >>> >>>> >>>>This is a 200 watt isolating dc/dc converter: >>>> >>>>https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 >>>> >>>>Some idiot who shall not be named figured that we could start it up by >>>>ramping up the drive pulse widths from the FPGA, starting very small >>>>and eventually making square waves. But even small pulses pull >>>>hundreds of amps and have side effects like deconfiguring the FPGA. >>>> >>>>The fix is to hack in a small board to ramp up the +48 supply, and >>>>leave the drive a square wave. >>>> >>>>https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 >>>> >>>>https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0 >>> >>>Cannot read ASCII but small series inductor shorted after power-up before secondary >>>rectifier capacitor? >>>Only takes one power MOSFET? >> >> >>Here's an improved version. >> >>https://www.dropbox.com/s/yv8wvzxya26bm5o/Z544_SoftStart_3.jpg?raw=1 >> >> >>The FPGA will start up the 250 KHz square wave into the h-bridge >>drivers, and then enable the 48 volt linear ramp. That should start up >>nice and smooth. >> >>My weekend assignment is to lay out the kluge board. >> > >This was what I thought of: > http://panteltje.com/pub/startup__impuse_reducer_IXIMG_0906.JPG >as the output voltage increases the inductor is shorted by the power MOSFET. >Sorry for bad drawing here in zero graffiti >Doing things low power is easier of course.I don't think the inductor would be a practical size. Here's my soft-start board. https://www.dropbox.com/s/hoicw55p91d9muc/99S544A1.pdf?dl=0 https://www.dropbox.com/s/rllue2bl0dl0ve5/Z544_SoftStart_A1.jpg?raw=1 It bolts onto the power supply board where the fuseholder used to be. It replicates the fuse and adds the soft start, under FPGA control. I like to lay out a small board now and then.
Reply by ●December 16, 20222022-12-16
On Wed, 14 Dec 2022 09:01:50 -0800, John Larkin <jlarkin@highlandSNIPMEtechnology.com> wrote:> >This is a 200 watt isolating dc/dc converter: > >https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 > >Some idiot who shall not be named figured that we could start it up by >ramping up the drive pulse widths from the FPGA, starting very small >and eventually making square waves. But even small pulses pull >hundreds of amps and have side effects like deconfiguring the FPGA. > >The fix is to hack in a small board to ramp up the +48 supply, and >leave the drive a square wave. > >https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 > >https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0 >Linear slow-start can be lossy. Your simulation doesn't show the dc-dc downstream load, so only mA are being supplied. The DC-DC has to be running during slow-start, to be effective. You need to calculate the joules, depending on total reflected DC load current plus rail capacitance dv/dt. RL
Reply by ●December 16, 20222022-12-16
On Thu, 15 Dec 2022 08:10:10 -0800 (PST), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>torsdag den 15. december 2022 kl. 16.35.42 UTC+1 skrev John Larkin: >> On Thu, 15 Dec 2022 15:01:53 +0100, Klaus Vestergaard Kragelund >> <klau...@hotmail.com> wrote: >> >> >On 15-12-2022 05:47, John Miles, KE5FX wrote: >> >> On Wednesday, December 14, 2022 at 7:14:33 PM UTC-8, John Larkin wrote: >> >>> I'm guessing that the first bridge turn-on pushes hundreds of amps >> >>> into the ground plane and makes potentials everywhere. If we make a >> >>> square wave into the bridge drive and ramp up the +48 from a bench >> >>> supply, it's all nice. >> >> >> >> But the parts you're using have a frequency response that's not infinite. >> >> You can turn them on as slowly as you want by scheduling both the >> >> duty cycle and frequency of the pulses. >> >> >> >> Pulse pairs spaced 5 ns apart aren't going to make it draw hundreds of >> >> amps, right? They will never make it through the gate drivers. How about >> >> 100 ns apart? Maybe it draws 10 mA now. 1000 ns on, then off? Maybe >> >> now it's 500 mA. Etc. >> >> >> > >> >It is possible to do soft start on a bridge configuration like this. >> >Like you mention, you need to be able to generate very close matching >> >duty cycles to start with ns ON cycles. >> > >> >Normally you would have an output inductor, since otherwise only leakage >> >inductances limits the currents >> > >> I seems that the gate drivers won't pass very narrow pulses, and we'd >> have to tease the fet gate thresholds in some analog manner. We tried >> FPGA things that didn't work. > >so don't use narrow pulses, run both half bridges at 50/50 duty cycle and delay one of them 0-180 degrees >You're supposed to be able to do anything with the FPGA (?) driver. Isn't that the whole idea behind direct digital control? RL
Reply by ●December 16, 20222022-12-16
On Fri, 16 Dec 2022 11:03:25 -0500, legg <legg@nospam.magma.ca> wrote:>On Thu, 15 Dec 2022 08:10:10 -0800 (PST), Lasse Langwadt Christensen ><langwadt@fonz.dk> wrote: > >>torsdag den 15. december 2022 kl. 16.35.42 UTC+1 skrev John Larkin: >>> On Thu, 15 Dec 2022 15:01:53 +0100, Klaus Vestergaard Kragelund >>> <klau...@hotmail.com> wrote: >>> >>> >On 15-12-2022 05:47, John Miles, KE5FX wrote: >>> >> On Wednesday, December 14, 2022 at 7:14:33 PM UTC-8, John Larkin wrote: >>> >>> I'm guessing that the first bridge turn-on pushes hundreds of amps >>> >>> into the ground plane and makes potentials everywhere. If we make a >>> >>> square wave into the bridge drive and ramp up the +48 from a bench >>> >>> supply, it's all nice. >>> >> >>> >> But the parts you're using have a frequency response that's not infinite. >>> >> You can turn them on as slowly as you want by scheduling both the >>> >> duty cycle and frequency of the pulses. >>> >> >>> >> Pulse pairs spaced 5 ns apart aren't going to make it draw hundreds of >>> >> amps, right? They will never make it through the gate drivers. How about >>> >> 100 ns apart? Maybe it draws 10 mA now. 1000 ns on, then off? Maybe >>> >> now it's 500 mA. Etc. >>> >> >>> > >>> >It is possible to do soft start on a bridge configuration like this. >>> >Like you mention, you need to be able to generate very close matching >>> >duty cycles to start with ns ON cycles. >>> > >>> >Normally you would have an output inductor, since otherwise only leakage >>> >inductances limits the currents >>> > >>> I seems that the gate drivers won't pass very narrow pulses, and we'd >>> have to tease the fet gate thresholds in some analog manner. We tried >>> FPGA things that didn't work. >> >>so don't use narrow pulses, run both half bridges at 50/50 duty cycle and delay one of them 0-180 degrees >> > >You're supposed to be able to do anything with the >FPGA (?) driver. Isn't that the whole idea behind >direct digital control? > >RLWe can't think of a way to start up the dc/dc inverters with digital control. The peak currents are just too high. Smaller fets might work, at loss of efficiency. The power supply rampup should work.
Reply by ●December 16, 20222022-12-16
On Fri, 16 Dec 2022 10:59:20 -0500, legg <legg@nospam.magma.ca> wrote:>On Wed, 14 Dec 2022 09:01:50 -0800, John Larkin ><jlarkin@highlandSNIPMEtechnology.com> wrote: > >> >>This is a 200 watt isolating dc/dc converter: >> >>https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 >> >>Some idiot who shall not be named figured that we could start it up by >>ramping up the drive pulse widths from the FPGA, starting very small >>and eventually making square waves. But even small pulses pull >>hundreds of amps and have side effects like deconfiguring the FPGA. >> >>The fix is to hack in a small board to ramp up the +48 supply, and >>leave the drive a square wave. >> >>https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 >> >>https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0 >> > >Linear slow-start can be lossy. Your simulation doesn't show the >dc-dc downstream load, so only mA are being supplied.Downstream of each dc/dc converter is a half-bridge PWM-programmable DC power supply. But it's off during startup. The startup energy dissipation is tiny, and the soft-start fet is under 20 mohms when things are operating.> >The DC-DC has to be running during slow-start, to be effective.Yes. We will turn on the square wave drive and start the DC voltage ramp simultaneously. The power supply to the inverter will ramp linearly from 0 to 48 in about 200 ms.> >You need to calculate the joules, depending on total reflected DC >load current plus rail capacitance dv/dt.Did that of course. The only startup load is the isolated side caps.> >RL
Reply by ●December 16, 20222022-12-16
fredag den 16. december 2022 kl. 17.02.10 UTC+1 skrev legg:> On Thu, 15 Dec 2022 08:10:10 -0800 (PST), Lasse Langwadt Christensen > <lang...@fonz.dk> wrote: > >torsdag den 15. december 2022 kl. 16.35.42 UTC+1 skrev John Larkin: > >> On Thu, 15 Dec 2022 15:01:53 +0100, Klaus Vestergaard Kragelund > >> <klau...@hotmail.com> wrote: > >> > >> >On 15-12-2022 05:47, John Miles, KE5FX wrote: > >> >> On Wednesday, December 14, 2022 at 7:14:33 PM UTC-8, John Larkin wrote: > >> >>> I'm guessing that the first bridge turn-on pushes hundreds of amps > >> >>> into the ground plane and makes potentials everywhere. If we make a > >> >>> square wave into the bridge drive and ramp up the +48 from a bench > >> >>> supply, it's all nice. > >> >> > >> >> But the parts you're using have a frequency response that's not infinite. > >> >> You can turn them on as slowly as you want by scheduling both the > >> >> duty cycle and frequency of the pulses. > >> >> > >> >> Pulse pairs spaced 5 ns apart aren't going to make it draw hundreds of > >> >> amps, right? They will never make it through the gate drivers. How about > >> >> 100 ns apart? Maybe it draws 10 mA now. 1000 ns on, then off? Maybe > >> >> now it's 500 mA. Etc. > >> >> > >> > > >> >It is possible to do soft start on a bridge configuration like this. > >> >Like you mention, you need to be able to generate very close matching > >> >duty cycles to start with ns ON cycles. > >> > > >> >Normally you would have an output inductor, since otherwise only leakage > >> >inductances limits the currents > >> > > >> I seems that the gate drivers won't pass very narrow pulses, and we'd > >> have to tease the fet gate thresholds in some analog manner. We tried > >> FPGA things that didn't work. > > > >so don't use narrow pulses, run both half bridges at 50/50 duty cycle and delay one of them 0-180 degrees > > > You're supposed to be able to do anything with the > FPGA (?) driver. Isn't that the whole idea behind > direct digital control?sure, the 50/50 and phaseshift just gets around the problem of the gate drivers swallowing short pulses, but it seems the board isn't wired to be able to do that
