On Wed, 14 Dec 2022 18:46:33 -0800 (PST), "John Miles, KE5FX" <jmiles@gmail.com> wrote:>On Wednesday, December 14, 2022 at 9:02:00 AM UTC-8, John Larkin wrote: >> Some idiot who shall not be named figured that we could start it up by >> ramping up the drive pulse widths from the FPGA, starting very small >> and eventually making square waves. But even small pulses pull >> hundreds of amps and have side effects like deconfiguring the FPGA. > >Doesn't sound like a bad idea, really. Have you played with frequency, >or just the duty cycle? If a very short duty cycle and very low initial >frequency still hose the FPGA, the problem is going to be unwanted >coupling somewhere, probably between different power buses. > >-- john, KE5FXI'm guessing that the first bridge turn-on pushes hundreds of amps into the ground plane and makes potentials everywhere. If we make a square wave into the bridge drive and ramp up the +48 from a bench supply, it's all nice.
soft-start blunder
Started by ●December 14, 2022
Reply by ●December 14, 20222022-12-14
Reply by ●December 15, 20222022-12-15
On Wednesday, December 14, 2022 at 7:14:33 PM UTC-8, John Larkin wrote:> I'm guessing that the first bridge turn-on pushes hundreds of amps > into the ground plane and makes potentials everywhere. If we make a > square wave into the bridge drive and ramp up the +48 from a bench > supply, it's all nice.But the parts you're using have a frequency response that's not infinite. You can turn them on as slowly as you want by scheduling both the duty cycle and frequency of the pulses. Pulse pairs spaced 5 ns apart aren't going to make it draw hundreds of amps, right? They will never make it through the gate drivers. How about 100 ns apart? Maybe it draws 10 mA now. 1000 ns on, then off? Maybe now it's 500 mA. Etc. -- john, KE5FX
Reply by ●December 15, 20222022-12-15
On a sunny day (Wed, 14 Dec 2022 09:01:50 -0800) it happened John Larkin <jlarkin@highlandSNIPMEtechnology.com> wrote in <cmvjphpgkb4sf3s7to9c8di0ph70um8f6q@4ax.com>:> >This is a 200 watt isolating dc/dc converter: > >https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 > >Some idiot who shall not be named figured that we could start it up by >ramping up the drive pulse widths from the FPGA, starting very small >and eventually making square waves. But even small pulses pull >hundreds of amps and have side effects like deconfiguring the FPGA. > >The fix is to hack in a small board to ramp up the +48 supply, and >leave the drive a square wave. > >https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 > >https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0Cannot read ASCII but small series inductor shorted after power-up before secondary rectifier capacitor? Only takes one power MOSFET?
Reply by ●December 15, 20222022-12-15
On Thu, 15 Dec 2022 05:45:45 GMT, Jan Panteltje <pNaonStpealmtje@yahoo.com> wrote:>On a sunny day (Wed, 14 Dec 2022 09:01:50 -0800) it happened John Larkin ><jlarkin@highlandSNIPMEtechnology.com> wrote in ><cmvjphpgkb4sf3s7to9c8di0ph70um8f6q@4ax.com>: > >> >>This is a 200 watt isolating dc/dc converter: >> >>https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 >> >>Some idiot who shall not be named figured that we could start it up by >>ramping up the drive pulse widths from the FPGA, starting very small >>and eventually making square waves. But even small pulses pull >>hundreds of amps and have side effects like deconfiguring the FPGA. >> >>The fix is to hack in a small board to ramp up the +48 supply, and >>leave the drive a square wave. >> >>https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 >> >>https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0 > >Cannot read ASCII but small series inductor shorted after power-up before secondary >rectifier capacitor? >Only takes one power MOSFET?Here's an improved version. https://www.dropbox.com/s/yv8wvzxya26bm5o/Z544_SoftStart_3.jpg?raw=1 The FPGA will start up the 250 KHz square wave into the h-bridge drivers, and then enable the 48 volt linear ramp. That should start up nice and smooth. My weekend assignment is to lay out the kluge board.
Reply by ●December 15, 20222022-12-15
On 2022-12-14, John Larkin <jlarkin@highlandSNIPMEtechnology.com> wrote:> > This is a 200 watt isolating dc/dc converter: > > https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 > > Some idiot who shall not be named figured that we could start it up by > ramping up the drive pulse widths from the FPGA, starting very small > and eventually making square waves. But even small pulses pull > hundreds of amps and have side effects like deconfiguring the FPGA. > > The fix is to hack in a small board to ramp up the +48 supply, and > leave the drive a square wave. > > https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 > > https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0Hmm, it looks to be a forwards converter topology, so volts in is basically proportional to volts out, your only lattitude to regulate the output seems to be messing with the frequency, or doing "burp mode" - which is still messing with the frequency just with less distortion to the spectrum. You could get a half-voltage mode by only running one half of the bridge. Putting an inductor between the bridge rectifier and the capacitor could help PWM response. -- Jasen.
Reply by ●December 15, 20222022-12-15
On 15-12-2022 05:47, John Miles, KE5FX wrote:> On Wednesday, December 14, 2022 at 7:14:33 PM UTC-8, John Larkin wrote: >> I'm guessing that the first bridge turn-on pushes hundreds of amps >> into the ground plane and makes potentials everywhere. If we make a >> square wave into the bridge drive and ramp up the +48 from a bench >> supply, it's all nice. > > But the parts you're using have a frequency response that's not infinite. > You can turn them on as slowly as you want by scheduling both the > duty cycle and frequency of the pulses. > > Pulse pairs spaced 5 ns apart aren't going to make it draw hundreds of > amps, right? They will never make it through the gate drivers. How about > 100 ns apart? Maybe it draws 10 mA now. 1000 ns on, then off? Maybe > now it's 500 mA. Etc. >It is possible to do soft start on a bridge configuration like this. Like you mention, you need to be able to generate very close matching duty cycles to start with ns ON cycles. Normally you would have an output inductor, since otherwise only leakage inductances limits the currents
Reply by ●December 15, 20222022-12-15
On Wednesday, December 14, 2022 at 2:43:59 PM UTC-5, erichp...@hotmail.com wrote:> On 14/12/2022 6:44 pm, Fred Bloggs wrote: > > > > That's actually the best approach BUT you have to be able kill the transformer drive, either both H or both L, otherwise the core keeps integrating voltage and accumulating flux. Doesn't look like you have that capability. > > > Do the capacitors in series with the primary help prevent that? > > pigletCapacitors are good for averages but not so good for peaks. His problem sounds like he has minimal margin from Bsat in normal operation. I bet that transformer gets hot.
Reply by ●December 15, 20222022-12-15
On Thu, 15 Dec 2022 15:01:53 +0100, Klaus Vestergaard Kragelund <klauskvik@hotmail.com> wrote:>On 15-12-2022 05:47, John Miles, KE5FX wrote: >> On Wednesday, December 14, 2022 at 7:14:33 PM UTC-8, John Larkin wrote: >>> I'm guessing that the first bridge turn-on pushes hundreds of amps >>> into the ground plane and makes potentials everywhere. If we make a >>> square wave into the bridge drive and ramp up the +48 from a bench >>> supply, it's all nice. >> >> But the parts you're using have a frequency response that's not infinite. >> You can turn them on as slowly as you want by scheduling both the >> duty cycle and frequency of the pulses. >> >> Pulse pairs spaced 5 ns apart aren't going to make it draw hundreds of >> amps, right? They will never make it through the gate drivers. How about >> 100 ns apart? Maybe it draws 10 mA now. 1000 ns on, then off? Maybe >> now it's 500 mA. Etc. >> > >It is possible to do soft start on a bridge configuration like this. >Like you mention, you need to be able to generate very close matching >duty cycles to start with ns ON cycles. > >Normally you would have an output inductor, since otherwise only leakage >inductances limits the currents >I seems that the gate drivers won't pass very narrow pulses, and we'd have to tease the fet gate thresholds in some analog manner. We tried FPGA things that didn't work. The +48 ramper works and is an easy analog fix. 8 little parts, 10 if I include an LED.
Reply by ●December 15, 20222022-12-15
On Thu, 15 Dec 2022 06:50:31 -0000 (UTC), Jasen Betts <usenet@revmaps.no-ip.org> wrote:>On 2022-12-14, John Larkin <jlarkin@highlandSNIPMEtechnology.com> wrote: >> >> This is a 200 watt isolating dc/dc converter: >> >> https://www.dropbox.com/s/9k0oe2rc67mmvc1/23S941A_iso_ps.pdf?dl=0 >> >> Some idiot who shall not be named figured that we could start it up by >> ramping up the drive pulse widths from the FPGA, starting very small >> and eventually making square waves. But even small pulses pull >> hundreds of amps and have side effects like deconfiguring the FPGA. >> >> The fix is to hack in a small board to ramp up the +48 supply, and >> leave the drive a square wave. >> >> https://www.dropbox.com/s/q8znxmv44llm5zb/P941_SS_1.asc?dl=0 >> >> https://www.dropbox.com/s/xfvpxryevel6d5m/P940_SS_hack_1.jpg?dl=0 > >Hmm, it looks to be a forwards converter topology, so volts in is >basically proportional to volts out, your only lattitude to regulate >the output seems to be messing with the frequency, or doing "burp mode" >- which is still messing with the frequency just with less distortion >to the spectrum.We want isolated 56 volts, which actually drives another half-bridge+lowpass filter which is our final output. That topology has good open-loop dynamics from 0 to 42 volts out, at any load. Nothing ever goes discontinuous. It works great, once we get it started up.> >You could get a half-voltage mode by only running one half of the >bridge. > >Putting an inductor between the bridge rectifier and the capacitor >could help PWM response.That becomes a classic forward converter, ugly over the load range. I'm not sure what to call the square-wave version without the inductor; I call it a dc/dc converter. After decades in the picosecond and photonics business, I find myself in the power supply business. Pico becomes milli. Here's the board. https://www.dropbox.com/s/cq7blf81wzbk1b2/P941A_Top.jpg?raw=1 I'll do a quick-turn board to add the soft-start as a bolt-on hack. We'll do that nice in rev B.
Reply by ●December 15, 20222022-12-15
On Thu, 15 Dec 2022 07:19:38 -0800 (PST), Fred Bloggs <bloggs.fredbloggs.fred@gmail.com> wrote:>On Wednesday, December 14, 2022 at 2:43:59 PM UTC-5, erichp...@hotmail.com wrote: >> On 14/12/2022 6:44 pm, Fred Bloggs wrote: >> > >> > That's actually the best approach BUT you have to be able kill the transformer drive, either both H or both L, otherwise the core keeps integrating voltage and accumulating flux. Doesn't look like you have that capability. >> > >> Do the capacitors in series with the primary help prevent that? >> >> piglet > >Capacitors are good for averages but not so good for peaks. His problem sounds like he has minimal margin from Bsat in normal operation. I bet that transformer gets hot.Just a little warm. At max current load, it's mostly copper/skin loss, but not much. The giant peak currents on the first short pulse are't magnetizing current, it's from the bridge rectifiers and caps on the secondary. This Coilcraft planar transformer is in fact too good.
