On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky: >> On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote: >> > torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky: >> > > On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote: >> > > > On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky >> > > > <gnuarm.del...@gmail.com> wrote: >> > > > >On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: >> > > > >> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >> > > > >> wrote: >> > > > >> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >> > > > >> > >> > > > >> >> My question was, why make a sine wave if the final result is a digital >> > > > >> >> clock? >> > > > >> > >> > > > >> >Do you want the digital clock edges to be synchronous with an existing source, or >> > > > >> >asynchronous? Mathematically, the creation of an asynchronous clock is >> > > > >> >not gonna happen in clocked logic circuitry, it has to have an analog component. >> > > > >> Of course. The analog components are dac, filter, comparator. >> > > > >> >> > > > >> I want a programmable internal trigger rate for a pulse generator. >> > > > >> >> > > > >> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >> > > > >> up to Nyquist. But it gets messy at low frequencies where the dac is >> > > > >> incremented infrequently and the filter doesn't do much. >> > > > > >> > > > >Sounds like an application for dithering. >> > > > >> > > > Do you even need explicit dithering ? >> > > > >> > > > The DAC output has some wide band (thermal) white noise. If the wide >> > > > noise power is close to the LSB size, do you need additional >> > > > dithering?. At low frequencies, there is also the 1/f noise. >> > > > >> > > > For audio frequencies "24 bit" 192 kHz DACs are available, which >> > > > accepts 24 bit sample values, but in practice the last few LSB bits >> > > > are buried in noise. >> > > > >> > > > If you need better dither control, some DDS chips have phase and/or >> > > > amplitude modulators built in, so the PM/AM inputs can be used to >> > > > control the high frequency dither more precisely. >> > > larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock. >> > > >> > > He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to filter. >> > > >> > > The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas. >> > > >> > > I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for the different ranges of clock output rates. >> > > >> > > Don't you agree? >> > afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate >> And your point is? >> >> If larkin is talking about producing a square or "trapezoidal" wave from the NCO and skipping the filter, that's fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the NCO truncation. >> >> Maybe I shouldn't say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn't produce the unfilterable spurs. I'm not betting on it. >> > >you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine >you want to turn that into a square wave so you stick it into a comparator. > >The comparator isn't perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc. >At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s >so 1uV tresh hold variation turns into a ~16us timing variation > >ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop >the peaks off since we are only interested in the zero crossing >so 1uV tresh hold variation is now only a ~160ns timing variationYes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC will change about every millisecond. And theoretically one step parks at zero volts. So jitter is bad. Gain doesn't improve things. -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
DDS questions
Started by ●August 7, 2022
Reply by ●August 11, 20222022-08-11
Reply by ●August 11, 20222022-08-11
On Thu, 11 Aug 2022 15:08:28 -0700, John Larkin wrote:> On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > >>torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky: >>> On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk >>> wrote: >>> > torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky: >>> > > On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, >>> > > upsid...@downunder.com wrote: >>> > > > On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky >>> > > > <gnuarm.del...@gmail.com> wrote: >>> > > > >On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin >>> > > > >wrote: >>> > > > >> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd >>> > > > >> <whi...@gmail.com> wrote: >>> > > > >> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin >>> > > > >> >wrote: >>> > > > >> > >>> > > > >> >> My question was, why make a sine wave if the final result >>> > > > >> >> is a digital clock? >>> > > > >> > >>> > > > >> >Do you want the digital clock edges to be synchronous with >>> > > > >> >an existing source, or asynchronous? Mathematically, the >>> > > > >> >creation of an asynchronous clock is not gonna happen in >>> > > > >> >clocked logic circuitry, it has to have an analog component. >>> > > > >> Of course. The analog components are dac, filter, comparator. >>> > > > >> >>> > > > >> I want a programmable internal trigger rate for a pulse >>> > > > >> generator. >>> > > > >> >>> > > > >> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for >>> > > > >> arbitrary N, >>> > > > >> up to Nyquist. But it gets messy at low frequencies where the >>> > > > >> dac is incremented infrequently and the filter doesn't do >>> > > > >> much. >>> > > > > >>> > > > >Sounds like an application for dithering. >>> > > > >>> > > > Do you even need explicit dithering ? >>> > > > >>> > > > The DAC output has some wide band (thermal) white noise. If the >>> > > > wide noise power is close to the LSB size, do you need >>> > > > additional dithering?. At low frequencies, there is also the 1/f >>> > > > noise. >>> > > > >>> > > > For audio frequencies "24 bit" 192 kHz DACs are available, which >>> > > > accepts 24 bit sample values, but in practice the last few LSB >>> > > > bits are buried in noise. >>> > > > >>> > > > If you need better dither control, some DDS chips have phase >>> > > > and/or amplitude modulators built in, so the PM/AM inputs can be >>> > > > used to control the high frequency dither more precisely. >>> > > larkin is concerned about what amounts to dead band in the input >>> > > to the DAC. I believe he is talking about much higher sample rates >>> > > than what you can get in audio DACs. He wants to program clock >>> > > rates over a very wide range. Otherwise, none of this is a >>> > > problem. It's also not a problem if multiple filters are switched >>> > > depending on the frequency of the output clock. >>> > > >>> > > He's already talked about using octave dividers to slow the clock. >>> > > He is trying to view the problem from a very different perspective >>> > > to see if he can gain some insight rather than using the standard, >>> > > well defined approach. From what I've read, if he is looking for >>> > > minimum jitter, there's nothing better than optimizing the length >>> > > of the phase counter, then using any of various means for >>> > > generating a sine waveform with high resolution, then rounding to >>> > > the data width of your DAC. If the clipping/rounding is done at >>> > > the phase word, it introduces close in spurs that can not be >>> > > effectively filtered out. The spurs introduced by rounding or >>> > > truncation of the sine data, tend to be harmonically related to >>> > > the fundamental, and so are much easier to filter. >>> > > >>> > > The rocket science of NCO/DDS has already been researched and it >>> > > is now more of a cookbook matter, other than the details of >>> > > implementing the hardware, which has lots of analog gotchas. >>> > > >>> > > I've never looked at the idea of using dither on the digital sine >>> > > values, but it might have some utility in this case. I think the >>> > > best solution, though, and certainly more likely to produce a good >>> > > result, is to implement different low pass filters for the >>> > > different ranges of clock output rates. >>> > > >>> > > Don't you agree? >>> > afaict we are talking about making a square wave from the DDS >>> > output, so the issues is if you have, say just as an example, 1mV of >>> > noise on where there comparator switches. The slow slewrate of a >>> > sinewave going through that 1mV can cause more just jitter on the >>> > resulting squarewave than just hammering through that 1mV window >>> > with some waveform with a high slewrate >>> And your point is? >>> >>> If larkin is talking about producing a square or "trapezoidal" wave >>> from the NCO and skipping the filter, that's fine. He will get a >>> jitter of one clock period. Adding a filter will do little to clean up >>> jitter in the square wave and will slow the edge rate to create the >>> noise sensitivity problem again. If the requirements allow this much >>> jitter, then there was no need for all the fuss in the first place. If >>> he needs low ps level jitter, then he has to mitigate the close in >>> spurs created by the NCO truncation. >>> >>> Maybe I shouldn't say that. The close in spurs are from phase >>> truncation, but maybe they only appear when running that through the >>> sine wave generator. If you skip the sine generation, perhaps that >>> doesn't produce the unfilterable spurs. I'm not betting on it. >>> >>> >>you are missing the point. Imagine you have a perfect DDS and filter >>combo that makes an absolutely perfect 2Vpp 1Hz sine you want to turn >>that into a square wave so you stick it into a comparator. >> >>The comparator isn't perfect, the thresh hold varies by, lets say 1uV >>just to pick a number, due to noise etc. >>At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s so 1uV tresh >>hold variation turns into a ~16us timing variation >> >>ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes >>628V/s, the DAC can't make 200V so we'll chop the peaks off since we are >>only interested in the zero crossing so 1uV tresh hold variation is now >>only a ~160ns timing variation > > Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC will > change about every millisecond. And theoretically one step parks at zero > volts. So jitter is bad. Gain doesn't improve things.So if I have this right the DDS has lowest jitter at high frequencies and a digital clock will have lowest jitter at low frequencies, where you can calculate the optimal crossover frequency between the two for lowest jitter across a wide range, and you want to use the phase accumulator? of the DDS as your digital clock at lower frequencies, allowing for fast synchronized transition between the two? Been a long time since I used a DDS, not at all clear on the details, but is this basically what you are trying to do? Glen
Reply by ●August 11, 20222022-08-11
On Thursday, August 11, 2022 at 3:08:46 PM UTC-7, John Larkin wrote:> On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen > <lang...@fonz.dk> wrote:> >ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop > >the peaks off since we are only interested in the zero crossing > >so 1uV tresh hold variation is now only a ~160ns timing variation> Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC > will change about every millisecond. And theoretically one step parks > at zero volts. So jitter is bad. Gain doesn't improve things.Oh, if your goal is to clock logic, gain certainly DOES improve things; you want the fast rise. And, 'one step' is exactly what the filter doesn't pass; your DAC is clocked at sub-microsecond intervals complete with some dither, and the microsecond-steps are filtered away. You're using the oversampling wrong if you have a millisecond duration zero volt output.
Reply by ●August 11, 20222022-08-11
On Thu, 11 Aug 2022 22:53:41 GMT, Glen Walpert <nospam@null.void> wrote:>On Thu, 11 Aug 2022 15:08:28 -0700, John Larkin wrote: > >> On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen >> <langwadt@fonz.dk> wrote: >> >>>torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky: >>>> On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk >>>> wrote: >>>> > torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky: >>>> > > On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, >>>> > > upsid...@downunder.com wrote: >>>> > > > On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky >>>> > > > <gnuarm.del...@gmail.com> wrote: >>>> > > > >On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin >>>> > > > >wrote: >>>> > > > >> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd >>>> > > > >> <whi...@gmail.com> wrote: >>>> > > > >> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin >>>> > > > >> >wrote: >>>> > > > >> > >>>> > > > >> >> My question was, why make a sine wave if the final result >>>> > > > >> >> is a digital clock? >>>> > > > >> > >>>> > > > >> >Do you want the digital clock edges to be synchronous with >>>> > > > >> >an existing source, or asynchronous? Mathematically, the >>>> > > > >> >creation of an asynchronous clock is not gonna happen in >>>> > > > >> >clocked logic circuitry, it has to have an analog component. >>>> > > > >> Of course. The analog components are dac, filter, comparator. >>>> > > > >> >>>> > > > >> I want a programmable internal trigger rate for a pulse >>>> > > > >> generator. >>>> > > > >> >>>> > > > >> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for >>>> > > > >> arbitrary N, >>>> > > > >> up to Nyquist. But it gets messy at low frequencies where the >>>> > > > >> dac is incremented infrequently and the filter doesn't do >>>> > > > >> much. >>>> > > > > >>>> > > > >Sounds like an application for dithering. >>>> > > > >>>> > > > Do you even need explicit dithering ? >>>> > > > >>>> > > > The DAC output has some wide band (thermal) white noise. If the >>>> > > > wide noise power is close to the LSB size, do you need >>>> > > > additional dithering?. At low frequencies, there is also the 1/f >>>> > > > noise. >>>> > > > >>>> > > > For audio frequencies "24 bit" 192 kHz DACs are available, which >>>> > > > accepts 24 bit sample values, but in practice the last few LSB >>>> > > > bits are buried in noise. >>>> > > > >>>> > > > If you need better dither control, some DDS chips have phase >>>> > > > and/or amplitude modulators built in, so the PM/AM inputs can be >>>> > > > used to control the high frequency dither more precisely. >>>> > > larkin is concerned about what amounts to dead band in the input >>>> > > to the DAC. I believe he is talking about much higher sample rates >>>> > > than what you can get in audio DACs. He wants to program clock >>>> > > rates over a very wide range. Otherwise, none of this is a >>>> > > problem. It's also not a problem if multiple filters are switched >>>> > > depending on the frequency of the output clock. >>>> > > >>>> > > He's already talked about using octave dividers to slow the clock. >>>> > > He is trying to view the problem from a very different perspective >>>> > > to see if he can gain some insight rather than using the standard, >>>> > > well defined approach. From what I've read, if he is looking for >>>> > > minimum jitter, there's nothing better than optimizing the length >>>> > > of the phase counter, then using any of various means for >>>> > > generating a sine waveform with high resolution, then rounding to >>>> > > the data width of your DAC. If the clipping/rounding is done at >>>> > > the phase word, it introduces close in spurs that can not be >>>> > > effectively filtered out. The spurs introduced by rounding or >>>> > > truncation of the sine data, tend to be harmonically related to >>>> > > the fundamental, and so are much easier to filter. >>>> > > >>>> > > The rocket science of NCO/DDS has already been researched and it >>>> > > is now more of a cookbook matter, other than the details of >>>> > > implementing the hardware, which has lots of analog gotchas. >>>> > > >>>> > > I've never looked at the idea of using dither on the digital sine >>>> > > values, but it might have some utility in this case. I think the >>>> > > best solution, though, and certainly more likely to produce a good >>>> > > result, is to implement different low pass filters for the >>>> > > different ranges of clock output rates. >>>> > > >>>> > > Don't you agree? >>>> > afaict we are talking about making a square wave from the DDS >>>> > output, so the issues is if you have, say just as an example, 1mV of >>>> > noise on where there comparator switches. The slow slewrate of a >>>> > sinewave going through that 1mV can cause more just jitter on the >>>> > resulting squarewave than just hammering through that 1mV window >>>> > with some waveform with a high slewrate >>>> And your point is? >>>> >>>> If larkin is talking about producing a square or "trapezoidal" wave >>>> from the NCO and skipping the filter, that's fine. He will get a >>>> jitter of one clock period. Adding a filter will do little to clean up >>>> jitter in the square wave and will slow the edge rate to create the >>>> noise sensitivity problem again. If the requirements allow this much >>>> jitter, then there was no need for all the fuss in the first place. If >>>> he needs low ps level jitter, then he has to mitigate the close in >>>> spurs created by the NCO truncation. >>>> >>>> Maybe I shouldn't say that. The close in spurs are from phase >>>> truncation, but maybe they only appear when running that through the >>>> sine wave generator. If you skip the sine generation, perhaps that >>>> doesn't produce the unfilterable spurs. I'm not betting on it. >>>> >>>> >>>you are missing the point. Imagine you have a perfect DDS and filter >>>combo that makes an absolutely perfect 2Vpp 1Hz sine you want to turn >>>that into a square wave so you stick it into a comparator. >>> >>>The comparator isn't perfect, the thresh hold varies by, lets say 1uV >>>just to pick a number, due to noise etc. >>>At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s so 1uV tresh >>>hold variation turns into a ~16us timing variation >>> >>>ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes >>>628V/s, the DAC can't make 200V so we'll chop the peaks off since we are >>>only interested in the zero crossing so 1uV tresh hold variation is now >>>only a ~160ns timing variation >> >> Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC will >> change about every millisecond. And theoretically one step parks at zero >> volts. So jitter is bad. Gain doesn't improve things. > >So if I have this right the DDS has lowest jitter at high frequencies and >a digital clock will have lowest jitter at low frequencies, where you can >calculate the optimal crossover frequency between the two for lowest >jitter across a wide range, and you want to use the phase accumulator? of >the DDS as your digital clock at lower frequencies, allowing for fast >synchronized transition between the two? Been a long time since I used a >DDS, not at all clear on the details, but is this basically what you are >trying to do? > >GlenThat's about right. At high frequencies, synthesize a waveform (usually a sine) and lowpass filter it into a comparator. At low frequencies, just use the MSB of the phase accumulator as the clock. I think a glitchless transition can be made between those two modes. And next step, do something trickier between the phase accumulator and the DAC, trapezoid maybe at a high DAC clock rate where the filter still helps. -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
Reply by ●August 11, 20222022-08-11
On Thu, 11 Aug 2022 16:02:42 -0700 (PDT), whit3rd <whit3rd@gmail.com> wrote:>On Thursday, August 11, 2022 at 3:08:46 PM UTC-7, John Larkin wrote: >> On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen >> <lang...@fonz.dk> wrote: > >> >ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop >> >the peaks off since we are only interested in the zero crossing >> >so 1uV tresh hold variation is now only a ~160ns timing variation > >> Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC >> will change about every millisecond. And theoretically one step parks >> at zero volts. So jitter is bad. Gain doesn't improve things. > >Oh, if your goal is to clock logic, gain certainly DOES improve things; you want >the fast rise. And, 'one step' is exactly what the filter doesn't pass; your DAC is clocked >at sub-microsecond intervals complete with some dither, and the microsecond-steps are >filtered away. You're using the oversampling wrong if you have a millisecond duration zero >volt output.A comparator makes a fast rise. The problem is at the DAC output. Dithering sounds like a jitter generator. I'd rather put some clever waveform into the DAC. -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
Reply by ●August 11, 20222022-08-11
On Thu, 11 Aug 2022 19:00:28 -0000 (UTC), Mike Monett <spamme@not.com> wrote:>whit3rd <whit3rd@gmail.com> wrote: > >> On Thursday, August 11, 2022 at 8:54:36 AM UTC-7, John Larkin wrote: >>> On Thu, 11 Aug 2022 16:51:33 +0200, Klaus Vestergaard Kragelund >>> <klau...@hotmail.com> wrote: >> >>> >A precision clock, high frequency low jitter >>> > >>> >Feeding into the FPGA with say 64bit counter, adding delay line for sub >>> >clock cycle accuracy >>> > >>> >Compare and lookup on that counter, coupled to the delay line also >>> > >>> >Like standard PWM done in microcontroller timer >>> > >>> >Programming is cycle to cycle, changing just the compare capture word >> >>> That architecture works in theory, and the math isn't bad to do >>> on-the-fly in an FPGA. One practical difficulty is building an >>> instantly-programmable glitch-free delay line. >> >> Or, just fine-tune a cavity oscillator by moving a wall, trombone-style. >> You get continuous frequency control, but it does need a moving part. >> Next step up from that, is a YIG system tuned with magnetic field. > >Yig's are great, but you have to stabilize the current.It sounds messy to get extreme mag field stability. And a yig won't go down to 1 Hz. -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
Reply by ●August 11, 20222022-08-11
On Friday, August 12, 2022 at 1:54:36 AM UTC+10, John Larkin wrote:> On Thu, 11 Aug 2022 16:51:33 +0200, Klaus Vestergaard Kragelund > <klau...@hotmail.com> wrote: > > >On 11/08/2022 16.35, John Larkin wrote: > >> On Thu, 11 Aug 2022 10:13:10 +0200, Klaus Vestergaard Kragelund > >> <klau...@hotmail.com> wrote: > >> > >>> On 10/08/2022 16.47, John Larkin wrote: > >>>> On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown > >>>> <'''newspam'''@nonad.co.uk> wrote: > >>>> > >>>>> On 08/08/2022 21:17, Ricky wrote: > >>>>>> On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: > >>>>>>> sųndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin: > >>>>>>>> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen > >>>>>>>> <lang...@fonz.dk> wrote: > >>>>>>>>> s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: > >>>>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> > >>>>>>>>>> wrote: > >>>>>>>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: > >>>>>>>>>>> > >>>>>>>>>>>> My question was, why make a sine wave if the final result is a digital > >>>>>>>>>>>> clock? > >>>>>>>>>>> > >>>>>>>>>>> Do you want the digital clock edges to be synchronous with an existing source, or > >>>>>>>>>>> asynchronous? Mathematically, the creation of an asynchronous clock is > >>>>>>>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component. > >>>>>>>>>> Of course. The analog components are dac, filter, comparator. > >>>>>>>>>> > >>>>>>>>>> I want a programmable internal trigger rate for a pulse generator. > >>>>>>>>>> > >>>>>>>>>> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, > >>>>>>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is > >>>>>>>>>> incremented infrequently and the filter doesn't do much. > >>>>>>>>> > >>>>>>>>> if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff > >>>>>>>>> > >>>>>>>> That has problems too. > >>>>>>>> > >>>>>>>> We were thinking that you could gain-up and clip the sine wave to > >>>>>>>> increase the zero-cross slope. The logical end of that is to make a > >>>>>>>> trapezoid with a steep rise. > >>>>>>> keep decreasing the rise time and you get back to a squarewave > >>>>>>> a sine is probably some kind of optimum > >>>>>> > >>>>>> It is an optimum in that it is most easily filtered to give lowest jitter. > >>>>>> > >>>>>> > >>>>>>>> The DAC lsb increments rarely at low frequencies, so magically include > >>>>>>>> some lower phase accumulator bits to effectively increase the DAC > >>>>>>>> sample rate on that steep slope. Digitally interpolate. > >>>>>>> but if the DAC can't run any faster or have any more bits, how? > >>>>>> > >>>>>> He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to. > >>>>> > >>>>> If he wants to waste his time on this after ignoring all the good advice > >>>>> so far then one of the cheap and nasty Chinese DDS signal generators > >>>>> that has a user defined waveform lookup table would be the way to go. > >>>> > >>>> Thinking about possibilities is never a waste of time. It may lead to > >>>> something useful now or later, and thinking is good exercise for > >>>> thinking. > >>>> > >>>> Try it. > >>>> > >>>>> > >>>>> Nothing refutes a daft idea so effectively as practical experiment. > >>>> > >>>> The idea shooters here don't need experiments, when insults are > >>>> easier. > >>>> > >>>>> > >>>>> Not knowing exactly why he really wants to do this - the simplest > >>>>> waveforms that are steeper at the origin than sin(x) and matched in > >>>>> gradient at zero crossing are parabolic or more generally of the form > >>>>> > >>>>> (1- (|x/pi-1/2|)^N) > >>>>> > >>>>> (and that function negated that on alternate half cycles) > >>>>> > >>>>> NB gradient of his triangle wave is 1 (or -1) everywhere but the > >>>>> gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). > >>>>> There is a very good reason why people generate sine waves by default. > >>>>> > >>>>> I suppose triangle wave and diode shaping to a sine wave would be an > >>>>> option (HP once used it to very good effect and their patent for that > >>>>> network has probably long since expired by now). ICL8038 did a crude > >>>>> imitation of the same trick in their monolithic function generator chip. > >>>>>> > >>>>>> In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the sine value/DAC resolution. > >>>>>> > >>>>>> Anyone who wishes to research DDS design will find this. > >>>>> > >>>>> The low pass filter needs to be frequency matched to the artefacts in > >>>>> the fundamental frequency being generated. No point in low pass > >>>>> filtering at 1MHz when the output is 10Hz. You need to attenuate the > >>>>> harmonics generated by the discrete steps in the DAC waveform. > >>>> > >>>> And one has to do something about the fact that the DAC code will > >>>> increment infrequently at 1 Hz. That is a time-domain concept. > >>>> > >>>> I suggested digitally shaping the DAC waveform to increase the sample > >>>> rate and slope at low frequencies. Or at all frequencies. > >>>> Interpolation is one approach. > >>>> > >>>> New idea: at some low frequency, just banging the dac rail-to-rail > >>>> with the phase accumulator MSB will make less jitter than stubbornly > >>>> insisting on making a slow sine into the filter+comparator. At high > >>>> frequencies, the unfiltered MSB is a horror. > >>>> > >>>> That idea has interesting offshoots. > >>> > >>> I am late into this discussion, so maybe missing something. The aim is > >>> to generate a programmed clock. Why not ditch the DDS and use a > >>> precision clock into a FPGA that digitally generates the clock > >> > >> How would that work? > >> > >>> > > > >A precision clock, high frequency low jitter > > > >Feeding into the FPGA with say 64bit counter, adding delay line for sub > >clock cycle accuracy > > > >Compare and lookup on that counter, coupled to the delay line also > > > >Like standard PWM done in microcontroller timer > > > >Programming is cycle to cycle, changing just the compare capture word > That architecture works in theory, and the math isn't bad to do > on-the-fly in an FPGA. One practical difficulty is building an > instantly-programmable glitch-free delay line.Been done. https://www.onsemi.com/pdf/datasheet/mc100ep195-d.pdf The 100ep196 has a fine-tune option built in. How fast and accurately you can change the 0 to 60psec continuously variable extra delay isn't specificied https://www.onsemi.com/pdf/datasheet/mc100ep196-d.pdf The actual delays are slightly temperature dependent, so you either have to thermostat the part or use to two of them and spend half your time measuring what what is actually doing - which needn't take long - while the other is doing the job. I figured on generating a pulse-width-modulated waveform and digiitising the average DC level with a fast ADC.> A second problem is that any output from an FPGA has picoseconds of excess jitter.So resynchronise it it a good clock. -- Bill Sloman, Sydney
Reply by ●August 11, 20222022-08-11
On Friday, August 12, 2022 at 9:40:02 AM UTC+10, John Larkin wrote:> On Thu, 11 Aug 2022 19:00:28 -0000 (UTC), Mike Monett <spa...@not.com> > wrote: > >whit3rd <whi...@gmail.com> wrote: > > > >> On Thursday, August 11, 2022 at 8:54:36 AM UTC-7, John Larkin wrote: > >>> On Thu, 11 Aug 2022 16:51:33 +0200, Klaus Vestergaard Kragelund > >>> <klau...@hotmail.com> wrote: > >> > >>> >A precision clock, high frequency low jitter > >>> > > >>> >Feeding into the FPGA with say 64bit counter, adding delay line for sub > >>> >clock cycle accuracy > >>> > > >>> >Compare and lookup on that counter, coupled to the delay line also > >>> > > >>> >Like standard PWM done in microcontroller timer > >>> > > >>> >Programming is cycle to cycle, changing just the compare capture word > >> > >>> That architecture works in theory, and the math isn't bad to do > >>> on-the-fly in an FPGA. One practical difficulty is building an > >>> instantly-programmable glitch-free delay line. > >> > >> Or, just fine-tune a cavity oscillator by moving a wall, trombone-style. > >> You get continuous frequency control, but it does need a moving part. > >> Next step up from that, is a YIG system tuned with magnetic field. > > > >Yig's are great, but you have to stabilize the current. > It sounds messy to get extreme mag field stability. And a yig won't go > down to 1 Hz.It doesn't have to. If you can tune the YIG oscillator over a continuous 2:1 range , a binary divider can get you almost literally any lower frequency - a thirty stage divider get you close to 1Hz. And the YIG oscillation frequency is a pretty accurate guide to the magnetic field - monitor that for feedback control of the magnetic field. -- Bill Sloman, Sydney
Reply by ●August 12, 20222022-08-12
On 11/08/2022 23:08, John Larkin wrote:> On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > >> torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky: >>> On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote: >>>> torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky: >>>>> On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote: >>>>>> On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky >>>>>> <gnuarm.del...@gmail.com> wrote: >>>>>>> On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: >>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>>> wrote: >>>>>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>> >>>>>>>>>> My question was, why make a sine wave if the final result is a digital >>>>>>>>>> clock? >>>>>>>>> >>>>>>>>> Do you want the digital clock edges to be synchronous with an existing source, or >>>>>>>>> asynchronous? Mathematically, the creation of an asynchronous clock is >>>>>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component. >>>>>>>> Of course. The analog components are dac, filter, comparator. >>>>>>>> >>>>>>>> I want a programmable internal trigger rate for a pulse generator. >>>>>>>> >>>>>>>> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>>> incremented infrequently and the filter doesn't do much. >>>>>>> >>>>>>> Sounds like an application for dithering. >>>>>> >>>>>> Do you even need explicit dithering ? >>>>>> >>>>>> The DAC output has some wide band (thermal) white noise. If the wide >>>>>> noise power is close to the LSB size, do you need additional >>>>>> dithering?. At low frequencies, there is also the 1/f noise. >>>>>> >>>>>> For audio frequencies "24 bit" 192 kHz DACs are available, which >>>>>> accepts 24 bit sample values, but in practice the last few LSB bits >>>>>> are buried in noise. >>>>>> >>>>>> If you need better dither control, some DDS chips have phase and/or >>>>>> amplitude modulators built in, so the PM/AM inputs can be used to >>>>>> control the high frequency dither more precisely. >>>>> larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock. >>>>> >>>>> He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to filter. >>>>> >>>>> The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas. >>>>> >>>>> I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for the different ranges of clock output rates. >>>>> >>>>> Don't you agree? >>>> afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate >>> And your point is? >>> >>> If larkin is talking about producing a square or "trapezoidal" wave from the NCO and skipping the filter, that's fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the NCO truncation. >>> >>> Maybe I shouldn't say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn't produce the unfilterable spurs. I'm not betting on it. >>> >> >> you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine >> you want to turn that into a square wave so you stick it into a comparator. >> >> The comparator isn't perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc. >> At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s >> so 1uV tresh hold variation turns into a ~16us timing variation >> >> ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop >> the peaks off since we are only interested in the zero crossing >> so 1uV tresh hold variation is now only a ~160ns timing variation > > Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC > will change about every millisecond. And theoretically one step parks > at zero volts. So jitter is bad. Gain doesn't improve things.Although that is true if you set your zero crossing high/low by half a least significant bit (or half the smallest step in the sine wave table) then you can trade lower jitter for a small asymmetry in the waveform. Then divide by two in the digital domain and you are done. The other option is to integrate the output of the DAC so that you get a join the dots piecewise linear waveform much more amenable to comparator thresholding and interpolation in the time domain. But then you have new problems - drift/offsets in the integrator, variable gain and delay offset as the frequency changes. There is no free lunch! -- Regards, Martin Brown
Reply by ●August 12, 20222022-08-12
On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky <gnuarm.deletethisbit@gmail.com> wrote:>On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote: >> On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky >> <gnuarm.del...@gmail.com> wrote: >> >On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: >> >> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >> >> wrote: >> >> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >> >> > >> >> >> My question was, why make a sine wave if the final result is a digital >> >> >> clock? >> >> > >> >> >Do you want the digital clock edges to be synchronous with an existing source, or >> >> >asynchronous? Mathematically, the creation of an asynchronous clock is >> >> >not gonna happen in clocked logic circuitry, it has to have an analog component. >> >> Of course. The analog components are dac, filter, comparator. >> >> >> >> I want a programmable internal trigger rate for a pulse generator. >> >> >> >> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >> >> up to Nyquist. But it gets messy at low frequencies where the dac is >> >> incremented infrequently and the filter doesn't do much. >> > >> >Sounds like an application for dithering. >> >> Do you even need explicit dithering ? >> >> The DAC output has some wide band (thermal) white noise. If the wide >> noise power is close to the LSB size, do you need additional >> dithering?. At low frequencies, there is also the 1/f noise. >> >> For audio frequencies "24 bit" 192 kHz DACs are available, which >> accepts 24 bit sample values, but in practice the last few LSB bits >> are buried in noise. >> >> If you need better dither control, some DDS chips have phase and/or >> amplitude modulators built in, so the PM/AM inputs can be used to >> control the high frequency dither more precisely. > >larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock. > >He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach.If the purpose is to create a variable _timing_ generator (not just frequency generator), why mess with the DDS principle at all ? Using a divide-by-N counter clocked at say, 1 GHz, you can timing intervals in 1 ns steps. With a 48 bit synchronous down counter, you can get timing intervals of several days with 1 ns timing steps. Some trickery is needed to avoid running all 48 stages at full ECL speed. But the real question is, do you really need nanosecond step size in minutes, hours or day time scale ? Admittedly, the 1 ns timing step is quite coarse at short pulses, inn which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS might be justified to get 1 ps timing steps. But for longer times, say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider after the DDS ? Combining the DDS and divide-by-N programming, quite strange periods can be obtained.
