On Wed, 10 Aug 2022 15:03:20 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>onsdag den 10. august 2022 kl. 23.15.59 UTC+2 skrev John Larkin: >> On Wed, 10 Aug 2022 13:22:13 -0700 (PDT), Lasse Langwadt Christensen >> <lang...@fonz.dk> wrote: >> >> >onsdag den 10. august 2022 kl. 16.47.20 UTC+2 skrev John Larkin: >> >> >> >> New idea: at some low frequency, just banging the dac rail-to-rail >> >> with the phase accumulator MSB will make less jitter than stubbornly >> >> insisting on making a slow sine into the filter+comparator. At high >> >> frequencies, the unfiltered MSB is a horror. >> >> >> > >> >ahh now I see what are on about, at very low frequencies >> >the fixed jitter of a Fclk cycle could be better than >> >a comparator trying to digitize a (noisy) slow rising sine >> > >> >maybe a frequency dependent gain and clamp to maintain a constant slew-rate could work >> The MSB of the phase accumulator has jitter of one clock p-p. The RMS >> jitter of that is 1 clock period / sqrt(12). That could be a few ns >> RMS jitter at mHz frequencies. >> >> I was just thinking about possible tricks to reduce DDS period jitter >> at low frequencies, without the obvious post-comparator divisor. > >The sine and filter does that. Draw a line between the data points and see >that the zero crossing doesn't fall on a clock edgeObviously, the filter is there to interpolate between DAC clocks. But it doesn't at low frequencies. At, say, 1 Hz, the dac increments infrequently and comparator noise becomes a serious jitter source. Even comparators have 1/f noise.> >but it might help to gain up the sine to increase the slew rate so it doesn't >hang around the comparator threshold forever, when all it has to do is delay >a variable +/-1 cycleOr maybe something even better. -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
DDS questions
Started by ●August 7, 2022
Reply by ●August 10, 20222022-08-10
Reply by ●August 10, 20222022-08-10
On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:> On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky > <gnuarm.del...@gmail.com> wrote: > >On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: > >> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> > >> wrote: > >> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: > >> > > >> >> My question was, why make a sine wave if the final result is a digital > >> >> clock? > >> > > >> >Do you want the digital clock edges to be synchronous with an existing source, or > >> >asynchronous? Mathematically, the creation of an asynchronous clock is > >> >not gonna happen in clocked logic circuitry, it has to have an analog component. > >> Of course. The analog components are dac, filter, comparator. > >> > >> I want a programmable internal trigger rate for a pulse generator. > >> > >> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, > >> up to Nyquist. But it gets messy at low frequencies where the dac is > >> incremented infrequently and the filter doesn't do much. > > > >Sounds like an application for dithering. > > Do you even need explicit dithering ? > > The DAC output has some wide band (thermal) white noise. If the wide > noise power is close to the LSB size, do you need additional > dithering?. At low frequencies, there is also the 1/f noise. > > For audio frequencies "24 bit" 192 kHz DACs are available, which > accepts 24 bit sample values, but in practice the last few LSB bits > are buried in noise. > > If you need better dither control, some DDS chips have phase and/or > amplitude modulators built in, so the PM/AM inputs can be used to > control the high frequency dither more precisely.larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock. He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to filter. The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas. I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for the different ranges of clock output rates. Don't you agree? -- Rick C. -+- Get 1,000 miles of free Supercharging -+- Tesla referral code - https://ts.la/richard11209
Reply by ●August 10, 20222022-08-10
torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:> On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote: > > On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky > > <gnuarm.del...@gmail.com> wrote: > > >On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: > > >> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> > > >> wrote: > > >> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: > > >> > > > >> >> My question was, why make a sine wave if the final result is a digital > > >> >> clock? > > >> > > > >> >Do you want the digital clock edges to be synchronous with an existing source, or > > >> >asynchronous? Mathematically, the creation of an asynchronous clock is > > >> >not gonna happen in clocked logic circuitry, it has to have an analog component. > > >> Of course. The analog components are dac, filter, comparator. > > >> > > >> I want a programmable internal trigger rate for a pulse generator. > > >> > > >> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, > > >> up to Nyquist. But it gets messy at low frequencies where the dac is > > >> incremented infrequently and the filter doesn't do much. > > > > > >Sounds like an application for dithering. > > > > Do you even need explicit dithering ? > > > > The DAC output has some wide band (thermal) white noise. If the wide > > noise power is close to the LSB size, do you need additional > > dithering?. At low frequencies, there is also the 1/f noise. > > > > For audio frequencies "24 bit" 192 kHz DACs are available, which > > accepts 24 bit sample values, but in practice the last few LSB bits > > are buried in noise. > > > > If you need better dither control, some DDS chips have phase and/or > > amplitude modulators built in, so the PM/AM inputs can be used to > > control the high frequency dither more precisely. > larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock. > > He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to filter. > > The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas. > > I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for the different ranges of clock output rates. > > Don't you agree?afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate
Reply by ●August 10, 20222022-08-10
On 8/7/2022 1:53 PM, John Larkin wrote:> On Sun, 7 Aug 2022 10:11:44 -0700 (PDT), whit3rd <whit3rd@gmail.com> > wrote: > >> On Sunday, August 7, 2022 at 9:08:13 AM UTC-7, John Larkin wrote: >>> On Sun, 7 Aug 2022 08:23:49 -0700 (PDT), whit3rd <whi...@gmail.com> >>> wrote: >>>> On Sunday, August 7, 2022 at 6:55:32 AM UTC-7, John Larkin wrote: >>>>> To make a programmable-frequency clock, the usual DDS chip has >> ... >>>>> M most-significant bits of that goes into a sine lookup table >> >>>> The sine lookup minimizes the difference function, which is the target of >>>> the (analog) lowpass filter. That makes it a kind of digital filter doing the >>>> bulk of the work. >> >>> The positive zero crossing of a sine wave and a triangle look a lot >>> alike, a straight line within the attention span of the lowpass >>> filter. It can't remember enough long-ago to tell the difference. >> >> But one wouldn't use the zero crossing (adds voltage offset error >> to the timing signal) when a trangle wave has a nice crisp >> cusp to define a timing. > > The point of the DDS lowpass filter is to interpolate multiple samples > and reduce jitter. If we use sharp edges on the waveform, the filter > just delays but doesn't reduce jitter. May as well use the phase > accumulator MSB. > > A sawtooth has a nice long straight line rising edge. The filter will > love that. > > > >>> >>> We don't push the Nyquist rate, which needs an ideal lowpass filter. >>> In fact, the sawtooth looks better to me... there is more linear >>> history before the zero cross than a sine. >> >>>> Other than synchronization possibilities, the triangle-wave basis hasn't an >>>> advantage to speak of. >> >>> No sine lookup table and no error contributions from that. >> >> But, the triangle wave, for a given amplitude, has lower slew rate (lower >> V signal at delta-T from the zero) than a sine wave. So, lower signal/noise. >> > > If D MSBs of the phase accumulator are pushed into the DAC, we get a > sawtooth that goes rail-to-rail in one DDS cycle. Nice. We conjecture > that some digital tricks could do even better, make a steeper > waveform, especially at low frequencies. > >>> It's a clock. We don't want to filter out harmonics. Who designs >>> digital clocks with low harmonic content? >> >> A 'digital clock' would usually be square-wave, neither triangle or sine. > > Exactly. Synchronous harmonics add no period jitter. But we want to > make the square clock *after* the analog filter does its Shannon > thing.The sawtooth defined by the MSBs of the phase accumulator isn't intrinsically band-limited but you know you can generate band-limited sawtooths directly in software, yeah? You just integrate a band-limited impulse train. see e.g. <https://www.dafx.de/paper-archive/2008/papers/dafx08_05.pdf>
Reply by ●August 11, 20222022-08-11
On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote:> torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky: > > On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote: > > > On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky > > > <gnuarm.del...@gmail.com> wrote: > > > >On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: > > > >> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> > > > >> wrote: > > > >> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: > > > >> > > > > >> >> My question was, why make a sine wave if the final result is a digital > > > >> >> clock? > > > >> > > > > >> >Do you want the digital clock edges to be synchronous with an existing source, or > > > >> >asynchronous? Mathematically, the creation of an asynchronous clock is > > > >> >not gonna happen in clocked logic circuitry, it has to have an analog component. > > > >> Of course. The analog components are dac, filter, comparator. > > > >> > > > >> I want a programmable internal trigger rate for a pulse generator. > > > >> > > > >> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, > > > >> up to Nyquist. But it gets messy at low frequencies where the dac is > > > >> incremented infrequently and the filter doesn't do much. > > > > > > > >Sounds like an application for dithering. > > > > > > Do you even need explicit dithering ? > > > > > > The DAC output has some wide band (thermal) white noise. If the wide > > > noise power is close to the LSB size, do you need additional > > > dithering?. At low frequencies, there is also the 1/f noise. > > > > > > For audio frequencies "24 bit" 192 kHz DACs are available, which > > > accepts 24 bit sample values, but in practice the last few LSB bits > > > are buried in noise. > > > > > > If you need better dither control, some DDS chips have phase and/or > > > amplitude modulators built in, so the PM/AM inputs can be used to > > > control the high frequency dither more precisely. > > larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock. > > > > He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to filter. > > > > The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas. > > > > I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for the different ranges of clock output rates. > > > > Don't you agree? > afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrateAnd your point is? If larkin is talking about producing a square or "trapezoidal" wave from the NCO and skipping the filter, that's fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the NCO truncation. Maybe I shouldn't say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn't produce the unfilterable spurs. I'm not betting on it. -- Rick C. -++ Get 1,000 miles of free Supercharging -++ Tesla referral code - https://ts.la/richard11209
Reply by ●August 11, 20222022-08-11
On 10/08/2022 16.47, John Larkin wrote:> On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown > <'''newspam'''@nonad.co.uk> wrote: > >> On 08/08/2022 21:17, Ricky wrote: >>> On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: >>>> søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin: >>>>> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen >>>>> <lang...@fonz.dk> wrote: >>>>>> s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>> wrote: >>>>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>> >>>>>>>>> My question was, why make a sine wave if the final result is a digital >>>>>>>>> clock? >>>>>>>> >>>>>>>> Do you want the digital clock edges to be synchronous with an existing source, or >>>>>>>> asynchronous? Mathematically, the creation of an asynchronous clock is >>>>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component. >>>>>>> Of course. The analog components are dac, filter, comparator. >>>>>>> >>>>>>> I want a programmable internal trigger rate for a pulse generator. >>>>>>> >>>>>>> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>> incremented infrequently and the filter doesn't do much. >>>>>> >>>>>> if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff >>>>>> >>>>> That has problems too. >>>>> >>>>> We were thinking that you could gain-up and clip the sine wave to >>>>> increase the zero-cross slope. The logical end of that is to make a >>>>> trapezoid with a steep rise. >>>> keep decreasing the rise time and you get back to a squarewave >>>> a sine is probably some kind of optimum >>> >>> It is an optimum in that it is most easily filtered to give lowest jitter. >>> >>> >>>>> The DAC lsb increments rarely at low frequencies, so magically include >>>>> some lower phase accumulator bits to effectively increase the DAC >>>>> sample rate on that steep slope. Digitally interpolate. >>>> but if the DAC can't run any faster or have any more bits, how? >>> >>> He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to. >> >> If he wants to waste his time on this after ignoring all the good advice >> so far then one of the cheap and nasty Chinese DDS signal generators >> that has a user defined waveform lookup table would be the way to go. > > Thinking about possibilities is never a waste of time. It may lead to > something useful now or later, and thinking is good exercise for > thinking. > > Try it. > >> >> Nothing refutes a daft idea so effectively as practical experiment. > > The idea shooters here don't need experiments, when insults are > easier. > >> >> Not knowing exactly why he really wants to do this - the simplest >> waveforms that are steeper at the origin than sin(x) and matched in >> gradient at zero crossing are parabolic or more generally of the form >> >> (1- (|x/pi-1/2|)^N) >> >> (and that function negated that on alternate half cycles) >> >> NB gradient of his triangle wave is 1 (or -1) everywhere but the >> gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). >> There is a very good reason why people generate sine waves by default. >> >> I suppose triangle wave and diode shaping to a sine wave would be an >> option (HP once used it to very good effect and their patent for that >> network has probably long since expired by now). ICL8038 did a crude >> imitation of the same trick in their monolithic function generator chip. >>> >>> In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the sine value/DAC resolution. >>> >>> Anyone who wishes to research DDS design will find this. >> >> The low pass filter needs to be frequency matched to the artefacts in >> the fundamental frequency being generated. No point in low pass >> filtering at 1MHz when the output is 10Hz. You need to attenuate the >> harmonics generated by the discrete steps in the DAC waveform. > > And one has to do something about the fact that the DAC code will > increment infrequently at 1 Hz. That is a time-domain concept. > > I suggested digitally shaping the DAC waveform to increase the sample > rate and slope at low frequencies. Or at all frequencies. > Interpolation is one approach. > > New idea: at some low frequency, just banging the dac rail-to-rail > with the phase accumulator MSB will make less jitter than stubbornly > insisting on making a slow sine into the filter+comparator. At high > frequencies, the unfiltered MSB is a horror. > > That idea has interesting offshoots.I am late into this discussion, so maybe missing something. The aim is to generate a programmed clock. Why not ditch the DDS and use a precision clock into a FPGA that digitally generates the clock Maybe the FPGA has clock jitter, but isn't that as good as the DDS jitter?
Reply by ●August 11, 20222022-08-11
On Thursday, August 11, 2022 at 4:13:20 AM UTC-4, Klaus Kragelund wrote:> On 10/08/2022 16.47, John Larkin wrote: > > On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown > > <'''newspam'''@nonad.co.uk> wrote: > > > >> On 08/08/2022 21:17, Ricky wrote: > >>> On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: > >>>> søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin: > >>>>> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen > >>>>> <lang...@fonz.dk> wrote: > >>>>>> s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: > >>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> > >>>>>>> wrote: > >>>>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: > >>>>>>>> > >>>>>>>>> My question was, why make a sine wave if the final result is a digital > >>>>>>>>> clock? > >>>>>>>> > >>>>>>>> Do you want the digital clock edges to be synchronous with an existing source, or > >>>>>>>> asynchronous? Mathematically, the creation of an asynchronous clock is > >>>>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component. > >>>>>>> Of course. The analog components are dac, filter, comparator. > >>>>>>> > >>>>>>> I want a programmable internal trigger rate for a pulse generator. > >>>>>>> > >>>>>>> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, > >>>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is > >>>>>>> incremented infrequently and the filter doesn't do much. > >>>>>> > >>>>>> if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff > >>>>>> > >>>>> That has problems too. > >>>>> > >>>>> We were thinking that you could gain-up and clip the sine wave to > >>>>> increase the zero-cross slope. The logical end of that is to make a > >>>>> trapezoid with a steep rise. > >>>> keep decreasing the rise time and you get back to a squarewave > >>>> a sine is probably some kind of optimum > >>> > >>> It is an optimum in that it is most easily filtered to give lowest jitter. > >>> > >>> > >>>>> The DAC lsb increments rarely at low frequencies, so magically include > >>>>> some lower phase accumulator bits to effectively increase the DAC > >>>>> sample rate on that steep slope. Digitally interpolate. > >>>> but if the DAC can't run any faster or have any more bits, how? > >>> > >>> He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to. > >> > >> If he wants to waste his time on this after ignoring all the good advice > >> so far then one of the cheap and nasty Chinese DDS signal generators > >> that has a user defined waveform lookup table would be the way to go. > > > > Thinking about possibilities is never a waste of time. It may lead to > > something useful now or later, and thinking is good exercise for > > thinking. > > > > Try it. > > > >> > >> Nothing refutes a daft idea so effectively as practical experiment. > > > > The idea shooters here don't need experiments, when insults are > > easier. > > > >> > >> Not knowing exactly why he really wants to do this - the simplest > >> waveforms that are steeper at the origin than sin(x) and matched in > >> gradient at zero crossing are parabolic or more generally of the form > >> > >> (1- (|x/pi-1/2|)^N) > >> > >> (and that function negated that on alternate half cycles) > >> > >> NB gradient of his triangle wave is 1 (or -1) everywhere but the > >> gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). > >> There is a very good reason why people generate sine waves by default. > >> > >> I suppose triangle wave and diode shaping to a sine wave would be an > >> option (HP once used it to very good effect and their patent for that > >> network has probably long since expired by now). ICL8038 did a crude > >> imitation of the same trick in their monolithic function generator chip. > >>> > >>> In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the sine value/DAC resolution. > >>> > >>> Anyone who wishes to research DDS design will find this. > >> > >> The low pass filter needs to be frequency matched to the artefacts in > >> the fundamental frequency being generated. No point in low pass > >> filtering at 1MHz when the output is 10Hz. You need to attenuate the > >> harmonics generated by the discrete steps in the DAC waveform. > > > > And one has to do something about the fact that the DAC code will > > increment infrequently at 1 Hz. That is a time-domain concept. > > > > I suggested digitally shaping the DAC waveform to increase the sample > > rate and slope at low frequencies. Or at all frequencies. > > Interpolation is one approach. > > > > New idea: at some low frequency, just banging the dac rail-to-rail > > with the phase accumulator MSB will make less jitter than stubbornly > > insisting on making a slow sine into the filter+comparator. At high > > frequencies, the unfiltered MSB is a horror. > > > > That idea has interesting offshoots. > I am late into this discussion, so maybe missing something. The aim is > to generate a programmed clock. Why not ditch the DDS and use a > precision clock into a FPGA that digitally generates the clock > > Maybe the FPGA has clock jitter, but isn't that as good as the DDS jitter?The concept of the DDS is to generate a sine wave, which would have some artifacts which could be smoothed by filtering, then a comparator would produce the square wave clock from the sine. This would allow very high resolution of timing, much finer than a cycle of the sample rate clock of the DAC. However... when producing a sine wave that is much slower than the sample rate clock, the limited resolution of the sine value produces what is essentially a much slower sample rate and the filter doesn't work as well. This can be mitigated by using different filters to suit the output sine wave frequency. -- Rick C. +-- Get 1,000 miles of free Supercharging +-- Tesla referral code - https://ts.la/richard11209
Reply by ●August 11, 20222022-08-11
On Thursday, August 11, 2022 at 6:13:20 PM UTC+10, Klaus Kragelund wrote:> On 10/08/2022 16.47, John Larkin wrote: > > On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown > > <'''newspam'''@nonad.co.uk> wrote: > > > >> On 08/08/2022 21:17, Ricky wrote: > >>> On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: > >>>> søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin: > >>>>> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen > >>>>> <lang...@fonz.dk> wrote: > >>>>>> s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: > >>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> > >>>>>>> wrote: > >>>>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:<snip>> I am late into this discussion, so maybe missing something. The aim is > to generate a programmed clock. Why not ditch the DDS and use a > precision clock into a FPGA that digitally generates the clock > > Maybe the FPGA has clock jitter, but isn't that as good as the DDS jitter?I think the point is that John Larkin wants to generate an infinite number of arbitary frequencies, and can't afford to limit himself to dividing down even a very high frequency clock by a fixed divisor. A DDS offers the option of using a DAC to interpolate between fixed divisors. The DAC produces a stair-case waveform approximating to a sine wave, so you have to low pass filter the DAC output so that the zero-crossings do happen between clock edges to get the effect you want. John doesn't seem to have thought this through. -- Bill Sloman, Sydney
Reply by ●August 11, 20222022-08-11
On 11/08/2022 11.17, Ricky wrote:> On Thursday, August 11, 2022 at 4:13:20 AM UTC-4, Klaus Kragelund wrote: >> On 10/08/2022 16.47, John Larkin wrote: >>> On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown >>> <'''newspam'''@nonad.co.uk> wrote: >>> >>>> On 08/08/2022 21:17, Ricky wrote: >>>>> On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: >>>>>> søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin: >>>>>>> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen >>>>>>> <lang...@fonz.dk> wrote: >>>>>>>> s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>>>> wrote: >>>>>>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>>> >>>>>>>>>>> My question was, why make a sine wave if the final result is a digital >>>>>>>>>>> clock? >>>>>>>>>> >>>>>>>>>> Do you want the digital clock edges to be synchronous with an existing source, or >>>>>>>>>> asynchronous? Mathematically, the creation of an asynchronous clock is >>>>>>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component. >>>>>>>>> Of course. The analog components are dac, filter, comparator. >>>>>>>>> >>>>>>>>> I want a programmable internal trigger rate for a pulse generator. >>>>>>>>> >>>>>>>>> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>>>> incremented infrequently and the filter doesn't do much. >>>>>>>> >>>>>>>> if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff >>>>>>>> >>>>>>> That has problems too. >>>>>>> >>>>>>> We were thinking that you could gain-up and clip the sine wave to >>>>>>> increase the zero-cross slope. The logical end of that is to make a >>>>>>> trapezoid with a steep rise. >>>>>> keep decreasing the rise time and you get back to a squarewave >>>>>> a sine is probably some kind of optimum >>>>> >>>>> It is an optimum in that it is most easily filtered to give lowest jitter. >>>>> >>>>> >>>>>>> The DAC lsb increments rarely at low frequencies, so magically include >>>>>>> some lower phase accumulator bits to effectively increase the DAC >>>>>>> sample rate on that steep slope. Digitally interpolate. >>>>>> but if the DAC can't run any faster or have any more bits, how? >>>>> >>>>> He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to. >>>> >>>> If he wants to waste his time on this after ignoring all the good advice >>>> so far then one of the cheap and nasty Chinese DDS signal generators >>>> that has a user defined waveform lookup table would be the way to go. >>> >>> Thinking about possibilities is never a waste of time. It may lead to >>> something useful now or later, and thinking is good exercise for >>> thinking. >>> >>> Try it. >>> >>>> >>>> Nothing refutes a daft idea so effectively as practical experiment. >>> >>> The idea shooters here don't need experiments, when insults are >>> easier. >>> >>>> >>>> Not knowing exactly why he really wants to do this - the simplest >>>> waveforms that are steeper at the origin than sin(x) and matched in >>>> gradient at zero crossing are parabolic or more generally of the form >>>> >>>> (1- (|x/pi-1/2|)^N) >>>> >>>> (and that function negated that on alternate half cycles) >>>> >>>> NB gradient of his triangle wave is 1 (or -1) everywhere but the >>>> gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). >>>> There is a very good reason why people generate sine waves by default. >>>> >>>> I suppose triangle wave and diode shaping to a sine wave would be an >>>> option (HP once used it to very good effect and their patent for that >>>> network has probably long since expired by now). ICL8038 did a crude >>>> imitation of the same trick in their monolithic function generator chip. >>>>> >>>>> In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the sine value/DAC resolution. >>>>> >>>>> Anyone who wishes to research DDS design will find this. >>>> >>>> The low pass filter needs to be frequency matched to the artefacts in >>>> the fundamental frequency being generated. No point in low pass >>>> filtering at 1MHz when the output is 10Hz. You need to attenuate the >>>> harmonics generated by the discrete steps in the DAC waveform. >>> >>> And one has to do something about the fact that the DAC code will >>> increment infrequently at 1 Hz. That is a time-domain concept. >>> >>> I suggested digitally shaping the DAC waveform to increase the sample >>> rate and slope at low frequencies. Or at all frequencies. >>> Interpolation is one approach. >>> >>> New idea: at some low frequency, just banging the dac rail-to-rail >>> with the phase accumulator MSB will make less jitter than stubbornly >>> insisting on making a slow sine into the filter+comparator. At high >>> frequencies, the unfiltered MSB is a horror. >>> >>> That idea has interesting offshoots. >> I am late into this discussion, so maybe missing something. The aim is >> to generate a programmed clock. Why not ditch the DDS and use a >> precision clock into a FPGA that digitally generates the clock >> >> Maybe the FPGA has clock jitter, but isn't that as good as the DDS jitter? > > The concept of the DDS is to generate a sine wave, which would have some artifacts which could be smoothed by filtering, then a comparator would produce the square wave clock from the sine. This would allow very high resolution of timing, much finer than a cycle of the sample rate clock of the DAC. >Ok, makes good sense. Thanks for the explanation. One could use delaylines to get sub cycle resolution, but I guess he must have discarded that solution
Reply by ●August 11, 20222022-08-11
On Thu, 11 Aug 2022 10:13:10 +0200, Klaus Vestergaard Kragelund <klauskvik@hotmail.com> wrote:>On 10/08/2022 16.47, John Larkin wrote: >> On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown >> <'''newspam'''@nonad.co.uk> wrote: >> >>> On 08/08/2022 21:17, Ricky wrote: >>>> On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: >>>>> s�ndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin: >>>>>> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen >>>>>> <lang...@fonz.dk> wrote: >>>>>>> s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>>> wrote: >>>>>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>> >>>>>>>>>> My question was, why make a sine wave if the final result is a digital >>>>>>>>>> clock? >>>>>>>>> >>>>>>>>> Do you want the digital clock edges to be synchronous with an existing source, or >>>>>>>>> asynchronous? Mathematically, the creation of an asynchronous clock is >>>>>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component. >>>>>>>> Of course. The analog components are dac, filter, comparator. >>>>>>>> >>>>>>>> I want a programmable internal trigger rate for a pulse generator. >>>>>>>> >>>>>>>> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>>> incremented infrequently and the filter doesn't do much. >>>>>>> >>>>>>> if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff >>>>>>> >>>>>> That has problems too. >>>>>> >>>>>> We were thinking that you could gain-up and clip the sine wave to >>>>>> increase the zero-cross slope. The logical end of that is to make a >>>>>> trapezoid with a steep rise. >>>>> keep decreasing the rise time and you get back to a squarewave >>>>> a sine is probably some kind of optimum >>>> >>>> It is an optimum in that it is most easily filtered to give lowest jitter. >>>> >>>> >>>>>> The DAC lsb increments rarely at low frequencies, so magically include >>>>>> some lower phase accumulator bits to effectively increase the DAC >>>>>> sample rate on that steep slope. Digitally interpolate. >>>>> but if the DAC can't run any faster or have any more bits, how? >>>> >>>> He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to. >>> >>> If he wants to waste his time on this after ignoring all the good advice >>> so far then one of the cheap and nasty Chinese DDS signal generators >>> that has a user defined waveform lookup table would be the way to go. >> >> Thinking about possibilities is never a waste of time. It may lead to >> something useful now or later, and thinking is good exercise for >> thinking. >> >> Try it. >> >>> >>> Nothing refutes a daft idea so effectively as practical experiment. >> >> The idea shooters here don't need experiments, when insults are >> easier. >> >>> >>> Not knowing exactly why he really wants to do this - the simplest >>> waveforms that are steeper at the origin than sin(x) and matched in >>> gradient at zero crossing are parabolic or more generally of the form >>> >>> (1- (|x/pi-1/2|)^N) >>> >>> (and that function negated that on alternate half cycles) >>> >>> NB gradient of his triangle wave is 1 (or -1) everywhere but the >>> gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). >>> There is a very good reason why people generate sine waves by default. >>> >>> I suppose triangle wave and diode shaping to a sine wave would be an >>> option (HP once used it to very good effect and their patent for that >>> network has probably long since expired by now). ICL8038 did a crude >>> imitation of the same trick in their monolithic function generator chip. >>>> >>>> In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the sine value/DAC resolution. >>>> >>>> Anyone who wishes to research DDS design will find this. >>> >>> The low pass filter needs to be frequency matched to the artefacts in >>> the fundamental frequency being generated. No point in low pass >>> filtering at 1MHz when the output is 10Hz. You need to attenuate the >>> harmonics generated by the discrete steps in the DAC waveform. >> >> And one has to do something about the fact that the DAC code will >> increment infrequently at 1 Hz. That is a time-domain concept. >> >> I suggested digitally shaping the DAC waveform to increase the sample >> rate and slope at low frequencies. Or at all frequencies. >> Interpolation is one approach. >> >> New idea: at some low frequency, just banging the dac rail-to-rail >> with the phase accumulator MSB will make less jitter than stubbornly >> insisting on making a slow sine into the filter+comparator. At high >> frequencies, the unfiltered MSB is a horror. >> >> That idea has interesting offshoots. > >I am late into this discussion, so maybe missing something. The aim is >to generate a programmed clock. Why not ditch the DDS and use a >precision clock into a FPGA that digitally generates the clockHow would that work?> >Maybe the FPGA has clock jitter, but isn't that as good as the DDS jitter?We want a user to be able to program a trigger rate from 15 MHz down to milliHz with high resolution and low period jitter. 1 mHz resolution is a reasonable goal. We can do that on some instruments now, but 1. If we do classic DDS, phase accumulator and sine lookup table and DAC and lowpass filter and comparator, jitter is horrible at low frequencies. 2. If we synthesize an octave or so and divide down after the comparator, jitter is good but there can be ugly transients when the user changes frequency: the DDS and the divisor both need to be changed, and that's tricky using a commercial DDS chip that's slow to reprogram. Even the divisor is difficult if it's in an FPGA that has other stuff going on. Getting picosecond timing out of an FPGA has hazards, like crosstalk, ground bounce, and supply voltage sensitivity, which we measure in microvolts per picosecond. So, I'm thinking about DDS clock synthesis from basics, and particularly thinking in time domain. It's basically a time domain problem, so there's nothing magic about sine waves. This box does internal clock rate generation to mHz resolution, with an RF synthesizer (not a DDS) and post-dividers. http://www.highlandtechnology.com/DSS/P500DS.shtml but it takes a long time to reprogram the synth (lots of math) so we stop triggering while we reprogram. Some customers don't like that; their lasers blow up or something. -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
