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DDS questions

Started by John Larkin August 7, 2022
On Fri, 12 Aug 2022 08:20:50 +0100, Martin Brown
<'''newspam'''@nonad.co.uk> wrote:

>On 11/08/2022 23:08, John Larkin wrote: >> On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen >> <langwadt@fonz.dk> wrote: >> >>> torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky: >>>> On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote: >>>>> torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky: >>>>>> On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote: >>>>>>> On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky >>>>>>> <gnuarm.del...@gmail.com> wrote: >>>>>>>> On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: >>>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>>>> wrote: >>>>>>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>>> >>>>>>>>>>> My question was, why make a sine wave if the final result is a digital >>>>>>>>>>> clock? >>>>>>>>>> >>>>>>>>>> Do you want the digital clock edges to be synchronous with an existing source, or >>>>>>>>>> asynchronous? Mathematically, the creation of an asynchronous clock is >>>>>>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component. >>>>>>>>> Of course. The analog components are dac, filter, comparator. >>>>>>>>> >>>>>>>>> I want a programmable internal trigger rate for a pulse generator. >>>>>>>>> >>>>>>>>> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>>>> incremented infrequently and the filter doesn't do much. >>>>>>>> >>>>>>>> Sounds like an application for dithering. >>>>>>> >>>>>>> Do you even need explicit dithering ? >>>>>>> >>>>>>> The DAC output has some wide band (thermal) white noise. If the wide >>>>>>> noise power is close to the LSB size, do you need additional >>>>>>> dithering?. At low frequencies, there is also the 1/f noise. >>>>>>> >>>>>>> For audio frequencies "24 bit" 192 kHz DACs are available, which >>>>>>> accepts 24 bit sample values, but in practice the last few LSB bits >>>>>>> are buried in noise. >>>>>>> >>>>>>> If you need better dither control, some DDS chips have phase and/or >>>>>>> amplitude modulators built in, so the PM/AM inputs can be used to >>>>>>> control the high frequency dither more precisely. >>>>>> larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock. >>>>>> >>>>>> He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to filter. >>>>>> >>>>>> The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas. >>>>>> >>>>>> I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for the different ranges of clock output rates. >>>>>> >>>>>> Don't you agree? >>>>> afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate >>>> And your point is? >>>> >>>> If larkin is talking about producing a square or "trapezoidal" wave from the NCO and skipping the filter, that's fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the NCO truncation. >>>> >>>> Maybe I shouldn't say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn't produce the unfilterable spurs. I'm not betting on it. >>>> >>> >>> you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine >>> you want to turn that into a square wave so you stick it into a comparator. >>> >>> The comparator isn't perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc. >>> At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s >>> so 1uV tresh hold variation turns into a ~16us timing variation >>> >>> ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop >>> the peaks off since we are only interested in the zero crossing >>> so 1uV tresh hold variation is now only a ~160ns timing variation >> >> Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC >> will change about every millisecond. And theoretically one step parks >> at zero volts. So jitter is bad. Gain doesn't improve things. > >Although that is true if you set your zero crossing high/low by half a >least significant bit (or half the smallest step in the sine wave table) >then you can trade lower jitter for a small asymmetry in the waveform.
The DAC still increments once a millisecond.
> >Then divide by two in the digital domain and you are done. > >The other option is to integrate the output of the DAC so that you get a >join the dots piecewise linear waveform much more amenable to comparator >thresholding and interpolation in the time domain. > >But then you have new problems - drift/offsets in the integrator, >variable gain and delay offset as the frequency changes. > >There is no free lunch!
The option is to do digital tricks in the FPGA. Almost free lunch. I'm thinking that it's (barely) possible to simulate the DDS in LT Spice. The tricky part would then be measuring period jitter. -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
On Fri, 12 Aug 2022 16:54:04 +0300, upsidedown@downunder.com wrote:

>On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky ><gnuarm.deletethisbit@gmail.com> wrote: > >>On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote: >>> On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky >>> <gnuarm.del...@gmail.com> wrote: >>> >On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: >>> >> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>> >> wrote: >>> >> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>> >> > >>> >> >> My question was, why make a sine wave if the final result is a digital >>> >> >> clock? >>> >> > >>> >> >Do you want the digital clock edges to be synchronous with an existing source, or >>> >> >asynchronous? Mathematically, the creation of an asynchronous clock is >>> >> >not gonna happen in clocked logic circuitry, it has to have an analog component. >>> >> Of course. The analog components are dac, filter, comparator. >>> >> >>> >> I want a programmable internal trigger rate for a pulse generator. >>> >> >>> >> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>> >> up to Nyquist. But it gets messy at low frequencies where the dac is >>> >> incremented infrequently and the filter doesn't do much. >>> > >>> >Sounds like an application for dithering. >>> >>> Do you even need explicit dithering ? >>> >>> The DAC output has some wide band (thermal) white noise. If the wide >>> noise power is close to the LSB size, do you need additional >>> dithering?. At low frequencies, there is also the 1/f noise. >>> >>> For audio frequencies "24 bit" 192 kHz DACs are available, which >>> accepts 24 bit sample values, but in practice the last few LSB bits >>> are buried in noise. >>> >>> If you need better dither control, some DDS chips have phase and/or >>> amplitude modulators built in, so the PM/AM inputs can be used to >>> control the high frequency dither more precisely. >> >>larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock. >> >>He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. > >If the purpose is to create a variable _timing_ generator (not just >frequency generator), why mess with the DDS principle at all ?
Most of our customers expect to set an internal trigger frequency. There are times when setting it to high resolution is valuable.
> >Using a divide-by-N counter clocked at say, 1 GHz, you can timing >intervals in 1 ns steps. With a 48 bit synchronous down counter, you >can get timing intervals of several days with 1 ns timing steps. Some >trickery is needed to avoid running all 48 stages at full ECL speed.
I can't do that in an FPGA. And resolution is mediocre around 10 MHz. It might be interesting to program a 1 GHz SERDES channel (which we can do) DDS-sorta waveform that we can filter into a comparator. That's hard to think about, which I can delegate.
> >But the real question is, do you really need nanosecond step size in >minutes, hours or day time scale ?
A straightforward DDS will have tons of period jitter at low frequencies, which is ugly. And some customers whine if we stop triggering while we reprogram a DDS (or a synth chip) and a divisor.
> >Admittedly, the 1 ns timing step is quite coarse at short pulses, inn >which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS >might be justified to get 1 ps timing steps. But for longer times, >say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider >after the DDS ? Combining the DDS and divide-by-N programming, quite >strange periods can be obtained.
I'll ping the boys about the SERDES idea. That could be cool. -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
On Saturday, August 13, 2022 at 12:11:15 AM UTC+10, John Larkin wrote:
> On Fri, 12 Aug 2022 16:54:04 +0300, upsid...@downunder.com wrote: > >On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky <gnuarm.del...@gmail.com> wrote: > >>On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote: > >>> On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky <gnuarm.del...@gmail.com> wrote: > >>> >On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: > >>> >> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> wrote: > >>> >> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:
<snip>
> >Using a divide-by-N counter clocked at say, 1 GHz, you can timing > >intervals in 1 ns steps. With a 48 bit synchronous down counter, you > >can get timing intervals of several days with 1 ns timing steps. Some > >trickery is needed to avoid running all 48 stages at full ECL speed. > > I can't do that in an FPGA. And resolution is mediocre around 10 MHz.
Peter Alfke probably could have. Sadly, he is dead. https://www.eetimes.com/peter-alfke-remembered-1931-2011/ There are quite a lot of different sorts of FPGA's around, some of them quite quick
> It might be interesting to program a 1 GHz SERDES channel (which we > can do) DDS-sorta waveform that we can filter into a comparator. > That's hard to think about, which I can delegate. > > > >But the real question is, do you really need nanosecond step size in > >minutes, hours or day time scale? > > A straightforward DDS will have tons of period jitter at low frequencies, which is ugly.
So don't use a "straightforward DDS".
> And some customers whine if we stop triggering while we reprogram a DDS (or a synth chip) and a divisor.
So ping-pong between two.
> >Admittedly, the 1 ns timing step is quite coarse at short pulses, inn > >which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS > >might be justified to get 1 ps timing steps. But for longer times, > >say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider > >after the DDS ? Combining the DDS and divide-by-N programming, quite > >strange periods can be obtained. > > I'll ping the boys about the SERDES idea. That could be cool.
The last serial data link that I played with was the Taxichip back in 1988. It used an 8-bit to 10-bit recoding scheme to avoid sending troublesome bit patterns. Working out what you were actually sending might be a bit tedious. -- Bill Sloman, Sydney
upsidedown@downunder.com wrote:

[...]

> If the purpose is to create a variable _timing_ generator (not just > frequency generator), why mess with the DDS principle at all ? > > Using a divide-by-N counter clocked at say, 1 GHz, you can timing > intervals in 1 ns steps. With a 48 bit synchronous down counter, you > can get timing intervals of several days with 1 ns timing steps. Some > trickery is needed to avoid running all 48 stages at full ECL speed. > > But the real question is, do you really need nanosecond step size in > minutes, hours or day time scale ? > > Admittedly, the 1 ns timing step is quite coarse at short pulses, inn > which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS > might be justified to get 1 ps timing steps. But for longer times, > say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider > after the DDS ? Combining the DDS and divide-by-N programming, quite > strange periods can be obtained.
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On Friday, August 12, 2022 at 10:11:15 AM UTC-4, John Larkin wrote:
> On Fri, 12 Aug 2022 16:54:04 +0300, upsid...@downunder.com wrote: > > >On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky > ><gnuarm.del...@gmail.com> wrote: > > > >>On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote: > >>> On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky > >>> <gnuarm.del...@gmail.com> wrote: > >>> >On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: > >>> >> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> > >>> >> wrote: > >>> >> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: > >>> >> > > >>> >> >> My question was, why make a sine wave if the final result is a digital > >>> >> >> clock? > >>> >> > > >>> >> >Do you want the digital clock edges to be synchronous with an existing source, or > >>> >> >asynchronous? Mathematically, the creation of an asynchronous clock is > >>> >> >not gonna happen in clocked logic circuitry, it has to have an analog component. > >>> >> Of course. The analog components are dac, filter, comparator. > >>> >> > >>> >> I want a programmable internal trigger rate for a pulse generator. > >>> >> > >>> >> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, > >>> >> up to Nyquist. But it gets messy at low frequencies where the dac is > >>> >> incremented infrequently and the filter doesn't do much. > >>> > > >>> >Sounds like an application for dithering. > >>> > >>> Do you even need explicit dithering ? > >>> > >>> The DAC output has some wide band (thermal) white noise. If the wide > >>> noise power is close to the LSB size, do you need additional > >>> dithering?. At low frequencies, there is also the 1/f noise. > >>> > >>> For audio frequencies "24 bit" 192 kHz DACs are available, which > >>> accepts 24 bit sample values, but in practice the last few LSB bits > >>> are buried in noise. > >>> > >>> If you need better dither control, some DDS chips have phase and/or > >>> amplitude modulators built in, so the PM/AM inputs can be used to > >>> control the high frequency dither more precisely. > >> > >>larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock. > >> > >>He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. > > > >If the purpose is to create a variable _timing_ generator (not just > >frequency generator), why mess with the DDS principle at all ? > Most of our customers expect to set an internal trigger frequency. > There are times when setting it to high resolution is valuable. > > > >Using a divide-by-N counter clocked at say, 1 GHz, you can timing > >intervals in 1 ns steps. With a 48 bit synchronous down counter, you > >can get timing intervals of several days with 1 ns timing steps. Some > >trickery is needed to avoid running all 48 stages at full ECL speed. > I can't do that in an FPGA. And resolution is mediocre around 10 MHz. > > It might be interesting to program a 1 GHz SERDES channel (which we > can do) DDS-sorta waveform that we can filter into a comparator. > That's hard to think about, which I can delegate. > > > >But the real question is, do you really need nanosecond step size in > >minutes, hours or day time scale ? > A straightforward DDS will have tons of period jitter at low > frequencies, which is ugly. And some customers whine if we stop > triggering while we reprogram a DDS (or a synth chip) and a divisor. > > > >Admittedly, the 1 ns timing step is quite coarse at short pulses, inn > >which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS > >might be justified to get 1 ps timing steps. But for longer times, > >say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider > >after the DDS ? Combining the DDS and divide-by-N programming, quite > >strange periods can be obtained. > I'll ping the boys about the SERDES idea. That could be cool.
Cool, but it puts you right back at dealing with all the jitter issues of outputting the timing signal directly from the FPGA. -- Rick C. +++ Get 1,000 miles of free Supercharging +++ Tesla referral code - https://ts.la/richard11209
John Larkin wrote:
> On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > >> torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky: >>> On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote: >>>> torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky: >>>>> On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote: >>>>>> On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky >>>>>> <gnuarm.del...@gmail.com> wrote: >>>>>>> On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: >>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>>> wrote: >>>>>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>> >>>>>>>>>> My question was, why make a sine wave if the final result is a digital >>>>>>>>>> clock? >>>>>>>>> >>>>>>>>> Do you want the digital clock edges to be synchronous with an existing source, or >>>>>>>>> asynchronous? Mathematically, the creation of an asynchronous clock is >>>>>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component. >>>>>>>> Of course. The analog components are dac, filter, comparator. >>>>>>>> >>>>>>>> I want a programmable internal trigger rate for a pulse generator. >>>>>>>> >>>>>>>> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>>> incremented infrequently and the filter doesn't do much. >>>>>>> >>>>>>> Sounds like an application for dithering. >>>>>> >>>>>> Do you even need explicit dithering ? >>>>>> >>>>>> The DAC output has some wide band (thermal) white noise. If the wide >>>>>> noise power is close to the LSB size, do you need additional >>>>>> dithering?. At low frequencies, there is also the 1/f noise. >>>>>> >>>>>> For audio frequencies "24 bit" 192 kHz DACs are available, which >>>>>> accepts 24 bit sample values, but in practice the last few LSB bits >>>>>> are buried in noise. >>>>>> >>>>>> If you need better dither control, some DDS chips have phase and/or >>>>>> amplitude modulators built in, so the PM/AM inputs can be used to >>>>>> control the high frequency dither more precisely. >>>>> larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock. >>>>> >>>>> He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to filter. >>>>> >>>>> The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas. >>>>> >>>>> I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for the different ranges of clock output rates. >>>>> >>>>> Don't you agree? >>>> afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate >>> And your point is? >>> >>> If larkin is talking about producing a square or "trapezoidal" wave from the NCO and skipping the filter, that's fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the NCO truncation. >>> >>> Maybe I shouldn't say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn't produce the unfilterable spurs. I'm not betting on it. >>> >> >> you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine >> you want to turn that into a square wave so you stick it into a comparator. >> >> The comparator isn't perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc. >> At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s >> so 1uV tresh hold variation turns into a ~16us timing variation >> >> ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop >> the peaks off since we are only interested in the zero crossing >> so 1uV tresh hold variation is now only a ~160ns timing variation > > Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC > will change about every millisecond. And theoretically one step parks > at zero volts. So jitter is bad. Gain doesn't improve things.
Numerical gain ahead of the DAC does help, though, as somebody pointed out upthread. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
On Friday, August 12, 2022 at 1:03:24 PM UTC-4, Phil Hobbs wrote:
> John Larkin wrote: > > On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen > > <lang...@fonz.dk> wrote: > > > >> torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky: > >>> On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote: > >>>> torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky: > >>>>> On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote: > >>>>>> On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky > >>>>>> <gnuarm.del...@gmail.com> wrote: > >>>>>>> On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: > >>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> > >>>>>>>> wrote: > >>>>>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: > >>>>>>>>> > >>>>>>>>>> My question was, why make a sine wave if the final result is a digital > >>>>>>>>>> clock? > >>>>>>>>> > >>>>>>>>> Do you want the digital clock edges to be synchronous with an existing source, or > >>>>>>>>> asynchronous? Mathematically, the creation of an asynchronous clock is > >>>>>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component. > >>>>>>>> Of course. The analog components are dac, filter, comparator. > >>>>>>>> > >>>>>>>> I want a programmable internal trigger rate for a pulse generator. > >>>>>>>> > >>>>>>>> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, > >>>>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is > >>>>>>>> incremented infrequently and the filter doesn't do much. > >>>>>>> > >>>>>>> Sounds like an application for dithering. > >>>>>> > >>>>>> Do you even need explicit dithering ? > >>>>>> > >>>>>> The DAC output has some wide band (thermal) white noise. If the wide > >>>>>> noise power is close to the LSB size, do you need additional > >>>>>> dithering?. At low frequencies, there is also the 1/f noise. > >>>>>> > >>>>>> For audio frequencies "24 bit" 192 kHz DACs are available, which > >>>>>> accepts 24 bit sample values, but in practice the last few LSB bits > >>>>>> are buried in noise. > >>>>>> > >>>>>> If you need better dither control, some DDS chips have phase and/or > >>>>>> amplitude modulators built in, so the PM/AM inputs can be used to > >>>>>> control the high frequency dither more precisely. > >>>>> larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock. > >>>>> > >>>>> He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to filter. > >>>>> > >>>>> The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas. > >>>>> > >>>>> I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for the different ranges of clock output rates. > >>>>> > >>>>> Don't you agree? > >>>> afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate > >>> And your point is? > >>> > >>> If larkin is talking about producing a square or "trapezoidal" wave from the NCO and skipping the filter, that's fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the NCO truncation. > >>> > >>> Maybe I shouldn't say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn't produce the unfilterable spurs. I'm not betting on it. > >>> > >> > >> you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine > >> you want to turn that into a square wave so you stick it into a comparator. > >> > >> The comparator isn't perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc. > >> At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s > >> so 1uV tresh hold variation turns into a ~16us timing variation > >> > >> ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop > >> the peaks off since we are only interested in the zero crossing > >> so 1uV tresh hold variation is now only a ~160ns timing variation > > > > Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC > > will change about every millisecond. And theoretically one step parks > > at zero volts. So jitter is bad. Gain doesn't improve things. > Numerical gain ahead of the DAC does help, though, as somebody pointed > out upthread.
It's hard to do good work with a 10 bit DAC. A 16 bit DAC would improve the time step to about 16 us. https://www.ti.com/data-converters/dac-circuit/high-speed/products.html#p84=16;16&sort=p1130;asc This time step does not define the jitter. That's why the sine wave is filtered, to smooth the threshold point to a proper sine function. Different filters are needed for different frequency ranges. That would seem to be pretty obvious. -- Rick C. ---- Get 1,000 miles of free Supercharging ---- Tesla referral code - https://ts.la/richard11209
On 12/8/22 17:20, Martin Brown wrote:
> Although that is true if you set your zero crossing high/low by half a > least significant bit (or half the smallest step in the sine wave table) > then you can trade lower jitter for a small asymmetry in the waveform.
Wouldn't it be just as good (and symmetrical) to introduce a one-bit hysteresis? And not need to divide?
> The other option is to integrate the output of the DAC so that you get a > join the dots piecewise linear waveform much more amenable to comparator > thresholding and interpolation in the time domain.
So, a first-order filter? What do you reckon a normal DDS filter is doing? Clifford Heath
On 12/8/22 23:54, upsidedown@downunder.com wrote:
> On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky > <gnuarm.deletethisbit@gmail.com> wrote: > >> On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote: >>> On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky >>> <gnuarm.del...@gmail.com> wrote: >>>> On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: >>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>> wrote: >>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>> >>>>>>> My question was, why make a sine wave if the final result is a digital >>>>>>> clock? >>>>>> >>>>>> Do you want the digital clock edges to be synchronous with an existing source, or >>>>>> asynchronous? Mathematically, the creation of an asynchronous clock is >>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component. >>>>> Of course. The analog components are dac, filter, comparator. >>>>> >>>>> I want a programmable internal trigger rate for a pulse generator. >>>>> >>>>> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>> incremented infrequently and the filter doesn't do much. >>>> >>>> Sounds like an application for dithering. >>> >>> Do you even need explicit dithering ? >>> >>> The DAC output has some wide band (thermal) white noise. If the wide >>> noise power is close to the LSB size, do you need additional >>> dithering?. At low frequencies, there is also the 1/f noise. >>> >>> For audio frequencies "24 bit" 192 kHz DACs are available, which >>> accepts 24 bit sample values, but in practice the last few LSB bits >>> are buried in noise. >>> >>> If you need better dither control, some DDS chips have phase and/or >>> amplitude modulators built in, so the PM/AM inputs can be used to >>> control the high frequency dither more precisely. >> >> larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock. >> >> He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. > > If the purpose is to create a variable _timing_ generator (not just > frequency generator), why mess with the DDS principle at all ? > > Using a divide-by-N counter clocked at say, 1 GHz, you can timing > intervals in 1 ns steps. With a 48 bit synchronous down counter, you > can get timing intervals of several days with 1 ns timing steps. Some > trickery is needed to avoid running all 48 stages at full ECL speed. > > But the real question is, do you really need nanosecond step size in > minutes, hours or day time scale ? > > Admittedly, the 1 ns timing step is quite coarse at short pulses, inn > which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS > might be justified to get 1 ps timing steps. But for longer times, > say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider > after the DDS ? Combining the DDS and divide-by-N programming, quite > strange periods can be obtained.
You just described a one-bit DDS. It doesn't need a lookup table, of course. CH
On 13/8/22 00:10, John Larkin wrote:
> On Fri, 12 Aug 2022 16:54:04 +0300, upsidedown@downunder.com wrote: > >> On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky >> <gnuarm.deletethisbit@gmail.com> wrote: >> >>> On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote: >>>> On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky >>>> <gnuarm.del...@gmail.com> wrote: >>>>> On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: >>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>> wrote: >>>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>> >>>>>>>> My question was, why make a sine wave if the final result is a digital >>>>>>>> clock? >>>>>>> >>>>>>> Do you want the digital clock edges to be synchronous with an existing source, or >>>>>>> asynchronous? Mathematically, the creation of an asynchronous clock is >>>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component. >>>>>> Of course. The analog components are dac, filter, comparator. >>>>>> >>>>>> I want a programmable internal trigger rate for a pulse generator. >>>>>> >>>>>> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>> incremented infrequently and the filter doesn't do much. >>>>> >>>>> Sounds like an application for dithering. >>>> >>>> Do you even need explicit dithering ? >>>> >>>> The DAC output has some wide band (thermal) white noise. If the wide >>>> noise power is close to the LSB size, do you need additional >>>> dithering?. At low frequencies, there is also the 1/f noise. >>>> >>>> For audio frequencies "24 bit" 192 kHz DACs are available, which >>>> accepts 24 bit sample values, but in practice the last few LSB bits >>>> are buried in noise. >>>> >>>> If you need better dither control, some DDS chips have phase and/or >>>> amplitude modulators built in, so the PM/AM inputs can be used to >>>> control the high frequency dither more precisely. >>> >>> larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock. >>> >>> He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. >> >> If the purpose is to create a variable _timing_ generator (not just >> frequency generator), why mess with the DDS principle at all ? > > Most of our customers expect to set an internal trigger frequency. > There are times when setting it to high resolution is valuable. > >> >> Using a divide-by-N counter clocked at say, 1 GHz, you can timing >> intervals in 1 ns steps. With a 48 bit synchronous down counter, you >> can get timing intervals of several days with 1 ns timing steps. Some >> trickery is needed to avoid running all 48 stages at full ECL speed. > > I can't do that in an FPGA. And resolution is mediocre around 10 MHz. > > It might be interesting to program a 1 GHz SERDES channel (which we > can do) DDS-sorta waveform that we can filter into a comparator. > That's hard to think about, which I can delegate. > >> >> But the real question is, do you really need nanosecond step size in >> minutes, hours or day time scale ? > > A straightforward DDS will have tons of period jitter at low > frequencies, which is ugly. And some customers whine if we stop > triggering while we reprogram a DDS (or a synth chip) and a divisor.
So use the top bit of the DDS accumulator, but take the next few bits to drive a digital delay generator to add 0..1ns of extra delay (or 0.5..1.5ns, etc). You're good with design of picosecond digital delay generators, I understand? Clifford Heath.