DDS questions

lørdag den 13. august 2022 kl. 02.17.58 UTC+2 skrev Clifford Heath:
> On 13/8/22 00:10, John Larkin wrote: 
> > On Fri, 12 Aug 2022 16:54:04 +0300, upsid...@downunder.com wrote: 
> > 
> >> On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky 
> >> <gnuarm.del...@gmail.com> wrote: 
> >> 
> >>> On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote: 
> >>>> On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky 
> >>>> <gnuarm.del...@gmail.com> wrote: 
> >>>>> On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: 
> >>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> 
> >>>>>> wrote: 
> >>>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: 
> >>>>>>> 
> >>>>>>>> My question was, why make a sine wave if the final result is a digital 
> >>>>>>>> clock? 
> >>>>>>> 
> >>>>>>> Do you want the digital clock edges to be synchronous with an existing source, or 
> >>>>>>> asynchronous? Mathematically, the creation of an asynchronous clock is 
> >>>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component. 
> >>>>>> Of course. The analog components are dac, filter, comparator. 
> >>>>>> 
> >>>>>> I want a programmable internal trigger rate for a pulse generator. 
> >>>>>> 
> >>>>>> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, 
> >>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is 
> >>>>>> incremented infrequently and the filter doesn't do much. 
> >>>>> 
> >>>>> Sounds like an application for dithering. 
> >>>> 
> >>>> Do you even need explicit dithering ? 
> >>>> 
> >>>> The DAC output has some wide band (thermal) white noise. If the wide 
> >>>> noise power is close to the LSB size, do you need additional 
> >>>> dithering?. At low frequencies, there is also the 1/f noise. 
> >>>> 
> >>>> For audio frequencies "24 bit" 192 kHz DACs are available, which 
> >>>> accepts 24 bit sample values, but in practice the last few LSB bits 
> >>>> are buried in noise. 
> >>>> 
> >>>> If you need better dither control, some DDS chips have phase and/or 
> >>>> amplitude modulators built in, so the PM/AM inputs can be used to 
> >>>> control the high frequency dither more precisely. 
> >>> 
> >>> larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock. 
> >>> 
> >>> He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. 
> >> 
> >> If the purpose is to create a variable _timing_ generator (not just 
> >> frequency generator), why mess with the DDS principle at all ? 
> > 
> > Most of our customers expect to set an internal trigger frequency. 
> > There are times when setting it to high resolution is valuable. 
> > 
> >> 
> >> Using a divide-by-N counter clocked at say, 1 GHz, you can timing 
> >> intervals in 1 ns steps. With a 48 bit synchronous down counter, you 
> >> can get timing intervals of several days with 1 ns timing steps. Some 
> >> trickery is needed to avoid running all 48 stages at full ECL speed. 
> > 
> > I can't do that in an FPGA. And resolution is mediocre around 10 MHz. 
> > 
> > It might be interesting to program a 1 GHz SERDES channel (which we 
> > can do) DDS-sorta waveform that we can filter into a comparator. 
> > That's hard to think about, which I can delegate. 
> > 
> >> 
> >> But the real question is, do you really need nanosecond step size in 
> >> minutes, hours or day time scale ? 
> > 
> > A straightforward DDS will have tons of period jitter at low 
> > frequencies, which is ugly. And some customers whine if we stop 
> > triggering while we reprogram a DDS (or a synth chip) and a divisor.
> So use the top bit of the DDS accumulator, but take the next few bits to 
> drive a digital delay generator to add 0..1ns of extra delay (or 
> 0.5..1.5ns, etc). 

make a square wave with the DAC, into integrator (filter)
vary the amplitude

On Fri, 12 Aug 2022 07:10:56 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:

>On Fri, 12 Aug 2022 16:54:04 +0300, upsidedown@downunder.com wrote:
>
>>On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky

<snip>

>>If the purpose is to create a variable _timing_ generator (not just
>>frequency generator), why mess with the DDS principle at all ?
>
>Most of our customers expect to set an internal trigger frequency.
>There are times when setting it to high resolution is valuable.
>
>>
>>Using a divide-by-N counter clocked at say, 1 GHz, you can timing
>>intervals in 1 ns steps. With a 48 bit synchronous down counter, you
>>can get timing intervals of several days with 1 ns timing steps. Some
>>trickery is needed to avoid running  all 48 stages at full ECL speed. 
>
>I can't do that in an FPGA. And resolution is mediocre around 10 MHz.

Use a fast 8 bit down counter followed by a slow 40 bit down counter.
If the fast counter is run at 1 GHz (1 ns), the slow  counter only
runs at 4 MHz. When the slow down counter reaches 0x0000000000, it can
start reloading the preset value. At that time the fast counter is at
0xFF and it takes 256 ns before reaching zero and doing the preset. At
that time the slow counter has already been reloaded and it can start
counting as soon as the preset fast counter reaches 0 the next time.

<snip>

>>But the real question is, do you really need nanosecond step size in
>>minutes, hours or day time scale ?
>
>A straightforward DDS will have tons of period jitter at low
>frequencies, which is ugly. 

Then do not use DDS directly for very low frequencies.

>And some customers whine if we stop
>triggering while we reprogram a DDS (or a synth chip) and a divisor.

Reprogramming DDS = loading a new addend value into the DDS. After
that the phase accumulator increases more or less rapidly, so quite
hard to even detect in a short time. 

>>Admittedly, the 1 ns timing step is quite coarse at short pulses, inn
>>which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS
>>might be justified to get 1 ps  timing steps. But for longer times,
>>say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider
>>after the DDS ? Combining the DDS and divide-by-N programming, quite
>>strange periods can be obtained.

If you have a DDS for periods shorter than 1 s, you could add a
divide-by-N for longer periods. Each time the divide-by-N reaches 0,
you could enable the DDS addend loading, thus the timing would be
quite clean, even for a time sweep. Of course, this will require
precalculating the DDS addend and the divide-by-N before the divider
expires, but a very primitive CPU could do it before a sweep or other
predictable sequence.

On Friday, August 12, 2022 at 9:08:27 AM UTC-7, Mike Monett wrote:
> A New Frequency Synthesis Technique 
> . . .
> The description of Rational Approximation Synthesis starts on page 151. A 
> block diagram is on page 156. 

Amusing.  That wasn't exactly 'new' when I implemented it in 2002 or so.
( http://www.ke5fx.com/synth.html )  It was probably still covered
by one Qualcomm patent or another at the time, in retrospect.

I used a crystal filter rather than a narrowband VCXO, but same difference.

-- john, KE5FX

"John Miles, KE5FX" <jmiles@gmail.com> wrote:

> On Friday, August 12, 2022 at 9:08:27 AM UTC-7, Mike Monett wrote:
>> A New Frequency Synthesis Technique 
>> . . .
>> The description of Rational Approximation Synthesis starts on page 151. A 
>> block diagram is on page 156. 
> 
> Amusing.  That wasn't exactly 'new' when I implemented it in 2002 or so.
> ( http://www.ke5fx.com/synth.html )  It was probably still covered
> by one Qualcomm patent or another at the time, in retrospect.
> 
> I used a crystal filter rather than a narrowband VCXO, but same difference.
> 
> -- john, KE5FX

Amazing documentation. Thanks.

Mike 



-- 
MRM

On Saturday, August 13, 2022 at 8:18:00 PM UTC-7, Mike Monett wrote:
> Amazing documentation. Thanks. 

Pretty awful synthesizer design, though. :)

-- john, KE5FX

"John Miles, KE5FX" <jmiles@gmail.com> wrote:

> On Saturday, August 13, 2022 at 8:18:00 PM UTC-7, Mike Monett wrote:
>> Amazing documentation. Thanks. 
> 
> Pretty awful synthesizer design, though. :)
> 
> -- john, KE5FX

The performance is clearly superior to the ICOM. Congratulations.

I am absolutely amazed by the quantity and quality of your documentation. 
This would take a normal human a year to complete.



-- 
MRM

On Saturday, August 13, 2022 at 9:24:21 PM UTC-7, Mike Monett wrote:
> I am absolutely amazed by the quantity and quality of your documentation. 
> This would take a normal human a year to complete. 

Thanks!  There was lots of room for improvement (the crystal filter/
comparator section is just embarrassing) but it performed well 
on a $/dBc/Hz basis.  And it did made a very nice article for QEX.

Nowadays, all that stuff fits on a single IC and provides 20 GHz of
coverage with far less noise of both white and flicker varieties.  Of 
course the best chips are unobtainium TI parts that have to be sourced 
from Chinese scalpers at prices well into the 3-digit range, but that seems 
to be the new way of the world. 

-- john, KE5FX

"John Miles, KE5FX" <jmiles@gmail.com> wrote:

> On Saturday, August 13, 2022 at 9:24:21 PM UTC-7, Mike Monett wrote:
>> I am absolutely amazed by the quantity and quality of your
>> documentation. This would take a normal human a year to complete. 
> 
> Thanks!  There was lots of room for improvement (the crystal filter/
> comparator section is just embarrassing) but it performed well 
> on a $/dBc/Hz basis.  And it did made a very nice article for QEX.
> 
> Nowadays, all that stuff fits on a single IC and provides 20 GHz of
> coverage with far less noise of both white and flicker varieties.  Of 
> course the best chips are unobtainium TI parts that have to be sourced 
> from Chinese scalpers at prices well into the 3-digit range, but that
> seems to be the new way of the world. 
> 
> -- john, KE5FX

I'm interested. Can you name some of the best and who sells them?




-- 
MRM

On Saturday, August 13, 2022 at 11:04:08 PM UTC-7, Mike Monett wrote:
> I'm interested. Can you name some of the best and who sells them? 

LMX2820 (TI) and 8V97003 (Renesas) are two of the best integrated
PLL/VCO parts I've seen.  The LMX2595 has similar specs but the 
LMX2820 has some nice advantages, such as lower flicker noise and 
the ability to drive both phase detector inputs externally.

Look them up on octopart.com and you'll see that they are all 
sitting in Chinese warehouses by the tens of thousands, waiting for 
buyers who don't mind paying 4x-5x MSRP.  

ADF4371 (62.5 MHz - 32 GHz) also looks good.  Some stock left at
Mouser.   

Of all these parts, I've only messed with the LMX2820 in person.
I have a demo board for the Renesas part but haven't gotten
around to powering it up and trying it out yet.

-- john, KE5FX

Am 14.08.22 um 09:19 schrieb John Miles, KE5FX:
> On Saturday, August 13, 2022 at 11:04:08 PM UTC-7, Mike Monett wrote:
>> I'm interested. Can you name some of the best and who sells them?
> 
> LMX2820 (TI) and 8V97003 (Renesas) are two of the best integrated
> PLL/VCO parts I've seen.  The LMX2595 has similar specs but the
> LMX2820 has some nice advantages, such as lower flicker noise and
> the ability to drive both phase detector inputs externally.


I have published a synthesizer based on LMX2594 (15 GHz) in
Dubus 1/22. I will put it on my web site sooner or later, but
the chip is currently vapourware.
< 
https://www.flickr.com/photos/137684711@N07/51691780129/in/datetaken/    >

< 
https://www.flickr.com/photos/137684711@N07/51519856398/in/dateposted-public/ 
     >

There is 1 hittite HMC-451 output amplifier populated to drive
a HMC-220 ring mixer. The TI dongle & software cannot tell
it from an eval board.


There will be a companion clock generator with either a
100 MHz crystal oven or a CVHD-950. The oven/VCXO can be locked
to an external 10 MHz reference. It delivers
300 MHz for LMX2594 in fractional mode or
400 MHz for LMX2594 in integer mode.

400 MHz uses 2 SAW filters after the multiplier,
300 MHz uses 2*3pole LC, top coupled.
I could not find a nice 300 MHz SAW filter that is not EOL
or has less than 10 dB loss.

A previous version had some 10 MHz spurious from
the 1/10 prescaler.  It also had only 300 MHz.

< 
https://www.flickr.com/photos/137684711@N07/52284841519/in/dateposted-public/lightbox/ 
    >

It could be used for a DDS also, but currently there is no
need to rush it because of the 2594.


> Look them up on octopart.com and you'll see that they are all
> sitting in Chinese warehouses by the tens of thousands, waiting for
> buyers who don't mind paying 4x-5x MSRP.
> 
> ADF4371 (62.5 MHz - 32 GHz) also looks good.  Some stock left at
> Mouser.

At least it has some filtering after the output doubler.
The ADF5356 had a subharmonic that was horrible.

< 
https://www.flickr.com/photos/137684711@N07/50403778976/in/dateposted-public/ 
    >

If someone wants to play with these things, there are enough
boards. Hot air soldering is required, minimum.

cheers,
Gerhard   DK4XP