On 9/8/22 11:18, Mike Monett wrote:> Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote: > > [...] > >> Single-ended XOR gates are single-ended, but DBMs aren't necessarily. >> The RF and LO ports are both transformer-coupled, so you can drive them >> differentially with no issues. Even the LO port can be driven >> differentially for the upconversion. > > Yes, the RF and LO ports are both transformer-coupled. So what difference > does it make if these ports are driven single-ended vs differential? How does > the transformer know how the input is driven?Capacitive coupling? Transformers aren't perfect. And single-ended drive means the drive current goes into the local ground plane and spreads from there to whatever decoupling there is, leaving a visible signal across ground plane inductance and resistance.
DDS questions
Started by ●August 7, 2022
Reply by ●August 8, 20222022-08-08
Reply by ●August 10, 20222022-08-10
Clifford Heath <no_spam@please.net> wrote:> On 9/8/22 11:18, Mike Monett wrote: >> Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote: >> >> [...] >> >>> Single-ended XOR gates are single-ended, but DBMs aren't necessarily. >>> The RF and LO ports are both transformer-coupled, so you can drive >>> them differentially with no issues. Even the LO port can be driven >>> differentially for the upconversion. >> >> Yes, the RF and LO ports are both transformer-coupled. So what >> difference does it make if these ports are driven single-ended vs >> differential? How does the transformer know how the input is driven? > > Capacitive coupling? Transformers aren't perfect. > > And single-ended drive means the drive current goes into the local > ground plane and spreads from there to whatever decoupling there is, > leaving a visible signal across ground plane inductance and resistance.Yes. This is why I put noisy and sensitive circuits on their own ground plane, separated from the main ground plane. Signals in and out are differential whenever possible, and ground connections between the planes are chosen to minimise crosstalk. A number of oscilloscopes, such as Rigol, do the same thing. -- MRM
Reply by ●August 10, 20222022-08-10
On 08/08/2022 21:17, Ricky wrote:> On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: >> søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin: >>> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen >>> <lang...@fonz.dk> wrote: >>>> sųndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>> wrote: >>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>> >>>>>>> My question was, why make a sine wave if the final result is a digital >>>>>>> clock? >>>>>> >>>>>> Do you want the digital clock edges to be synchronous with an existing source, or >>>>>> asynchronous? Mathematically, the creation of an asynchronous clock is >>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component. >>>>> Of course. The analog components are dac, filter, comparator. >>>>> >>>>> I want a programmable internal trigger rate for a pulse generator. >>>>> >>>>> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>> incremented infrequently and the filter doesn't do much. >>>> >>>> if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff >>>> >>> That has problems too. >>> >>> We were thinking that you could gain-up and clip the sine wave to >>> increase the zero-cross slope. The logical end of that is to make a >>> trapezoid with a steep rise. >> keep decreasing the rise time and you get back to a squarewave >> a sine is probably some kind of optimum > > It is an optimum in that it is most easily filtered to give lowest jitter. > > >>> The DAC lsb increments rarely at low frequencies, so magically include >>> some lower phase accumulator bits to effectively increase the DAC >>> sample rate on that steep slope. Digitally interpolate. >> but if the DAC can't run any faster or have any more bits, how? > > He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to.If he wants to waste his time on this after ignoring all the good advice so far then one of the cheap and nasty Chinese DDS signal generators that has a user defined waveform lookup table would be the way to go. Nothing refutes a daft idea so effectively as practical experiment. Not knowing exactly why he really wants to do this - the simplest waveforms that are steeper at the origin than sin(x) and matched in gradient at zero crossing are parabolic or more generally of the form (1- (|x/pi-1/2|)^N) (and that function negated that on alternate half cycles) NB gradient of his triangle wave is 1 (or -1) everywhere but the gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). There is a very good reason why people generate sine waves by default. I suppose triangle wave and diode shaping to a sine wave would be an option (HP once used it to very good effect and their patent for that network has probably long since expired by now). ICL8038 did a crude imitation of the same trick in their monolithic function generator chip.> > In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the sine value/DAC resolution. > > Anyone who wishes to research DDS design will find this.The low pass filter needs to be frequency matched to the artefacts in the fundamental frequency being generated. No point in low pass filtering at 1MHz when the output is 10Hz. You need to attenuate the harmonics generated by the discrete steps in the DAC waveform. -- Regards, Martin Brown
Reply by ●August 10, 20222022-08-10
On Wednesday, August 10, 2022 at 4:50:56 AM UTC-4, Martin Brown wrote:> On 08/08/2022 21:17, Ricky wrote: > > On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: > >> søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin: > >>> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen > >>> <lang...@fonz.dk> wrote: > >>>> sųndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: > >>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> > >>>>> wrote: > >>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: > >>>>>> > >>>>>>> My question was, why make a sine wave if the final result is a digital > >>>>>>> clock? > >>>>>> > >>>>>> Do you want the digital clock edges to be synchronous with an existing source, or > >>>>>> asynchronous? Mathematically, the creation of an asynchronous clock is > >>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component. > >>>>> Of course. The analog components are dac, filter, comparator. > >>>>> > >>>>> I want a programmable internal trigger rate for a pulse generator. > >>>>> > >>>>> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, > >>>>> up to Nyquist. But it gets messy at low frequencies where the dac is > >>>>> incremented infrequently and the filter doesn't do much. > >>>> > >>>> if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff > >>>> > >>> That has problems too. > >>> > >>> We were thinking that you could gain-up and clip the sine wave to > >>> increase the zero-cross slope. The logical end of that is to make a > >>> trapezoid with a steep rise. > >> keep decreasing the rise time and you get back to a squarewave > >> a sine is probably some kind of optimum > > > > It is an optimum in that it is most easily filtered to give lowest jitter. > > > > > >>> The DAC lsb increments rarely at low frequencies, so magically include > >>> some lower phase accumulator bits to effectively increase the DAC > >>> sample rate on that steep slope. Digitally interpolate. > >> but if the DAC can't run any faster or have any more bits, how? > > > > He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to. > If he wants to waste his time on this after ignoring all the good advice > so far then one of the cheap and nasty Chinese DDS signal generators > that has a user defined waveform lookup table would be the way to go. > > Nothing refutes a daft idea so effectively as practical experiment. > > Not knowing exactly why he really wants to do this - the simplest > waveforms that are steeper at the origin than sin(x) and matched in > gradient at zero crossing are parabolic or more generally of the form > > (1- (|x/pi-1/2|)^N) > > (and that function negated that on alternate half cycles) > > NB gradient of his triangle wave is 1 (or -1) everywhere but the > gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). > There is a very good reason why people generate sine waves by default. > > I suppose triangle wave and diode shaping to a sine wave would be an > option (HP once used it to very good effect and their patent for that > network has probably long since expired by now). ICL8038 did a crude > imitation of the same trick in their monolithic function generator chip. > > > > In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the sine value/DAC resolution. > > > > Anyone who wishes to research DDS design will find this. > The low pass filter needs to be frequency matched to the artefacts in > the fundamental frequency being generated. No point in low pass > filtering at 1MHz when the output is 10Hz. You need to attenuate the > harmonics generated by the discrete steps in the DAC waveform.A 1 MHz filter would be appropriate if the sample rate is well above 1 MSPS. But the resolution of the DAC needs to also support such a wide range of frequencies. If he only needs a low frequency output, then this is not a good solution. But he seems to be saying he needs the wide frequency range. In that case, it would seem obvious that multiple filters would useful. Just like they don't build radios to cover all bands without separate band select filters, there will not be a one size fits all solution here. Most of the ideas he has talked about will impact the jitter requirements. Unless he addresses the phase accumulator truncation, he's never going to get really good jitter, no matter how good the filtering is. I don't recall the impact on jitter for a given resolution, but I found a reasonable phase truncation was 18 bits with an 18 bit sine table output. To improve beyond that with reasonable hardware (reasonable for my designs) requires sine approximation methods. But for his work, it would seem a CORDIC might be the right way to go. Add dithering to a few extra bits of sine with rounding, perhaps. -- Rick C. --+ Get 1,000 miles of free Supercharging --+ Tesla referral code - https://ts.la/richard11209
Reply by ●August 10, 20222022-08-10
On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown <'''newspam'''@nonad.co.uk> wrote:>On 08/08/2022 21:17, Ricky wrote: >> On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: >>> s�ndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin: >>>> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen >>>> <lang...@fonz.dk> wrote: >>>>> s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>> wrote: >>>>>>> On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>> >>>>>>>> My question was, why make a sine wave if the final result is a digital >>>>>>>> clock? >>>>>>> >>>>>>> Do you want the digital clock edges to be synchronous with an existing source, or >>>>>>> asynchronous? Mathematically, the creation of an asynchronous clock is >>>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component. >>>>>> Of course. The analog components are dac, filter, comparator. >>>>>> >>>>>> I want a programmable internal trigger rate for a pulse generator. >>>>>> >>>>>> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>> incremented infrequently and the filter doesn't do much. >>>>> >>>>> if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff >>>>> >>>> That has problems too. >>>> >>>> We were thinking that you could gain-up and clip the sine wave to >>>> increase the zero-cross slope. The logical end of that is to make a >>>> trapezoid with a steep rise. >>> keep decreasing the rise time and you get back to a squarewave >>> a sine is probably some kind of optimum >> >> It is an optimum in that it is most easily filtered to give lowest jitter. >> >> >>>> The DAC lsb increments rarely at low frequencies, so magically include >>>> some lower phase accumulator bits to effectively increase the DAC >>>> sample rate on that steep slope. Digitally interpolate. >>> but if the DAC can't run any faster or have any more bits, how? >> >> He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to. > >If he wants to waste his time on this after ignoring all the good advice >so far then one of the cheap and nasty Chinese DDS signal generators >that has a user defined waveform lookup table would be the way to go.Thinking about possibilities is never a waste of time. It may lead to something useful now or later, and thinking is good exercise for thinking. Try it.> >Nothing refutes a daft idea so effectively as practical experiment.The idea shooters here don't need experiments, when insults are easier.> >Not knowing exactly why he really wants to do this - the simplest >waveforms that are steeper at the origin than sin(x) and matched in >gradient at zero crossing are parabolic or more generally of the form > >(1- (|x/pi-1/2|)^N) > >(and that function negated that on alternate half cycles) > >NB gradient of his triangle wave is 1 (or -1) everywhere but the >gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). >There is a very good reason why people generate sine waves by default. > >I suppose triangle wave and diode shaping to a sine wave would be an >option (HP once used it to very good effect and their patent for that >network has probably long since expired by now). ICL8038 did a crude >imitation of the same trick in their monolithic function generator chip. >> >> In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the sine value/DAC resolution. >> >> Anyone who wishes to research DDS design will find this. > >The low pass filter needs to be frequency matched to the artefacts in >the fundamental frequency being generated. No point in low pass >filtering at 1MHz when the output is 10Hz. You need to attenuate the >harmonics generated by the discrete steps in the DAC waveform.And one has to do something about the fact that the DAC code will increment infrequently at 1 Hz. That is a time-domain concept. I suggested digitally shaping the DAC waveform to increase the sample rate and slope at low frequencies. Or at all frequencies. Interpolation is one approach. New idea: at some low frequency, just banging the dac rail-to-rail with the phase accumulator MSB will make less jitter than stubbornly insisting on making a slow sine into the filter+comparator. At high frequencies, the unfiltered MSB is a horror. That idea has interesting offshoots. -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
Reply by ●August 10, 20222022-08-10
On Wednesday, August 10, 2022 at 7:47:20 AM UTC-7, John Larkin wrote:> On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown > <'''newspam'''@nonad.co.uk> wrote:> >Nothing refutes a daft idea so effectively as practical experiment.> The idea shooters here don't need experiments, when insults are > easier.Oh, the refutation of an idea by an application of theory is just as effective as experiment, and multiple refutations of both sort have entered the discussion. There are no 'idea shooters' more useless than those who keep up a chorus of 'why not' and ignore the sensible answers.> >Not knowing exactly why he really wants to do this - the simplest > >waveforms that are steeper at the origin than sin(x) and matched in > >gradient at zero crossing are parabolic or more generally of the form > > > >(1- (|x/pi-1/2|)^N) > > > >(and that function negated that on alternate half cycles) > > > >NB gradient of his triangle wave is 1 (or -1) everywhere but the > >gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). > >There is a very good reason why people generate sine waves by default.Yes, that's a good analysis. Transient analysis might tell you what a filter gives for a triangle wave or sawtooth, but the sinewave analysis of filter operation is much easier, and supports useful conclusions. It's useful; use it.
Reply by ●August 10, 20222022-08-10
On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky <gnuarm.deletethisbit@gmail.com> wrote:>On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: >> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >> wrote: >> >On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >> > >> >> My question was, why make a sine wave if the final result is a digital >> >> clock? >> > >> >Do you want the digital clock edges to be synchronous with an existing source, or >> >asynchronous? Mathematically, the creation of an asynchronous clock is >> >not gonna happen in clocked logic circuitry, it has to have an analog component. >> Of course. The analog components are dac, filter, comparator. >> >> I want a programmable internal trigger rate for a pulse generator. >> >> A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >> up to Nyquist. But it gets messy at low frequencies where the dac is >> incremented infrequently and the filter doesn't do much. > >Sounds like an application for dithering.Do you even need explicit dithering ? The DAC output has some wide band (thermal) white noise. If the wide noise power is close to the LSB size, do you need additional dithering?. At low frequencies, there is also the 1/f noise. For audio frequencies "24 bit" 192 kHz DACs are available, which accepts 24 bit sample values, but in practice the last few LSB bits are buried in noise. If you need better dither control, some DDS chips have phase and/or amplitude modulators built in, so the PM/AM inputs can be used to control the high frequency dither more precisely.
Reply by ●August 10, 20222022-08-10
onsdag den 10. august 2022 kl. 16.47.20 UTC+2 skrev John Larkin:> > New idea: at some low frequency, just banging the dac rail-to-rail > with the phase accumulator MSB will make less jitter than stubbornly > insisting on making a slow sine into the filter+comparator. At high > frequencies, the unfiltered MSB is a horror. >ahh now I see what are on about, at very low frequencies the fixed jitter of a Fclk cycle could be better than a comparator trying to digitize a (noisy) slow rising sine maybe a frequency dependent gain and clamp to maintain a constant slew-rate could work
Reply by ●August 10, 20222022-08-10
On Wed, 10 Aug 2022 13:22:13 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>onsdag den 10. august 2022 kl. 16.47.20 UTC+2 skrev John Larkin: >> >> New idea: at some low frequency, just banging the dac rail-to-rail >> with the phase accumulator MSB will make less jitter than stubbornly >> insisting on making a slow sine into the filter+comparator. At high >> frequencies, the unfiltered MSB is a horror. >> > >ahh now I see what are on about, at very low frequencies >the fixed jitter of a Fclk cycle could be better than >a comparator trying to digitize a (noisy) slow rising sine > >maybe a frequency dependent gain and clamp to maintain a constant slew-rate could workThe MSB of the phase accumulator has jitter of one clock p-p. The RMS jitter of that is 1 clock period / sqrt(12). That could be a few ns RMS jitter at mHz frequencies. I was just thinking about possible tricks to reduce DDS period jitter at low frequencies, without the obvious post-comparator divisor. -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
Reply by ●August 10, 20222022-08-10
onsdag den 10. august 2022 kl. 23.15.59 UTC+2 skrev John Larkin:> On Wed, 10 Aug 2022 13:22:13 -0700 (PDT), Lasse Langwadt Christensen > <lang...@fonz.dk> wrote: > > >onsdag den 10. august 2022 kl. 16.47.20 UTC+2 skrev John Larkin: > >> > >> New idea: at some low frequency, just banging the dac rail-to-rail > >> with the phase accumulator MSB will make less jitter than stubbornly > >> insisting on making a slow sine into the filter+comparator. At high > >> frequencies, the unfiltered MSB is a horror. > >> > > > >ahh now I see what are on about, at very low frequencies > >the fixed jitter of a Fclk cycle could be better than > >a comparator trying to digitize a (noisy) slow rising sine > > > >maybe a frequency dependent gain and clamp to maintain a constant slew-rate could work > The MSB of the phase accumulator has jitter of one clock p-p. The RMS > jitter of that is 1 clock period / sqrt(12). That could be a few ns > RMS jitter at mHz frequencies. > > I was just thinking about possible tricks to reduce DDS period jitter > at low frequencies, without the obvious post-comparator divisor.The sine and filter does that. Draw a line between the data points and see that the zero crossing doesn't fall on a clock edge but it might help to gain up the sine to increase the slew rate so it doesn't hang around the comparator threshold forever, when all it has to do is delay a variable +/-1 cycle
