non-pipelined fast ADC

On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote:
> Does anybody know of one? I'd like to digitize 6 bits or so, really
> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
> bits might work.
> 
> Classic "flash" ADCs were fast, but needed 2^N comparators.

What are you trying to do that can't wait a few clock cycles?

-- john, KE5FX

On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), "John Miles, KE5FX"
<jmiles@gmail.com> wrote:

>On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote:
>> Does anybody know of one? I'd like to digitize 6 bits or so, really
>> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
>> bits might work.
>> 
>> Classic "flash" ADCs were fast, but needed 2^N comparators.
>
>What are you trying to do that can't wait a few clock cycles?
>
>-- john, KE5FX

It's a PLL, and lag slows down the loop dynamics.

I start an LC oscillator when I get a trigger, and use it to time out
delays. The ADC is clocked from an OCXO and observes the waveform of
the triggered LC oscillator, and I close a loop to lock the LC to the
XO. Actually, the LC frequency is whatever it wants to be. The math
gets ugly. 

The sooner and tighter we can close the loop, the less the LC drifts.

There's a DAC too, but they're fast.

I just found this:

https://www.analog.com/en/products/adv7125.html

Triple 8-bit DAC, 330 MHz, cheap.




-- 

John Larkin         Highland Technology, Inc

Science teaches us to doubt.

  Claude Bernard
  

On Tue, 25 Aug 2020 15:44:41 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 2020-08-25 14:34, John Larkin wrote:
>> 
>> Does anybody know of one? I'd like to digitize 6 bits or so, really
>> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
>> bits might work.
>> 
>> Classic "flash" ADCs were fast, but needed 2^N comparators.
>> 
>
>Plus they had fixed-pattern jitter due to the different RC delays on the 
>resistor string.
>
>How fast is fast?
>
>Cheers
>
>Phil Hobbs

200M s/s would be nice. More like 80M if I do some ugly undersampling.

I'm thinking about new delay generator architectures, and am very
confused. It's good to be confused for a while.



-- 

John Larkin         Highland Technology, Inc

Science teaches us to doubt.

  Claude Bernard
  

On Tuesday, August 25, 2020 at 2:34:31 PM UTC-4, John Larkin wrote:
> Does anybody know of one? I'd like to digitize 6 bits or so, really
> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
> bits might work.
> 
> Classic "flash" ADCs were fast, but needed 2^N comparators.

If you want a really fast 6 bit converter look to see what they were selling 20 years ago.  

I'm actually surprised they don't still make them in 6 bits.  I thought they mostly went to the complicated architectures to increase the resolution, but I guess the logic can be run faster with pipelining.  There's FAST and there's DAMN FAST.  That was actually terms used in a National data book if I remember correctly... for buffers I believe. 

-- 

  Rick C.

  - Get 1,000 miles of free Supercharging
  - Tesla referral code - https://ts.la/richard11209

On Tuesday, August 25, 2020 at 7:25:08 PM UTC-7, jla...@highlandsniptechnology.com wrote:
> On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), "John Miles, KE5FX"
> <jmiles@gmail.com> wrote:
> 
> >On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote:
> >> Does anybody know of one? I'd like to digitize 6 bits or so, really
> >> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
> >> bits might work.
> >> 
...
> It's a PLL, and lag slows down the loop dynamics.
> 
> I start an LC oscillator when I get a trigger, and use it to time out
> delays. The ADC is clocked from an OCXO and observes the waveform of
> the triggered LC oscillator, and I close a loop to lock the LC to the
> XO. Actually, the LC frequency is whatever it wants to be. The math
> gets ugly. 

So, the LC is just an inaccurate copy of the XO?
> 
> The sooner and tighter we can close the loop, the less the LC drifts.

The LC has a high Q, I assume, and that means it  has low phase noise, but
you're steering it, which means you aren't getting the Q advantage and
your phase noise includes artifacts due to corrections.

Maybe  downmix the LC oscillator against a filtered PLL (as the local oscillator)
which gives a low-frequency error signal, easily measured.   Any frequency/phase
comparison/correction will take time according to the frequency resolution, 
though.   Measure, and use the info for a correction afterwards, might be easier than 
control at HF in realtime.

On 2020-08-26 00:16, whit3rd wrote:
> On Tuesday, August 25, 2020 at 7:25:08 PM UTC-7, jla...@highlandsniptechnology.com wrote:
>> On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), "John Miles, KE5FX"
>> <jmiles@gmail.com> wrote:
>>
>>> On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote:
>>>> Does anybody know of one? I'd like to digitize 6 bits or so, really
>>>> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
>>>> bits might work.
>>>>
> ....
>> It's a PLL, and lag slows down the loop dynamics.
>>
>> I start an LC oscillator when I get a trigger, and use it to time out
>> delays. The ADC is clocked from an OCXO and observes the waveform of
>> the triggered LC oscillator, and I close a loop to lock the LC to the
>> XO. Actually, the LC frequency is whatever it wants to be. The math
>> gets ugly.
> 
> So, the LC is just an inaccurate copy of the XO?
>>
>> The sooner and tighter we can close the loop, the less the LC drifts.
> 
> The LC has a high Q, I assume, and that means it  has low phase noise, but
> you're steering it, which means you aren't getting the Q advantage and
> your phase noise includes artifacts due to corrections.
> 
> Maybe  downmix the LC oscillator against a filtered PLL (as the local oscillator)
> which gives a low-frequency error signal, easily measured.   Any frequency/phase
> comparison/correction will take time according to the frequency resolution,
> though.   Measure, and use the info for a correction afterwards, might be easier than
> control at HF in realtime.

Pretty hard to accurately delay an asynchronous input by a microsecond 
that way, especially with picosecond resolution.

JL has discussed the instant-on LC oscillator here many times.

A crystal oscillator is useless because you can't get at the interior 
node of the equivalent LC circuit to hang a switch on it--you have to 
put DC on the whole thing.  That means that at trigger time there's a 
big voltage step on the rest of the circuit (including the parallel 
capacitance and the other crystal modes).  That's bound to make the 
first few cycles look different from subsequent ones, which will make 
the timing indeterminate.

An LC triggered using a very low capacitance switch such as a pHEMT 
basically shimmers into life as though it had been oscillating all the time.

(I've never done it myself, but I do use crystal ring-down for 
calibrating AM detectors.  You have to ignore the first part of the 
exponential decay for the same reason, and of course because the crystal 
rings at its mechanical resonance, which is not where it was running at 
the beginning.)

Cheers

Phil Hobbs

-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

On 25/08/2020 10:33 pm, John Larkin wrote:
> I'm digitizing a capacitive linear ramp anyhow!
> 

Hmm? If it is linear then you know where it is going - why need to 
digitize at all, just have two comparators?

piglet

On 25/08/2020 19:34, John Larkin wrote:
> 
> Does anybody know of one? I'd like to digitize 6 bits or so, really
> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
> bits might work.
> 
> Classic "flash" ADCs were fast, but needed 2^N comparators.
> 
Your favourite supplier has a dual 800Mhz one:
MAX105ECS+

Mouser have stock.

MK

onsdag den 26. august 2020 kl. 15.01.37 UTC+2 skrev Michael Kellett:
> On 25/08/2020 19:34, John Larkin wrote:
> > 
> > Does anybody know of one? I'd like to digitize 6 bits or so, really
> > fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
> > bits might work.
> > 
> > Classic "flash" ADCs were fast, but needed 2^N comparators.
> > 
> Your favourite supplier has a dual 800Mhz one:
> MAX105ECS+
> 
> Mouser have stock.
> 

look at the datasheet, pipeline delay 5-6 cycles

On 08/26/20 03:24, jlarkin@highlandsniptechnology.com wrote:
> On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), "John Miles, KE5FX"
> <jmiles@gmail.com>  wrote:
>
>> On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote:
>>> Does anybody know of one? I'd like to digitize 6 bits or so, really
>>> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
>>> bits might work.
>>>
>>> Classic "flash" ADCs were fast, but needed 2^N comparators.
>>
>> What are you trying to do that can't wait a few clock cycles?
>>
>> -- john, KE5FX
>
> It's a PLL, and lag slows down the loop dynamics.
>
> I start an LC oscillator when I get a trigger, and use it to time out
> delays. The ADC is clocked from an OCXO and observes the waveform of
> the triggered LC oscillator, and I close a loop to lock the LC to the
> XO. Actually, the LC frequency is whatever it wants to be. The math
> gets ugly.
>
> The sooner and tighter we can close the loop, the less the LC drifts.
>
> There's a DAC too, but they're fast.
>
> I just found this:
>
> https://www.analog.com/en/products/adv7125.html
>
> Triple 8-bit DAC, 330 MHz, cheap.
>
>
>
>

Can't you rethink this and find a way to gate an oscillator that is
always on, perhaps already locked to the ocxo ?. Present sketch  of
a-d etc looks expensive and hard work...

Chris