On 26/08/2020 14:26, Lasse Langwadt Christensen wrote:> onsdag den 26. august 2020 kl. 15.01.37 UTC+2 skrev Michael Kellett: >> On 25/08/2020 19:34, John Larkin wrote: >>> >>> Does anybody know of one? I'd like to digitize 6 bits or so, really >>> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 >>> bits might work. >>> >>> Classic "flash" ADCs were fast, but needed 2^N comparators. >>> >> Your favourite supplier has a dual 800Mhz one: >> MAX105ECS+ >> >> Mouser have stock. >> > > look at the datasheet, pipeline delay 5-6 cycles > >Woops - so it is :-( MK
non-pipelined fast ADC
Started by ●August 25, 2020
Reply by ●August 26, 20202020-08-26
Reply by ●August 26, 20202020-08-26
Am 26.08.20 um 15:26 schrieb Lasse Langwadt Christensen:> onsdag den 26. august 2020 kl. 15.01.37 UTC+2 skrev Michael Kellett: >> On 25/08/2020 19:34, John Larkin wrote: >>> >>> Does anybody know of one? I'd like to digitize 6 bits or so, really >>> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 >>> bits might work. >>> >>> Classic "flash" ADCs were fast, but needed 2^N comparators.The first thing i had to build after grad. was a signal averager with a 8 bit 20 MHz flash converter. We got one from the TRW salesdroid in an clear epoxy cube. You could see the reference ladder on the chip with bare eyes. It took 8 74LS computation units in parallel/round robin to do the averaging. < https://www.flickr.com/photos/137684711@N07/50270501968/in/album-72157662535945536/lightbox/ > (really the boards in the background. On top is the first fpga implementation. There was an intermediate 100K-ECL version for 200 MHz.) The TRW flash ADC is the large chip on the bottom-right.>>> >> Your favourite supplier has a dual 800Mhz one: >> MAX105ECS+ >> >> Mouser have stock.DK, too> look at the datasheet, pipeline delay 5-6 cyclesWhen one clock delay at 100 MHz is OK, so are 6 cycles at 800 MHz. Cheers, Gerhard
Reply by ●August 26, 20202020-08-26
On Wed, 26 Aug 2020 13:50:56 +0100, piglet <erichpwagner@hotmail.com> wrote:>On 25/08/2020 10:33 pm, John Larkin wrote: >> I'm digitizing a capacitive linear ramp anyhow! >> > >Hmm? If it is linear then you know where it is going - why need to >digitize at all, just have two comparators? > >pigletYou can make time-to-digital converter by using a fast ADC to digitize a ramp or maybe some other waveform. The ADC is clocked by your local XO, and the ramp is started by some external event. The ADC samples can be processed to tell when the event started, measured in the local time frame. That's one way to answer the question "when was this box triggered?" -- John Larkin Highland Technology, Inc Science teaches us to doubt. Claude Bernard
Reply by ●August 26, 20202020-08-26
On Wed, 26 Aug 2020 08:23:06 -0400, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>On 2020-08-26 00:16, whit3rd wrote: >> On Tuesday, August 25, 2020 at 7:25:08 PM UTC-7, jla...@highlandsniptechnology.com wrote: >>> On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), "John Miles, KE5FX" >>> <jmiles@gmail.com> wrote: >>> >>>> On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote: >>>>> Does anybody know of one? I'd like to digitize 6 bits or so, really >>>>> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 >>>>> bits might work. >>>>> >> .... >>> It's a PLL, and lag slows down the loop dynamics. >>> >>> I start an LC oscillator when I get a trigger, and use it to time out >>> delays. The ADC is clocked from an OCXO and observes the waveform of >>> the triggered LC oscillator, and I close a loop to lock the LC to the >>> XO. Actually, the LC frequency is whatever it wants to be. The math >>> gets ugly. >> >> So, the LC is just an inaccurate copy of the XO? >>> >>> The sooner and tighter we can close the loop, the less the LC drifts. >> >> The LC has a high Q, I assume, and that means it has low phase noise, but >> you're steering it, which means you aren't getting the Q advantage and >> your phase noise includes artifacts due to corrections. >> >> Maybe downmix the LC oscillator against a filtered PLL (as the local oscillator) >> which gives a low-frequency error signal, easily measured. Any frequency/phase >> comparison/correction will take time according to the frequency resolution, >> though. Measure, and use the info for a correction afterwards, might be easier than >> control at HF in realtime. > >Pretty hard to accurately delay an asynchronous input by a microsecond >that way, especially with picosecond resolution. > >JL has discussed the instant-on LC oscillator here many times.It's a hobby. I did a couple of products with triggered delay-line oscillators, specifically coaxial ceramic resonators, but LC is better. HP did some nice boxes, like the 5370 time-interval counter, with delay-line oscillators. The 5370 manual is worth reading.> >A crystal oscillator is useless because you can't get at the interior >node of the equivalent LC circuit to hang a switch on it--you have to >put DC on the whole thing. That means that at trigger time there's a >big voltage step on the rest of the circuit (including the parallel >capacitance and the other crystal modes). That's bound to make the >first few cycles look different from subsequent ones, which will make >the timing indeterminate.HP made one delay generator box that did kick-start an XO when a trigger arrived. It was a nightmare and didn't last long. An XO is hard to start and hard to stop. I met a guy who worked on it. He was scarred for life.> >An LC triggered using a very low capacitance switch such as a pHEMT >basically shimmers into life as though it had been oscillating all the time.Right. It's a nice example of the "initial conditions" concept of differential equations. If you record all the voltages and currents of a circuit, you can restore them later, and it takes off as if time had been suspended. You can pause a Spice simulation, same idea.> >(I've never done it myself, but I do use crystal ring-down for >calibrating AM detectors. You have to ignore the first part of the >exponential decay for the same reason, and of course because the crystal >rings at its mechanical resonance, which is not where it was running at >the beginning.) > >Cheers > >Phil HobbsI'm just revisiting all the ways to make a DDG. New parts and new ideas happen. So do competitors. If I discover anything, I'll add it to the Wikipedia article. And SED should discuss electronics now and then. -- John Larkin Highland Technology, Inc Science teaches us to doubt. Claude Bernard
Reply by ●August 26, 20202020-08-26
On Wed, 26 Aug 2020 14:44:47 +0100, Chris <xxx.syseng.yyy@gfsys.co.uk> wrote:>On 08/26/20 03:24, jlarkin@highlandsniptechnology.com wrote: >> On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), "John Miles, KE5FX" >> <jmiles@gmail.com> wrote: >> >>> On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote: >>>> Does anybody know of one? I'd like to digitize 6 bits or so, really >>>> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 >>>> bits might work. >>>> >>>> Classic "flash" ADCs were fast, but needed 2^N comparators. >>> >>> What are you trying to do that can't wait a few clock cycles? >>> >>> -- john, KE5FX >> >> It's a PLL, and lag slows down the loop dynamics. >> >> I start an LC oscillator when I get a trigger, and use it to time out >> delays. The ADC is clocked from an OCXO and observes the waveform of >> the triggered LC oscillator, and I close a loop to lock the LC to the >> XO. Actually, the LC frequency is whatever it wants to be. The math >> gets ugly. >> >> The sooner and tighter we can close the loop, the less the LC drifts. >> >> There's a DAC too, but they're fast. >> >> I just found this: >> >> https://www.analog.com/en/products/adv7125.html >> >> Triple 8-bit DAC, 330 MHz, cheap. >> >> >> >> > >Can't you rethink this and find a way to gate an oscillator that is >always on, perhaps already locked to the ocxo ?. Present sketch of >a-d etc looks expensive and hard work... > >ChrisHP sort of did that. They ran a delay-line oscillator all the time, and phase-locked it to an XO. That kept it stable when not otherwise being used. When they got a trigger, a one-shot quenched it for 75 ns, then kicked it off again. Then a clever heterodyne system phase-locked it again, but preserved the original trigger time frame. This was done before fast ADCs and fast DACs existed. I did one product that used an XO, but rotated the phase just after trigger. It worked but was too tricky. Pepper's interrupted ramp idea is brilliant but is also tricky to implement. -- John Larkin Highland Technology, Inc Science teaches us to doubt. Claude Bernard
Reply by ●August 26, 20202020-08-26
On Wed, 26 Aug 2020 06:26:10 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>onsdag den 26. august 2020 kl. 15.01.37 UTC+2 skrev Michael Kellett: >> On 25/08/2020 19:34, John Larkin wrote: >> > >> > Does anybody know of one? I'd like to digitize 6 bits or so, really >> > fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 >> > bits might work. >> > >> > Classic "flash" ADCs were fast, but needed 2^N comparators. >> > >> Your favourite supplier has a dual 800Mhz one: >> MAX105ECS+ >> >> Mouser have stock. >> > >look at the datasheet, pipeline delay 5-6 cycles >That's not a lot of time, at 800 MHz. -- John Larkin Highland Technology, Inc Science teaches us to doubt. Claude Bernard
Reply by ●August 26, 20202020-08-26
On 08/26/20 16:00, jlarkin@highlandsniptechnology.com wrote:> On Wed, 26 Aug 2020 14:44:47 +0100, Chris<xxx.syseng.yyy@gfsys.co.uk> > wrote: > >> On 08/26/20 03:24, jlarkin@highlandsniptechnology.com wrote: >>> On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), "John Miles, KE5FX" >>> <jmiles@gmail.com> wrote: >>> >>>> On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote: >>>>> Does anybody know of one? I'd like to digitize 6 bits or so, really >>>>> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 >>>>> bits might work. >>>>> >>>>> Classic "flash" ADCs were fast, but needed 2^N comparators. >>>> >>>> What are you trying to do that can't wait a few clock cycles? >>>> >>>> -- john, KE5FX >>> >>> It's a PLL, and lag slows down the loop dynamics. >>> >>> I start an LC oscillator when I get a trigger, and use it to time out >>> delays. The ADC is clocked from an OCXO and observes the waveform of >>> the triggered LC oscillator, and I close a loop to lock the LC to the >>> XO. Actually, the LC frequency is whatever it wants to be. The math >>> gets ugly. >>> >>> The sooner and tighter we can close the loop, the less the LC drifts. >>> >>> There's a DAC too, but they're fast. >>> >>> I just found this: >>> >>> https://www.analog.com/en/products/adv7125.html >>> >>> Triple 8-bit DAC, 330 MHz, cheap. >>> >>> >>> >>> >> >> Can't you rethink this and find a way to gate an oscillator that is >> always on, perhaps already locked to the ocxo ?. Present sketch of >> a-d etc looks expensive and hard work... >> >> Chris > > HP sort of did that. They ran a delay-line oscillator all the time, > and phase-locked it to an XO. That kept it stable when not otherwise > being used. When they got a trigger, a one-shot quenched it for 75 ns, > then kicked it off again. Then a clever heterodyne system phase-locked > it again, but preserved the original trigger time frame. This was done > before fast ADCs and fast DACs existed. > > I did one product that used an XO, but rotated the phase just after > trigger. It worked but was too tricky. Pepper's interrupted ramp idea > is brilliant but is also tricky to implement. > > >The older high end HP spectrum analysers, the 8566 and 8568 did that as well. The marketing blurb called it lock and roll, locking the LO at start of sweep, then free running it open loop for the rest of the sweep. Allowed them to have a stable 10Hz resolution bw and 1KHz span at Ghz, in the late 1970's. I think what I was really saying was, was if the solution gets too complex, it maybe the wrong approach :-)...
Reply by ●August 26, 20202020-08-26
Am 26.08.20 um 18:29 schrieb Chris:> > The older high end HP spectrum analysers, the 8566 and 8568 did that > as well. The marketing blurb called it lock and roll, locking the > LO at start of sweep, then free running it open loop for the rest > of the sweep. Allowed them to have a stable 10Hz resolution bw and > 1KHz span at Ghz, in the late 1970's. > > I think what I was really saying was, was if the solution gets too > complex, it maybe the wrong approach :-)...IIRC, there was an article in the HP Journal about this. I think I have it on paper somewhere, but HP Journal is probably searchable somewhere. Cheers, Gerhard
Reply by ●August 26, 20202020-08-26
On 26/08/2020 5:58 pm, Gerhard Hoffmann wrote:> Am 26.08.20 um 18:29 schrieb Chris: > >> >> The older high end HP spectrum analysers, the 8566 and 8568 did that >> as well. The marketing blurb called it lock and roll, locking the >> LO at start of sweep, then free running it open loop for the rest >> of the sweep. Allowed them to have a stable 10Hz resolution bw and >> 1KHz span at Ghz, in the late 1970's. >> >> I think what I was really saying was, was if the solution gets too >> complex, it maybe the wrong approach :-)... > > IIRC, there was an article in the HP Journal about this. > I think I have it on paper somewhere, but HP Journal > is probably searchable somewhere. > > Cheers, GerhardThis one? <http://hparchive.com/Journals/HPJ-1978-06.pdf> piglet
Reply by ●August 26, 20202020-08-26
On 08/26/20 19:40, piglet wrote:> On 26/08/2020 5:58 pm, Gerhard Hoffmann wrote: >> Am 26.08.20 um 18:29 schrieb Chris: >> >>> >>> The older high end HP spectrum analysers, the 8566 and 8568 did that >>> as well. The marketing blurb called it lock and roll, locking the >>> LO at start of sweep, then free running it open loop for the rest >>> of the sweep. Allowed them to have a stable 10Hz resolution bw and >>> 1KHz span at Ghz, in the late 1970's. >>> >>> I think what I was really saying was, was if the solution gets too >>> complex, it maybe the wrong approach :-)... >> >> IIRC, there was an article in the HP Journal about this. >> I think I have it on paper somewhere, but HP Journal >> is probably searchable somewhere. >> >> Cheers, Gerhard > > This one? > <http://hparchive.com/Journals/HPJ-1978-06.pdf> > > piglet >I think i've seen that.Amazing bit of kit for it's time. HP really were at the peak of their game back then with tech prowess few, if any could match. Much of it still in use today. Last catalog price for the 8566, iirc, was 78,000 usd and yet, they sold bucketloads of them...
