onsdag den 26. august 2020 kl. 17.03.38 UTC+2 skrev jla...@highlandsniptechnology.com:> On Wed, 26 Aug 2020 06:26:10 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > > >onsdag den 26. august 2020 kl. 15.01.37 UTC+2 skrev Michael Kellett: > >> On 25/08/2020 19:34, John Larkin wrote: > >> > > >> > Does anybody know of one? I'd like to digitize 6 bits or so, really > >> > fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 > >> > bits might work. > >> > > >> > Classic "flash" ADCs were fast, but needed 2^N comparators. > >> > > >> Your favourite supplier has a dual 800Mhz one: > >> MAX105ECS+ > >> > >> Mouser have stock. > >> > > > >look at the datasheet, pipeline delay 5-6 cycles > > > > That's not a lot of time, at 800 MHz. >yeh and you probably have to keep up the clock rate anyway to not lose all the gain in processing as an example maxim also have dual 6 bit 90Mhz with 1 cycle pipeline, but looking at the datasheet it is more like one cycle for sampling, one cycle to the pins and then you need another cycle to get it into an fpga
non-pipelined fast ADC
Started by ●August 25, 2020
Reply by ●August 26, 20202020-08-26
Reply by ●August 26, 20202020-08-26
On 27/08/2020 00:37, jlarkin@highlandsniptechnology.com wrote:> On Wed, 26 Aug 2020 13:50:56 +0100, piglet <erichpwagner@hotmail.com> > wrote: > >> On 25/08/2020 10:33 pm, John Larkin wrote: >>> I'm digitizing a capacitive linear ramp anyhow! >>> >> >> Hmm? If it is linear then you know where it is going - why need to >> digitize at all, just have two comparators? >> >> piglet > > You can make time-to-digital converter by using a fast ADC to digitize > a ramp or maybe some other waveform. The ADC is clocked by your local > XO, and the ramp is started by some external event. The ADC samples > can be processed to tell when the event started, measured in the local > time frame. That's one way to answer the question "when was this box > triggered?" > > >Why not turn it around, and trigger the ADC with the external trigger signal, and make it take a sample of a RF sinewave locked to a crystal. Another ADC can take a sample of a RF cosine wave, and you can compute the trigger time. You won't need a fast ADC, just one with a fast sampling bandwidth which is a lot easier. If you need to resolve ambiguity about which cycle you got, you can also sample some slower waveforms too, which could be more sinewaves or digital. You might not need ADCs for those ones, e.g. you could latch the output of a gray-code counter, perhaps all of that in an FPGA.
Reply by ●August 26, 20202020-08-26
On Wednesday, August 26, 2020 at 7:53:38 AM UTC-7, jla...@highlandsniptechnology.com wrote:> On Wed, 26 Aug 2020 08:23:06 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > > >On 2020-08-26 00:16, whit3rd wrote: > >> On Tuesday, August 25, 2020 at 7:25:08 PM UTC-7, jla...@highlandsniptechnology.com wrote: > >>> On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), "John Miles, KE5FX" > >>> <jmiles@gmail.com> wrote: > >>> > >>>> On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote: > >>>>> Does anybody know of one? I'd like to digitize 6 bits or so, really > >>>>> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 > >>>>> bits might work. > >>>>> > >> .... > >>> It's a PLL, and lag slows down the loop dynamics. > >>> > >>> I start an LC oscillator when I get a trigger, and use it to time out > >>> delays. The ADC is clocked from an OCXO and observes the waveform of > >>> the triggered LC oscillator, and I close a loop to lock the LC to the > >>> XO. Actually, the LC frequency is whatever it wants to be. The math > >>> gets ugly> It's a hobby. I did a couple of products with triggered delay-line > oscillators, specifically coaxial ceramic resonators, but LC is > better. HP did some nice boxes, like the 5370 time-interval counter, > with delay-line oscillators. The 5370 manual is worth reading.But, the HP trick used tuned delayline oscillator frequency only because they were using a one-bit (latch) detector with their master oscillator clocking it, to detect the triggered oscillator phase. It had to be part-per-thousand locked to the master oscillator frequency to generate the phase-decode-event, with that one-bit detector, using (basically) one thousand one-bit detections to generate 10 useful bits of information. Your triggered LC doesn't have to match the master oscillator; all it has to do, is generate a sequence of events (or ADC samples) after the trigger event, then make a second trigger event with your master oscillator, and compare the ADC outputs for the phase shift... with some FFT capability, that works out totally independent of the LC frequency (except for the small delay - a few milliseconds?- between the two event/convert cycles). Instead of a thousand samples, you can do four-bit conversions on 256 clocks to get 1000 bits of information, and if you are tricky enough, it'll be more than ten useful bits.> >A crystal oscillator is useless because you can't get at the interior > >node of the equivalent LC circuit to hang a switch on it--Yeah, and damping the crystal to a halt between event captures is a BIG problem; damping a delay line is a problem. Damping an LC can be complete in under one cycle time, hardly any problem at all.
Reply by ●August 27, 20202020-08-27
On Thu, 27 Aug 2020 10:23:13 +1000, Chris Jones <lugnut808@spam.yahoo.com> wrote:>On 27/08/2020 00:37, jlarkin@highlandsniptechnology.com wrote: >> On Wed, 26 Aug 2020 13:50:56 +0100, piglet <erichpwagner@hotmail.com> >> wrote: >> >>> On 25/08/2020 10:33 pm, John Larkin wrote: >>>> I'm digitizing a capacitive linear ramp anyhow! >>>> >>> >>> Hmm? If it is linear then you know where it is going - why need to >>> digitize at all, just have two comparators? >>> >>> piglet >> >> You can make time-to-digital converter by using a fast ADC to digitize >> a ramp or maybe some other waveform. The ADC is clocked by your local >> XO, and the ramp is started by some external event. The ADC samples >> can be processed to tell when the event started, measured in the local >> time frame. That's one way to answer the question "when was this box >> triggered?" >> >> >> > >Why not turn it around, and trigger the ADC with the external trigger >signal, and make it take a sample of a RF sinewave locked to a crystal.That has been done, but the cheap and fast ADCs are pipeline types that need a continuous clock. And one ADC sampling one signal in that direction will have time ambiguities.>Another ADC can take a sample of a RF cosine wave, and you can compute >the trigger time. You won't need a fast ADC, just one with a fast >sampling bandwidth which is a lot easier.Right. You'd need two ADCs to resolve the ambiguity.> >If you need to resolve ambiguity about which cycle you got, you can also >sample some slower waveforms too, which could be more sinewaves or >digital. You might not need ADCs for those ones, e.g. you could latch >the output of a gray-code counter, perhaps all of that in an FPGA.That's all pretty complex. One ramp and one ADC works. -- John Larkin Highland Technology, Inc Science teaches us to doubt. Claude Bernard
Reply by ●August 28, 20202020-08-28
On 2020-08-26 14:47, Chris wrote:> On 08/26/20 19:40, piglet wrote: >> On 26/08/2020 5:58 pm, Gerhard Hoffmann wrote: >>> Am 26.08.20 um 18:29 schrieb Chris: >>> >>>> >>>> The older high end HP spectrum analysers, the 8566 and 8568 did that >>>> as well. The marketing blurb called it lock and roll, locking the >>>> LO at start of sweep, then free running it open loop for the rest >>>> of the sweep. Allowed them to have a stable 10Hz resolution bw and >>>> 1KHz span at Ghz, in the late 1970's. >>>> >>>> I think what I was really saying was, was if the solution gets too >>>> complex, it maybe the wrong approach :-)... >>> >>> IIRC, there was an article in the HP Journal about this. >>> I think I have it on paper somewhere, but HP Journal >>> is probably searchable somewhere. >>> >>> Cheers, Gerhard >> >> This one? >> <http://hparchive.com/Journals/HPJ-1978-06.pdf> >> >> piglet >> > > I think i've seen that.Amazing bit of kit for it's time. HP really > were at the peak of their game back then with tech prowess few, > if any could match. Much of it still in use today. > > Last catalog price for the 8566, iirc, was 78,000 usd and yet, > they sold bucketloads of them...Back in 1982, when I was working in satcom, we had a reasonably new Ailtech 757 (iirc). It was a manually-tuned gizmo that drifted around a bit before it warmed up. Then we got a swoopy new HP 8566A, later upgraded to a B. I was hooked. I had one for awhile at IBM, and about 6 years I bought a used one on eBay when I needed more top end than my previous 8568B. Its close-in phase noise is remarkably low on account of its YIG-tuned sweep oscillator. Its main drawback is that you can have the RF or microwave band displayed, but not both at once. Still, for 2 cents on the dollar one really can't complain too loudly. ;) Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
Reply by ●August 30, 20202020-08-30
On 2020-08-26 11:00, jlarkin@highlandsniptechnology.com wrote:> On Wed, 26 Aug 2020 14:44:47 +0100, Chris <xxx.syseng.yyy@gfsys.co.uk> > wrote: > >> On 08/26/20 03:24, jlarkin@highlandsniptechnology.com wrote: >>> On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), "John Miles, KE5FX" >>> <jmiles@gmail.com> wrote: >>> >>>> On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote: >>>>> Does anybody know of one? I'd like to digitize 6 bits or so, really >>>>> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 >>>>> bits might work. >>>>> >>>>> Classic "flash" ADCs were fast, but needed 2^N comparators. >>>> >>>> What are you trying to do that can't wait a few clock cycles? >>>> >>>> -- john, KE5FX >>> >>> It's a PLL, and lag slows down the loop dynamics. >>> >>> I start an LC oscillator when I get a trigger, and use it to time out >>> delays. The ADC is clocked from an OCXO and observes the waveform of >>> the triggered LC oscillator, and I close a loop to lock the LC to the >>> XO. Actually, the LC frequency is whatever it wants to be. The math >>> gets ugly. >>> >>> The sooner and tighter we can close the loop, the less the LC drifts. >>> >>> There's a DAC too, but they're fast. >>> >>> I just found this: >>> >>> https://www.analog.com/en/products/adv7125.html >>> >>> Triple 8-bit DAC, 330 MHz, cheap. >>> >>> >>> >>> >> >> Can't you rethink this and find a way to gate an oscillator that is >> always on, perhaps already locked to the ocxo ?. Present sketch of >> a-d etc looks expensive and hard work... >> >> Chris > > HP sort of did that. They ran a delay-line oscillator all the time, > and phase-locked it to an XO. That kept it stable when not otherwise > being used. When they got a trigger, a one-shot quenched it for 75 ns, > then kicked it off again. Then a clever heterodyne system phase-locked > it again, but preserved the original trigger time frame. This was done > before fast ADCs and fast DACs existed. > > I did one product that used an XO, but rotated the phase just after > trigger. It worked but was too tricky. Pepper's interrupted ramp idea > is brilliant but is also tricky to implement.Just rereading this thread. How about sampling the XO when the trigger appears, at the same time starting the LC. If you know which half-cycle the XO is on (which isn't too hard to do) you can compute the I/Q coefficients that make the initial phases of the LC and XO match. (For extra credit, two XOs locked in quadrature would allow you to always be on a good part of the slope, as well as disambiguating the quadrants.) That would work better in a DPLL, I expect. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
Reply by ●August 30, 20202020-08-30
On Sun, 30 Aug 2020 11:59:04 -0400, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>On 2020-08-26 11:00, jlarkin@highlandsniptechnology.com wrote: >> On Wed, 26 Aug 2020 14:44:47 +0100, Chris <xxx.syseng.yyy@gfsys.co.uk> >> wrote: >> >>> On 08/26/20 03:24, jlarkin@highlandsniptechnology.com wrote: >>>> On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), "John Miles, KE5FX" >>>> <jmiles@gmail.com> wrote: >>>> >>>>> On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote: >>>>>> Does anybody know of one? I'd like to digitize 6 bits or so, really >>>>>> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 >>>>>> bits might work. >>>>>> >>>>>> Classic "flash" ADCs were fast, but needed 2^N comparators. >>>>> >>>>> What are you trying to do that can't wait a few clock cycles? >>>>> >>>>> -- john, KE5FX >>>> >>>> It's a PLL, and lag slows down the loop dynamics. >>>> >>>> I start an LC oscillator when I get a trigger, and use it to time out >>>> delays. The ADC is clocked from an OCXO and observes the waveform of >>>> the triggered LC oscillator, and I close a loop to lock the LC to the >>>> XO. Actually, the LC frequency is whatever it wants to be. The math >>>> gets ugly. >>>> >>>> The sooner and tighter we can close the loop, the less the LC drifts. >>>> >>>> There's a DAC too, but they're fast. >>>> >>>> I just found this: >>>> >>>> https://www.analog.com/en/products/adv7125.html >>>> >>>> Triple 8-bit DAC, 330 MHz, cheap. >>>> >>>> >>>> >>>> >>> >>> Can't you rethink this and find a way to gate an oscillator that is >>> always on, perhaps already locked to the ocxo ?. Present sketch of >>> a-d etc looks expensive and hard work... >>> >>> Chris >> >> HP sort of did that. They ran a delay-line oscillator all the time, >> and phase-locked it to an XO. That kept it stable when not otherwise >> being used. When they got a trigger, a one-shot quenched it for 75 ns, >> then kicked it off again. Then a clever heterodyne system phase-locked >> it again, but preserved the original trigger time frame. This was done >> before fast ADCs and fast DACs existed. >> >> I did one product that used an XO, but rotated the phase just after >> trigger. It worked but was too tricky. Pepper's interrupted ramp idea >> is brilliant but is also tricky to implement. > >Just rereading this thread. How about sampling the XO when the trigger >appears, at the same time starting the LC. If you know which half-cycle >the XO is on (which isn't too hard to do) you can compute the I/Q >coefficients that make the initial phases of the LC and XO match. (For >extra credit, two XOs locked in quadrature would allow you to always be >on a good part of the slope, as well as disambiguating the quadrants.) > >That would work better in a DPLL, I expect. > >Cheers > >Phil HobbsI'm thinking along those same lines. If I can (quickly!) measure the phase angle between my XO and my triggered oscillator, I can seize the initial phase offset and close a loop on that. I did that a long time ago with all analog parts, but it was ugly... think compound sample-and-hold horrors. Rethinking it mostly digital, it looks interesting. Rather not say more in public. My triggered LC oscillator is great for a couple of microseconds, but is piling up drift and jitter. It needs to be locked to a good XO long-term. https://www.dropbox.com/s/18n2fhexbgazifi/Burst_Sine.JPG?raw=1 -- John Larkin Highland Technology, Inc Science teaches us to doubt. Claude Bernard
Reply by ●August 30, 20202020-08-30
Phil Hobbs wrote:> On 2020-08-26 11:00, jlarkin@highlandsniptechnology.com wrote: >> On Wed, 26 Aug 2020 14:44:47 +0100, Chris <xxx.syseng.yyy@gfsys.co.uk> >> wrote: >> >>> On 08/26/20 03:24, jlarkin@highlandsniptechnology.com wrote: >>>> On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), "John Miles, KE5FX" >>>> <jmiles@gmail.com> wrote: >>>> >>>>> On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote: >>>>>> Does anybody know of one? I'd like to digitize 6 bits or so, really >>>>>> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 >>>>>> bits might work. >>>>>> >>>>>> Classic "flash" ADCs were fast, but needed 2^N comparators. >>>>> >>>>> What are you trying to do that can't wait a few clock cycles? >>>>> >>>>> -- john, KE5FX >>>> >>>> It's a PLL, and lag slows down the loop dynamics. >>>> >>>> I start an LC oscillator when I get a trigger, and use it to time out >>>> delays. The ADC is clocked from an OCXO and observes the waveform of >>>> the triggered LC oscillator, and I close a loop to lock the LC to the >>>> XO. Actually, the LC frequency is whatever it wants to be. The math >>>> gets ugly. >>>> >>>> The sooner and tighter we can close the loop, the less the LC drifts. >>>> >>>> There's a DAC too, but they're fast. >>>> >>>> I just found this: >>>> >>>> https://www.analog.com/en/products/adv7125.html >>>> >>>> Triple 8-bit DAC, 330 MHz, cheap. >>>> >>>> >>>> >>>> >>> >>> Can't you rethink this and find a way to gate an oscillator that is >>> always on, perhaps already locked to the ocxo ?. Present sketch of >>> a-d etc looks expensive and hard work... >>> >>> Chris >> >> HP sort of did that. They ran a delay-line oscillator all the time, >> and phase-locked it to an XO. That kept it stable when not otherwise >> being used. When they got a trigger, a one-shot quenched it for 75 ns, >> then kicked it off again. Then a clever heterodyne system phase-locked >> it again, but preserved the original trigger time frame. This was done >> before fast ADCs and fast DACs existed. >> >> I did one product that used an XO, but rotated the phase just after >> trigger. It worked but was too tricky. Pepper's interrupted ramp idea >> is brilliant but is also tricky to implement. > > Just rereading this thread. How about sampling the XO when the trigger > appears, at the same time starting the LC. If you know which half-cycle > the XO is on (which isn't too hard to do) you can compute the I/Q > coefficients that make the initial phases of the LC and XO match. (For > extra credit, two XOs locked in quadrature would allow you to always be > on a good part of the slope, as well as disambiguating the quadrants.) > > That would work better in a DPLL, I expect. >It would *only* work if your PLL regime was rock solid. I've been out of it for a while, but if timing of the digital waveforms I've dealt with got smashed by ... things, you'd have to completely reaquire any nodes subject to it. I wrote the state machines for the analog and DPLLs ( why not both ?:) for the base station. It wasn't straightforward. And in my faulty recollection, it mainly just got nodes back online faster. Hopefully that was all just noise, which would be lower in this use case.> Cheers > > Phil Hobbs > >-- Les Cargill
Reply by ●August 30, 20202020-08-30
jlarkin@highlandsniptechnology.com wrote:> On Sun, 30 Aug 2020 11:59:04 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> On 2020-08-26 11:00, jlarkin@highlandsniptechnology.com wrote: >>> On Wed, 26 Aug 2020 14:44:47 +0100, Chris <xxx.syseng.yyy@gfsys.co.uk> >>> wrote: >>> >>>> On 08/26/20 03:24, jlarkin@highlandsniptechnology.com wrote: >>>>> On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), "John Miles, KE5FX" >>>>> <jmiles@gmail.com> wrote: >>>>> >>>>>> On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote: >>>>>>> Does anybody know of one? I'd like to digitize 6 bits or so, really >>>>>>> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 >>>>>>> bits might work. >>>>>>> >>>>>>> Classic "flash" ADCs were fast, but needed 2^N comparators. >>>>>> >>>>>> What are you trying to do that can't wait a few clock cycles? >>>>>> >>>>>> -- john, KE5FX >>>>> >>>>> It's a PLL, and lag slows down the loop dynamics. >>>>> >>>>> I start an LC oscillator when I get a trigger, and use it to time out >>>>> delays. The ADC is clocked from an OCXO and observes the waveform of >>>>> the triggered LC oscillator, and I close a loop to lock the LC to the >>>>> XO. Actually, the LC frequency is whatever it wants to be. The math >>>>> gets ugly. >>>>> >>>>> The sooner and tighter we can close the loop, the less the LC drifts. >>>>> >>>>> There's a DAC too, but they're fast. >>>>> >>>>> I just found this: >>>>> >>>>> https://www.analog.com/en/products/adv7125.html >>>>> >>>>> Triple 8-bit DAC, 330 MHz, cheap. >>>>> >>>>> >>>>> >>>>> >>>> >>>> Can't you rethink this and find a way to gate an oscillator that is >>>> always on, perhaps already locked to the ocxo ?. Present sketch of >>>> a-d etc looks expensive and hard work... >>>> >>>> Chris >>> >>> HP sort of did that. They ran a delay-line oscillator all the time, >>> and phase-locked it to an XO. That kept it stable when not otherwise >>> being used. When they got a trigger, a one-shot quenched it for 75 ns, >>> then kicked it off again. Then a clever heterodyne system phase-locked >>> it again, but preserved the original trigger time frame. This was done >>> before fast ADCs and fast DACs existed. >>> >>> I did one product that used an XO, but rotated the phase just after >>> trigger. It worked but was too tricky. Pepper's interrupted ramp idea >>> is brilliant but is also tricky to implement. >> >> Just rereading this thread. How about sampling the XO when the trigger >> appears, at the same time starting the LC. If you know which half-cycle >> the XO is on (which isn't too hard to do) you can compute the I/Q >> coefficients that make the initial phases of the LC and XO match. (For >> extra credit, two XOs locked in quadrature would allow you to always be >> on a good part of the slope, as well as disambiguating the quadrants.) >> >> That would work better in a DPLL, I expect. >> >> Cheers >> >> Phil Hobbs > > I'm thinking along those same lines. If I can (quickly!) measure the > phase angle between my XO and my triggered oscillator, I can seize the > initial phase offset and close a loop on that. I did that a long time > ago with all analog parts, but it was ugly... think compound > sample-and-hold horrors. Rethinking it mostly digital, it looks > interesting. Rather not say more in public. > > My triggered LC oscillator is great for a couple of microseconds, but > is piling up drift and jitter. It needs to be locked to a good XO > long-term. > > https://www.dropbox.com/s/18n2fhexbgazifi/Burst_Sine.JPG?raw=1 > > >Sigma-C is a thing... -- Les Cargill
Reply by ●August 30, 20202020-08-30
On 2020-08-30 13:51, Les Cargill wrote:> Phil Hobbs wrote: >> On 2020-08-26 11:00, jlarkin@highlandsniptechnology.com wrote: >>> On Wed, 26 Aug 2020 14:44:47 +0100, Chris <xxx.syseng.yyy@gfsys.co.uk> >>> wrote: >>> >>>> On 08/26/20 03:24, jlarkin@highlandsniptechnology.com wrote: >>>>> On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), "John Miles, KE5FX" >>>>> <jmiles@gmail.com> wrote: >>>>> >>>>>> On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote: >>>>>>> Does anybody know of one? I'd like to digitize 6 bits or so, really >>>>>>> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 >>>>>>> bits might work. >>>>>>> >>>>>>> Classic "flash" ADCs were fast, but needed 2^N comparators. >>>>>> >>>>>> What are you trying to do that can't wait a few clock cycles? >>>>>> >>>>>> -- john, KE5FX >>>>> >>>>> It's a PLL, and lag slows down the loop dynamics. >>>>> >>>>> I start an LC oscillator when I get a trigger, and use it to time out >>>>> delays. The ADC is clocked from an OCXO and observes the waveform of >>>>> the triggered LC oscillator, and I close a loop to lock the LC to the >>>>> XO. Actually, the LC frequency is whatever it wants to be. The math >>>>> gets ugly. >>>>> >>>>> The sooner and tighter we can close the loop, the less the LC drifts. >>>>> >>>>> There's a DAC too, but they're fast. >>>>> >>>>> I just found this: >>>>> >>>>> https://www.analog.com/en/products/adv7125.html >>>>> >>>>> Triple 8-bit DAC, 330 MHz, cheap. >>>>> >>>>> >>>>> >>>>> >>>> >>>> Can't you rethink this and find a way to gate an oscillator that is >>>> always on, perhaps already locked to the ocxo ?. Present sketch of >>>> a-d etc looks expensive and hard work... >>>> >>>> Chris >>> >>> HP sort of did that. They ran a delay-line oscillator all the time, >>> and phase-locked it to an XO. That kept it stable when not otherwise >>> being used. When they got a trigger, a one-shot quenched it for 75 ns, >>> then kicked it off again. Then a clever heterodyne system phase-locked >>> it again, but preserved the original trigger time frame. This was done >>> before fast ADCs and fast DACs existed. >>> >>> I did one product that used an XO, but rotated the phase just after >>> trigger. It worked but was too tricky. Pepper's interrupted ramp idea >>> is brilliant but is also tricky to implement. >> >> Just rereading this thread. How about sampling the XO when the >> trigger appears, at the same time starting the LC. If you know which >> half-cycle the XO is on (which isn't too hard to do) you can compute >> the I/Q coefficients that make the initial phases of the LC and XO >> match. (For extra credit, two XOs locked in quadrature would allow >> you to always be on a good part of the slope, as well as >> disambiguating the quadrants.) >> >> That would work better in a DPLL, I expect. >> > > It would *only* work if your PLL regime was rock solid. I've > been out of it for a while, but if timing of the digital waveforms I've > dealt with got smashed by ... things, you'd have to completely reaquire > any nodes subject to it. > > I wrote the state machines for the analog and DPLLs ( why not both ?:) > for the base station. It wasn't straightforward. And in my faulty > recollection, it mainly just got nodes back online faster. > > Hopefully that was all just noise, which would be lower in this use case.In a delay generator, the user can tap-dance on the input any way he likes, but you don't have to pay attention unless you choose to. ;) Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
