Forums

non-pipelined fast ADC

Started by John Larkin August 25, 2020
Does anybody know of one? I'd like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.

Classic "flash" ADCs were fast, but needed 2^N comparators.

tirsdag den 25. august 2020 kl. 20.34.31 UTC+2 skrev John Larkin:
> Does anybody know of one? I'd like to digitize 6 bits or so, really > fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 > bits might work. > > Classic "flash" ADCs were fast, but needed 2^N comparators.
how fast is really fast?
On Tue, 25 Aug 2020 12:12:32 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>tirsdag den 25. august 2020 kl. 20.34.31 UTC+2 skrev John Larkin: >> Does anybody know of one? I'd like to digitize 6 bits or so, really >> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 >> bits might work. >> >> Classic "flash" ADCs were fast, but needed 2^N comparators. > >how fast is really fast?
60 to maybe 150 MHz. The faster it is, the fewer bits I'd need. I guess I could overkill with a really fast ADC, 250 MHz maybe, and live with the pipeline delay and price. The really fast DACs are pipelined nowadays too. I once worked for an outfit that sold a CAMAC 6-bit, 50 MHz ADC that was made from parts, namely 63 comparators and a bunch of ECL. It didn't last long, as integrated ADCs got good soon after.
On 2020-08-25 14:34, John Larkin wrote:
> > Does anybody know of one? I'd like to digitize 6 bits or so, really > fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 > bits might work. > > Classic "flash" ADCs were fast, but needed 2^N comparators. >
Plus they had fixed-pattern jitter due to the different RC delays on the resistor string. How fast is fast? Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
tirsdag den 25. august 2020 kl. 21.29.41 UTC+2 skrev John Larkin:
> On Tue, 25 Aug 2020 12:12:32 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > > >tirsdag den 25. august 2020 kl. 20.34.31 UTC+2 skrev John Larkin: > >> Does anybody know of one? I'd like to digitize 6 bits or so, really > >> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 > >> bits might work. > >> > >> Classic "flash" ADCs were fast, but needed 2^N comparators. > > > >how fast is really fast? > > 60 to maybe 150 MHz. > > The faster it is, the fewer bits I'd need. I guess I could overkill > with a really fast ADC, 250 MHz maybe, and live with the pipeline > delay and price. The really fast DACs are pipelined nowadays too. > > I once worked for an outfit that sold a CAMAC 6-bit, 50 MHz ADC that > was made from parts, namely 63 comparators and a bunch of ECL. It > didn't last long, as integrated ADCs got good soon after.
how terrible would a string of resistors and a bunch of LVDS recievers on an FPGA be? a couple volt divided by 16/32 is right around 100mV minimum diff voltage for an LVDS receiver
On 8/25/2020 2:34 PM, John Larkin wrote:
> > Does anybody know of one? I'd like to digitize 6 bits or so, really > fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 > bits might work. > > Classic "flash" ADCs were fast, but needed 2^N comparators. >
Low value resistors, fast NAND gates: <http://zpostbox.ru/simple_adc.html>
On 8/25/2020 4:15 PM, bitrex wrote:
> On 8/25/2020 2:34 PM, John Larkin wrote: >> >> Does anybody know of one? I'd like to digitize 6 bits or so, really >> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 >> bits might work. >> >> Classic "flash" ADCs were fast, but needed 2^N comparators. >> > > Low value resistors, fast NAND gates: > > <http://zpostbox.ru/simple_adc.html>
I think NAND tends to have lower intrinsic propagation delay than NOR. maybe it's the other way round. idk.
On Tue, 25 Aug 2020 13:12:50 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>tirsdag den 25. august 2020 kl. 21.29.41 UTC+2 skrev John Larkin: >> On Tue, 25 Aug 2020 12:12:32 -0700 (PDT), Lasse Langwadt Christensen >> <langwadt@fonz.dk> wrote: >> >> >tirsdag den 25. august 2020 kl. 20.34.31 UTC+2 skrev John Larkin: >> >> Does anybody know of one? I'd like to digitize 6 bits or so, really >> >> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 >> >> bits might work. >> >> >> >> Classic "flash" ADCs were fast, but needed 2^N comparators. >> > >> >how fast is really fast? >> >> 60 to maybe 150 MHz. >> >> The faster it is, the fewer bits I'd need. I guess I could overkill >> with a really fast ADC, 250 MHz maybe, and live with the pipeline >> delay and price. The really fast DACs are pipelined nowadays too. >> >> I once worked for an outfit that sold a CAMAC 6-bit, 50 MHz ADC that >> was made from parts, namely 63 comparators and a bunch of ECL. It >> didn't last long, as integrated ADCs got good soon after. > >how terrible would a string of resistors and a bunch of LVDS recievers >on an FPGA be? > >a couple volt divided by 16/32 is right around 100mV minimum diff voltage >for an LVDS receiver
Interesting idea. If we use a ZYNQ, we'll have a zillion pins to spare. A 4-bit, 250 MHz flash ADC wouldn't be unreasonable.
tirsdag den 25. august 2020 kl. 22.47.42 UTC+2 skrev John Larkin:
> On Tue, 25 Aug 2020 13:12:50 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > > >tirsdag den 25. august 2020 kl. 21.29.41 UTC+2 skrev John Larkin: > >> On Tue, 25 Aug 2020 12:12:32 -0700 (PDT), Lasse Langwadt Christensen > >> <langwadt@fonz.dk> wrote: > >> > >> >tirsdag den 25. august 2020 kl. 20.34.31 UTC+2 skrev John Larkin: > >> >> Does anybody know of one? I'd like to digitize 6 bits or so, really > >> >> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 > >> >> bits might work. > >> >> > >> >> Classic "flash" ADCs were fast, but needed 2^N comparators. > >> > > >> >how fast is really fast? > >> > >> 60 to maybe 150 MHz. > >> > >> The faster it is, the fewer bits I'd need. I guess I could overkill > >> with a really fast ADC, 250 MHz maybe, and live with the pipeline > >> delay and price. The really fast DACs are pipelined nowadays too. > >> > >> I once worked for an outfit that sold a CAMAC 6-bit, 50 MHz ADC that > >> was made from parts, namely 63 comparators and a bunch of ECL. It > >> didn't last long, as integrated ADCs got good soon after. > > > >how terrible would a string of resistors and a bunch of LVDS recievers > >on an FPGA be? > > > >a couple volt divided by 16/32 is right around 100mV minimum diff voltage > >for an LVDS receiver > > Interesting idea. If we use a ZYNQ, we'll have a zillion pins to > spare. A 4-bit, 250 MHz flash ADC wouldn't be unreasonable.
driving it might be interesting, I think each pad is ~8pf
On Tue, 25 Aug 2020 14:22:41 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>tirsdag den 25. august 2020 kl. 22.47.42 UTC+2 skrev John Larkin: >> On Tue, 25 Aug 2020 13:12:50 -0700 (PDT), Lasse Langwadt Christensen >> <langwadt@fonz.dk> wrote: >> >> >tirsdag den 25. august 2020 kl. 21.29.41 UTC+2 skrev John Larkin: >> >> On Tue, 25 Aug 2020 12:12:32 -0700 (PDT), Lasse Langwadt Christensen >> >> <langwadt@fonz.dk> wrote: >> >> >> >> >tirsdag den 25. august 2020 kl. 20.34.31 UTC+2 skrev John Larkin: >> >> >> Does anybody know of one? I'd like to digitize 6 bits or so, really >> >> >> fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4 >> >> >> bits might work. >> >> >> >> >> >> Classic "flash" ADCs were fast, but needed 2^N comparators. >> >> > >> >> >how fast is really fast? >> >> >> >> 60 to maybe 150 MHz. >> >> >> >> The faster it is, the fewer bits I'd need. I guess I could overkill >> >> with a really fast ADC, 250 MHz maybe, and live with the pipeline >> >> delay and price. The really fast DACs are pipelined nowadays too. >> >> >> >> I once worked for an outfit that sold a CAMAC 6-bit, 50 MHz ADC that >> >> was made from parts, namely 63 comparators and a bunch of ECL. It >> >> didn't last long, as integrated ADCs got good soon after. >> > >> >how terrible would a string of resistors and a bunch of LVDS recievers >> >on an FPGA be? >> > >> >a couple volt divided by 16/32 is right around 100mV minimum diff voltage >> >for an LVDS receiver >> >> Interesting idea. If we use a ZYNQ, we'll have a zillion pins to >> spare. A 4-bit, 250 MHz flash ADC wouldn't be unreasonable. > >driving it might be interesting, I think each pad is ~8pf
I'm digitizing a capacitive linear ramp anyhow! I think the 8 pF is the max spec. They are very vague.