"John Larkin" <jjlarkin@highlandtechnology.com> wrote in message news:mpbdsc5sivu4vc47h5t08qbj8uoahcjvms@4ax.com...> Except for the soft corners, their plateau is horizontal. >Inflection point != flat. The same can be said of mine, https://www.seventransistorlabs.com/Images/STP19NM50N%201.045mA%20Gate%20Charge%20400V%2030.1%20ohm%20Drain.png I'm sure that's not quantization, it's actually flat. ;-)> Different mosfets, made on different processes, can be expected to > have different diffusion profiles and different C-V curves. Some slope > very gently, some have steep drop-offs. Like different diodes have > very different C-V curves. I hardly think that a bunch of mosfet > makers are publishing erroneous C-V curves; they have expensive test > gear.A bunch, perhaps not. ST, definitely. https://www.seventransistorlabs.com/Images/STP19NM50N%20Coss%20Comparison.png FYI, there's only one kind of diode I'm aware of, with an m that large (IIRC, even hyperabrupt varactors are only m ~ 2). The extreme dropoff (albeit not as extreme as their plot) is characteristic of the SuperJunction structure. Here's such a diode: http://www.vishay.com/docs/87700/vt5202-m3.pdf Somewhat niche value, but very nice if you need it. Diffusion profiles have very little to do with it. The active stuff on the top of the MOSFET (epitaxy) is physically shut off from the drain terminal after maybe 20V, because of how they've shaped the source, substrate and their doping profiles, and the SuperJunction pillars. You can't make depletion that aggressive with diffusion!> A Spice model of transition gate and drain volts usually has a flat > plateau, as the drain slews in its transition and feeds back into the > gate through Crss. I don't think that decades of academic and industry > Spice mosfet models are lying.So my pictures are made up? Because someone's got it wrong. Is it the SPICE model or the oscilloscope?> The data sheets are usually unclear about how they measure the gate > charge waveforms. They specify Vd and Id, but is the drain fed by a > constant-current source, or a resistor? >IR seems to suggest CCS (as in your other post). ST uses essentially the same circuit. IXYS doesn't say. I checked the appnotes. They don't seem to have any publications since 2003 or thereabouts, which means their appnotes don't even cover the debut of SuperJunction parts. Shame. I think that I've seen the measurement done with a load resistor (which is what I've done). Can't find an example to confirm that right now. In any case, the SPICE model was measured with the same method.> A little rounding of the plateau corners doesn't matter much in real > life.Reality is continuous. Seems to matter an awful lot... Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
MOSFET WTF
Started by ●September 23, 2017
Reply by ●September 23, 20172017-09-23
Reply by ●September 23, 20172017-09-23
On Sat, 23 Sep 2017 20:14:00 -0500, "Tim Williams" <tmoranwms@gmail.com> wrote:>"John Larkin" <jjlarkin@highlandtechnology.com> wrote in message >news:mpbdsc5sivu4vc47h5t08qbj8uoahcjvms@4ax.com... >> Except for the soft corners, their plateau is horizontal. >> > >Inflection point != flat. The same can be said of mine, >https://www.seventransistorlabs.com/Images/STP19NM50N%201.045mA%20Gate%20Charge%20400V%2030.1%20ohm%20Drain.png >I'm sure that's not quantization, it's actually flat. ;-) > > >> Different mosfets, made on different processes, can be expected to >> have different diffusion profiles and different C-V curves. Some slope >> very gently, some have steep drop-offs. Like different diodes have >> very different C-V curves. I hardly think that a bunch of mosfet >> makers are publishing erroneous C-V curves; they have expensive test >> gear. > >A bunch, perhaps not. ST, definitely. >https://www.seventransistorlabs.com/Images/STP19NM50N%20Coss%20Comparison.png > >FYI, there's only one kind of diode I'm aware of, with an m that large >(IIRC, even hyperabrupt varactors are only m ~ 2). The extreme dropoff >(albeit not as extreme as their plot) is characteristic of the SuperJunction >structure. > >Here's such a diode: >http://www.vishay.com/docs/87700/vt5202-m3.pdf >Somewhat niche value, but very nice if you need it. > >Diffusion profiles have very little to do with it. The active stuff on the >top of the MOSFET (epitaxy) is physically shut off from the drain terminal >after maybe 20V, because of how they've shaped the source, substrate and >their doping profiles, and the SuperJunction pillars. You can't make >depletion that aggressive with diffusion! > > >> A Spice model of transition gate and drain volts usually has a flat >> plateau, as the drain slews in its transition and feeds back into the >> gate through Crss. I don't think that decades of academic and industry >> Spice mosfet models are lying. > >So my pictures are made up? > >Because someone's got it wrong. Is it the SPICE model or the oscilloscope? > > >> The data sheets are usually unclear about how they measure the gate >> charge waveforms. They specify Vd and Id, but is the drain fed by a >> constant-current source, or a resistor? >> > >IR seems to suggest CCS (as in your other post). ST uses essentially the >same circuit. > >IXYS doesn't say. I checked the appnotes. They don't seem to have any >publications since 2003 or thereabouts, which means their appnotes don't >even cover the debut of SuperJunction parts. Shame. > >I think that I've seen the measurement done with a load resistor (which is >what I've done). Can't find an example to confirm that right now. > >In any case, the SPICE model was measured with the same method. > > >> A little rounding of the plateau corners doesn't matter much in real >> life. > >Reality is continuous. Seems to matter an awful lot... > >TimYou had a drain resistor, no? See my post below. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by ●September 23, 20172017-09-23
On Saturday, September 23, 2017 at 6:14:09 PM UTC-7, Tim Williams wrote: ...> https://www.seventransistorlabs.com/Images/STP19NM50N%201.045mA%20Gate%20Charge%20400V%2030.1%20ohm%20Drain.png > I'm sure that's not quantization, it's actually flat. ;-)... Is channel 1 the drain? If so how come the drain is at zero volts before the Miller plateau on the gate (Ch3?) If so there is no feedback through Cgd at that time. thanks kevin
Reply by ●September 24, 20172017-09-24
"John Larkin" <jjlarkin@highlandtechnology.com> wrote in message news:fr2esctegpl0lkci0se1vust4lf3ssrngm@4ax.com...> You had a drain resistor, no? See my post below. >Uh, so? On a related note, ST does actually have a document showing resistor load. http://www.st.com/content/ccc/resource/technical/document/user_manual/04/4d/16/0d/d9/49/46/29/DM00064632.pdf/files/DM00064632.pdf/jcr:content/translations/en.DM00064632.pdf They also describe the model, but don't happen to justify any of it. They also don't plot the model's capacitances... gee, I wonder why? :-) Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
Reply by ●September 24, 20172017-09-24
On a sunny day (Sat, 23 Sep 2017 13:10:09 -0700) it happened John Larkin <jjlarkin@highlandtechnology.com> wrote in <nofdschc7jenp50pd178ck4tnv48hf6a59@4ax.com>:>On Fri, 22 Sep 2017 23:21:30 -0500, "Tim Williams" ><tmoranwms@gmail.com> wrote: > >>VDMOS nonlinear capacitance is modeled in terms of Vgd. >> >>Too bad a real MOSFET doesn't show a steplike change in Ciss as Vgd changes >>sign. (This is easily demonstrated with the gate charge test circuit, >>watching the waveform at low Vdd. The cutoff slope depends only on Vds, not >>Vgd.) >> >>So many decades of bullshit to sift through... >> >>Tim > >Fun quiz: find out how many things are wrong with this circuit: > >https://www.dropbox.com/s/54oianu85weidb3/IRFL210_Qg_Ckt.jpg?raw=1I like it ;-)
Reply by ●September 24, 20172017-09-24
On Saturday, September 23, 2017 at 10:10:19 PM UTC+2, John Larkin wrote:> On Fri, 22 Sep 2017 23:21:30 -0500, "Tim Williams" > <tmoranwms@gmail.com> wrote: > > >VDMOS nonlinear capacitance is modeled in terms of Vgd. > > > >Too bad a real MOSFET doesn't show a steplike change in Ciss as Vgd changes > >sign. (This is easily demonstrated with the gate charge test circuit, > >watching the waveform at low Vdd. The cutoff slope depends only on Vds, not > >Vgd.) > > > >So many decades of bullshit to sift through... > > > >Tim > > Fun quiz: find out how many things are wrong with this circuit: > > https://www.dropbox.com/s/54oianu85weidb3/IRFL210_Qg_Ckt.jpg?raw=1 >What's wrong with it? If you set the Vgs right for the top MOSFET, then the current is almost perfect except for the last couple of volts drain-source Cheers Klaus
Reply by ●September 24, 20172017-09-24
On Sun, 24 Sep 2017 01:51:02 -0500, "Tim Williams" <tmoranwms@gmail.com> wrote:>"John Larkin" <jjlarkin@highlandtechnology.com> wrote in message >news:fr2esctegpl0lkci0se1vust4lf3ssrngm@4ax.com... >> You had a drain resistor, no? See my post below. >> > >Uh, so?Looks like different manufacturers use different load circuits, and most don't reveal it. That will change the shapes of the curves, but not much affect total Qg.> >On a related note, ST does actually have a document showing resistor load. >http://www.st.com/content/ccc/resource/technical/document/user_manual/04/4d/16/0d/d9/49/46/29/DM00064632.pdf/files/DM00064632.pdf/jcr:content/translations/en.DM00064632.pdf >They also describe the model, but don't happen to justify any of it. They >also don't plot the model's capacitances... gee, I wonder why? :-)Fig 12?> >TimFig 14 includes Vd and Id, which is not usually on the gate-charge curve. Interesting things going on there. The self-heating model, fig 1, is nice. I've done that in power amps, measured heat sink temp, fet voltage, and fet current, and run a realtime Tj simulation as the shutdown mechanism. That lets one safely push the fets a lot harder than any simple current limit. We derive our thermal models by blowing up fets. We're doing that again now, in our SSR module, but we're protecting a wirewound resistor, not the fets. A dual RC is probably a decent model. I'm accumulating a nice collection of exploded resistors. Not to change the subject (me?) but I'm testing a wirewound resistor this weekend, at 20J per shot. Viewed under my Mantis, every shot reveals the wire coil, under the silicone coating, by a brief red spiral-shaped flash. But with the illumination turned off, in the dark, there is nothing visible. So it's not incandescence, but a transient change in the chemistry of the coating? -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by ●September 24, 20172017-09-24
On Saturday, September 23, 2017 at 12:25:24 PM UTC-7, John Larkin wrote: ...> Except for the soft corners, their plateau is horizontal. >... The plateau will not be quite horizontal - its slope will depend upon the voltage gain which depends upon the gm of the FET and the effective resistance at the drain circuit. There has to be enough gate voltage change in the plateau region to cause the drain voltage to change to counteract the charge being suppled by the gate circuit to to the other end of Cgd. The test circuits with a constant current sourcing for the drain will have the most gain, the ones using another identical device as the CC source and the ones using a resistor will have decreasing order of gain and larger gate voltage slope on the plateau. The one using an identical device seems a reasonable standard as the gain will be "gm*Ro/2". kevin
Reply by ●September 24, 20172017-09-24
On Sun, 24 Sep 2017 10:07:51 -0700 (PDT), kevin93 <kevin@whitedigs.com> wrote:>On Saturday, September 23, 2017 at 12:25:24 PM UTC-7, John Larkin wrote: >... > >> Except for the soft corners, their plateau is horizontal. >> >... > >The plateau will not be quite horizontal - its slope will depend upon the voltage gain which depends upon the gm of the FET and the effective resistance at the drain circuit.All the capacitances are changing in real time, too. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by ●September 24, 20172017-09-24
On Sunday, September 24, 2017 at 2:15:37 PM UTC-7, John Larkin wrote:> On Sun, 24 Sep 2017 10:07:51 -0700 (PDT), kevin93 > >... > > > >The plateau will not be quite horizontal - its slope will depend upon the voltage gain which depends upon the gm of the FET and the effective resistance at the drain circuit. > > All the capacitances are changing in real time, too. >... Yup, agreed This is a curve I measured for a BSS138 at low current - there was about 160mV change in gate drive during the run down. There is a fair amount of curvature of the drain voltage slope. I used your technique of documenting it within the photo - good idea. https://i.imgur.com/xxG9CC8.jpg kevin
