VDMOS nonlinear capacitance is modeled in terms of Vgd. Too bad a real MOSFET doesn't show a steplike change in Ciss as Vgd changes sign. (This is easily demonstrated with the gate charge test circuit, watching the waveform at low Vdd. The cutoff slope depends only on Vds, not Vgd.) So many decades of bullshit to sift through... Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
MOSFET WTF
Started by ●September 23, 2017
Reply by ●September 23, 20172017-09-23
On a sunny day (Fri, 22 Sep 2017 23:21:30 -0500) it happened "Tim Williams" <tmoranwms@gmail.com> wrote in <oq4ngf$tce$1@dont-email.me>:>VDMOS nonlinear capacitance is modeled in terms of Vgd. > >Too bad a real MOSFET doesn't show a steplike change in Ciss as Vgd changes >sign. (This is easily demonstrated with the gate charge test circuit, >watching the waveform at low Vdd. The cutoff slope depends only on Vds, not >Vgd.) > >So many decades of bullshit to sift through... > >Timsimulations are not reality, pokemon is not real. NASA has never been on alien planets. Not every circuit is a Baxandal GlowBallWarming is real. Roger Rabit is fake.>-- >Seven Transistor Labs, LLC >Electrical Engineering Consultation and Contract Design >Website: http://seventransistorlabs.com > >
Reply by ●September 23, 20172017-09-23
On Fri, 22 Sep 2017 23:21:30 -0500, "Tim Williams" <tmoranwms@gmail.com> wrote:>VDMOS nonlinear capacitance is modeled in terms of Vgd. > >Too bad a real MOSFET doesn't show a steplike change in Ciss as Vgd changes >sign. (This is easily demonstrated with the gate charge test circuit, >watching the waveform at low Vdd. The cutoff slope depends only on Vds, not >Vgd.) > >So many decades of bullshit to sift through... > >TimAre you referring to the flat spot in fig 16? https://www.fairchildsemi.com/datasheets/FD/FDD86367_F085.pdf -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by ●September 23, 20172017-09-23
On 2017/09/22 9:21 PM, Tim Williams wrote:> VDMOS nonlinear capacitance is modeled in terms of Vgd. > > Too bad a real MOSFET doesn't show a steplike change in Ciss as Vgd > changes sign. (This is easily demonstrated with the gate charge test > circuit, watching the waveform at low Vdd. The cutoff slope depends > only on Vds, not Vgd.) > > So many decades of bullshit to sift through... > > Tim >Isn't that why you breadboard something after simulating it - to make sure the simulation matches the real world... So many models fail the reality test. Just ask HVAC engineers trying to model how heat flows in a building when you add in the outside world! John :-#)#
Reply by ●September 23, 20172017-09-23
"Jan Panteltje" <pNa0nStpealmtje@yahoo.com> wrote in message news:oq56m9$1o1$1@gioia.aioe.org...> simulations are not reality, pokemon is not real. >I know, that's why I'm trying to do Crysis! Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
Reply by ●September 23, 20172017-09-23
"John Robertson" <spam@flippers.com> wrote in message news:lN6dndGq5feMDVvEnZ2dnUU7-YGdnZ2d@giganews.com...>Isn't that why you breadboard something after simulating it - to makesure the simulation matches the real world... So many models fail the reality test.>Thing is, they could've constructed this model realistically, just by changing around a few things even. The model structure is old, probably since the 90s, and no one thought to question it for two or three decades. This is what the goofy model does: https://www.seventransistorlabs.com/Images/STW21NM50N_Gate_Charge.png This is Vgs charged with 1mA, set to an initial -10V using a switch. Vdd is swept from 0 to 10V in 2V steps. Vdd goes to drain via 28 ohms. What they got right: Ciss changes with Vds. The slope below the Miller plateau is different from the slope above (where Vds = 0, because the transistor is shorting out the load resistor). What they got wrong: Ciss (below Miller) is supposed to change slope. Over the whole Vgs range, from negative voltage until conduction begins. The slope is very nearly linear. (This could be the basis for a fantastic parametric amplifier.) As Vds rises, the slope rises (Ciss drops), and the Miller step gets longer. (The model does not reproduce Qg(Vdd) very well.) The most ugly part is how the Vds=0 slope encroaches on the Vds>0 slope. At a glance, it looks like Miller step, and it's just slowing down because it's beginning to conduct, right? But no, it /can't/ start conducting that sharply, and it doesn't start conducting at all in that range (Vto = 3.6V!). It's because the model has Cdg(Vdg) instead of Cgs(Vds) and Cdg(Vds). The real thing behaves as you would expect from the C(V) curves in the datasheet, taking them naively as the only nonlinear capacitances in the part. Well, it turns out that's not naive at all! Coss does not depend upon Vgs, and neither Ciss nor Coss depend on Vdg. Evidently, the reason they plot only the three capacitances they show, is because those are the only relationships present! I'm a bit shocked myself! Don't you just love fields were "just-good-enough", or often times, outright bad, information persists... Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
Reply by ●September 23, 20172017-09-23
"John Larkin" <jjlarkin@highlandtechnology.com> wrote in message news:b21dsctbh7rtro6033f2agannnf40u7oqb@4ax.com...> Are you referring to the flat spot in fig 16? > > https://www.fairchildsemi.com/datasheets/FD/FDD86367_F085.pdfYes. Those are just cartoons, BTW -- no real transistor looks quite like that. The corners are rounded, and the plateau isn't horizontal (which would be silly). IXYS actually plots measurements rather than cartoons: http://ixapps.ixys.com/DataSheet/DS100216B(TA-TP-TQ-TH460P2).pdf Fig. 10. The model thinks it looks like this: https://www.seventransistorlabs.com/Images/STW21NM50N_Gate_Charge.png Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
Reply by ●September 23, 20172017-09-23
On a sunny day (Sat, 23 Sep 2017 12:57:08 -0500) it happened "Tim Williams" <tmoranwms@gmail.com> wrote in <oq679q$8e9$1@dont-email.me>:>"Jan Panteltje" <pNa0nStpealmtje@yahoo.com> wrote in message >news:oq56m9$1o1$1@gioia.aioe.org... >> simulations are not reality, pokemon is not real. >> > >I know, that's why I'm trying to do Crysis!mm had to look that up: https://en.wikipedia.org/wiki/Crysis N Korea! Well I am all with Kim ;-)>Tim > >-- >Seven Transistor Labs, LLC >Electrical Engineering Consultation and Contract Design >Website: http://seventransistorlabs.com > >
Reply by ●September 23, 20172017-09-23
On Sat, 23 Sep 2017 13:36:05 -0500, "Tim Williams" <tmoranwms@gmail.com> wrote:>"John Larkin" <jjlarkin@highlandtechnology.com> wrote in message >news:b21dsctbh7rtro6033f2agannnf40u7oqb@4ax.com... >> Are you referring to the flat spot in fig 16? >> >> https://www.fairchildsemi.com/datasheets/FD/FDD86367_F085.pdf > >Yes. Those are just cartoons, BTW -- no real transistor looks quite like >that. The corners are rounded, and the plateau isn't horizontal (which >would be silly). IXYS actually plots measurements rather than cartoons: >http://ixapps.ixys.com/DataSheet/DS100216B(TA-TP-TQ-TH460P2).pdf >Fig. 10.Except for the soft corners, their plateau is horizontal.> >The model thinks it looks like this: >https://www.seventransistorlabs.com/Images/STW21NM50N_Gate_Charge.png > >TimDifferent mosfets, made on different processes, can be expected to have different diffusion profiles and different C-V curves. Some slope very gently, some have steep drop-offs. Like different diodes have very different C-V curves. I hardly think that a bunch of mosfet makers are publishing erroneous C-V curves; they have expensive test gear. A Spice model of transition gate and drain volts usually has a flat plateau, as the drain slews in its transition and feeds back into the gate through Crss. I don't think that decades of academic and industry Spice mosfet models are lying. The data sheets are usually unclear about how they measure the gate charge waveforms. They specify Vd and Id, but is the drain fed by a constant-current source, or a resistor? A little rounding of the plateau corners doesn't matter much in real life. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by ●September 23, 20172017-09-23
On Fri, 22 Sep 2017 23:21:30 -0500, "Tim Williams" <tmoranwms@gmail.com> wrote:>VDMOS nonlinear capacitance is modeled in terms of Vgd. > >Too bad a real MOSFET doesn't show a steplike change in Ciss as Vgd changes >sign. (This is easily demonstrated with the gate charge test circuit, >watching the waveform at low Vdd. The cutoff slope depends only on Vds, not >Vgd.) > >So many decades of bullshit to sift through... > >TimFun quiz: find out how many things are wrong with this circuit: https://www.dropbox.com/s/54oianu85weidb3/IRFL210_Qg_Ckt.jpg?raw=1 -- John Larkin Highland Technology, Inc lunatic fringe electronics
