>
>On Saturday, September 23, 2017 at 12:25:24 PM UTC-7, John Larkin wrote:
>...
>
>> Except for the soft corners, their plateau is horizontal.
>>=20
>...
>
>The plateau will not be quite horizontal - its slope will depend upon the v=
>oltage gain which depends upon the gm of the FET and the effective resistan=
>ce at the drain circuit.
>
>There has to be enough gate voltage change in the plateau region to cause t=
>he drain voltage to change to counteract the charge being suppled by the ga=
>te circuit to to the other end of Cgd.
>
>The test circuits with a constant current sourcing for the drain will have =
>the most gain, the ones using another identical device as the CC source and=
> the ones using a resistor will have decreasing order of gain and larger ga=
>te voltage slope on the plateau.
>
>The one using an identical device seems a reasonable standard as the gain w=
>ill be "gm*Ro/2".
Right, if the measurement is made at a high current
density for the MOSFET, it'll show a slope.
--
Thanks,
- Win
Reply by Tim Williams●September 24, 20172017-09-24
"kevin93" <kevin@whitedigs.com> wrote in message
news:6d76bb3a-0bea-4fc8-ae05-a17ddc4b5512@googlegroups.com...
> This is a curve I measured for a BSS138 at low current - there was about
> 160mV change in gate drive during the run down.
>
> There is a fair amount of curvature of the drain voltage slope.
>
> I used your technique of documenting it within the photo - good idea.
>
> https://i.imgur.com/xxG9CC8.jpg
See how it's angled in during the onset of the plateau?
Suppose Cdg were massively smaller at that point; what would happen? Well,
Vds would drop a whole lot faster, and Vgs would rise faster, too. Though
not quite as fast as below threshold.
Now reflect upon my waveform:
https://www.seventransistorlabs.com/Images/STP19NM50N%201.045mA%20Gate%20Charge%20400V%2030.1%20ohm%20Drain.png
The first 'break' in the rising gate voltage, where Vds first drops, is
exactly where that happens. Cdg is extremely small, perhaps 10pF.
Well, let's see. The initial slope is about 3:1, or 6V per 5.2nC, or 0.87nF
(which is Ciss, close to the 1nF datasheet figure).
When Vds starts to drop, it gets more shallow, about 1:1 slope, or 2V/5nC,
or 2.5nF equivalent. We could calculate the voltage gain and Miller effect,
but better to use the totals:
delta Vgs = 1.2V (4.0 to 5.2V)
delta T = 3.3us --> delta Q = 3.45nC
delta Vds = 340V
So delta Qg = 1.044nC (still assuming 0.87nF), so delta Qgd = 1.4nC. 1.4nC
/ 340V = 4.11pF average.
Which is pretty astonishingly low!
It's not fully "on" until 20us after trigger -- even though Vds swings 90%
in the first 7us. That's the magic of these SuperJunction parts. The
capacitance acts like a snubber network built into the MOSFET, massively
saving on switching losses, even for hard switched loads!
Tim
--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com
Reply by kevin93●September 24, 20172017-09-24
On Sunday, September 24, 2017 at 2:15:37 PM UTC-7, John Larkin wrote:
> On Sun, 24 Sep 2017 10:07:51 -0700 (PDT), kevin93
> >...
> >
> >The plateau will not be quite horizontal - its slope will depend upon the voltage gain which depends upon the gm of the FET and the effective resistance at the drain circuit.
>
> All the capacitances are changing in real time, too.
>
...
Yup, agreed
This is a curve I measured for a BSS138 at low current - there was about 160mV change in gate drive during the run down.
There is a fair amount of curvature of the drain voltage slope.
I used your technique of documenting it within the photo - good idea.
https://i.imgur.com/xxG9CC8.jpg
kevin
>On Saturday, September 23, 2017 at 12:25:24 PM UTC-7, John Larkin wrote:
>...
>
>> Except for the soft corners, their plateau is horizontal.
>>
>...
>
>The plateau will not be quite horizontal - its slope will depend upon the voltage gain which depends upon the gm of the FET and the effective resistance at the drain circuit.
All the capacitances are changing in real time, too.
--
John Larkin Highland Technology, Inc
lunatic fringe electronics
Reply by kevin93●September 24, 20172017-09-24
On Saturday, September 23, 2017 at 12:25:24 PM UTC-7, John Larkin wrote:
...
> Except for the soft corners, their plateau is horizontal.
>
...
The plateau will not be quite horizontal - its slope will depend upon the voltage gain which depends upon the gm of the FET and the effective resistance at the drain circuit.
There has to be enough gate voltage change in the plateau region to cause the drain voltage to change to counteract the charge being suppled by the gate circuit to to the other end of Cgd.
The test circuits with a constant current sourcing for the drain will have the most gain, the ones using another identical device as the CC source and the ones using a resistor will have decreasing order of gain and larger gate voltage slope on the plateau.
The one using an identical device seems a reasonable standard as the gain will be "gm*Ro/2".
kevin
>"John Larkin" <jjlarkin@highlandtechnology.com> wrote in message
>news:fr2esctegpl0lkci0se1vust4lf3ssrngm@4ax.com...
>> You had a drain resistor, no? See my post below.
>>
>
>Uh, so?
Looks like different manufacturers use different load circuits, and
most don't reveal it. That will change the shapes of the curves, but
not much affect total Qg.
Fig 14 includes Vd and Id, which is not usually on the gate-charge
curve. Interesting things going on there.
The self-heating model, fig 1, is nice. I've done that in power amps,
measured heat sink temp, fet voltage, and fet current, and run a
realtime Tj simulation as the shutdown mechanism. That lets one safely
push the fets a lot harder than any simple current limit. We derive
our thermal models by blowing up fets.
We're doing that again now, in our SSR module, but we're protecting a
wirewound resistor, not the fets. A dual RC is probably a decent
model. I'm accumulating a nice collection of exploded resistors.
Not to change the subject (me?) but I'm testing a wirewound resistor
this weekend, at 20J per shot. Viewed under my Mantis, every shot
reveals the wire coil, under the silicone coating, by a brief red
spiral-shaped flash. But with the illumination turned off, in the
dark, there is nothing visible. So it's not incandescence, but a
transient change in the chemistry of the coating?
--
John Larkin Highland Technology, Inc
lunatic fringe electronics
Reply by Klaus Kragelund●September 24, 20172017-09-24
On Saturday, September 23, 2017 at 10:10:19 PM UTC+2, John Larkin wrote:
> On Fri, 22 Sep 2017 23:21:30 -0500, "Tim Williams"
> <tmoranwms@gmail.com> wrote:
>
> >VDMOS nonlinear capacitance is modeled in terms of Vgd.
> >
> >Too bad a real MOSFET doesn't show a steplike change in Ciss as Vgd changes
> >sign. (This is easily demonstrated with the gate charge test circuit,
> >watching the waveform at low Vdd. The cutoff slope depends only on Vds, not
> >Vgd.)
> >
> >So many decades of bullshit to sift through...
> >
> >Tim
>
> Fun quiz: find out how many things are wrong with this circuit:
>
> https://www.dropbox.com/s/54oianu85weidb3/IRFL210_Qg_Ckt.jpg?raw=1
>
What's wrong with it?
If you set the Vgs right for the top MOSFET, then the current is almost perfect except for the last couple of volts drain-source
Cheers
Klaus
Reply by Jan Panteltje●September 24, 20172017-09-24
On a sunny day (Sat, 23 Sep 2017 13:10:09 -0700) it happened John Larkin
<jjlarkin@highlandtechnology.com> wrote in
<nofdschc7jenp50pd178ck4tnv48hf6a59@4ax.com>:
>On Fri, 22 Sep 2017 23:21:30 -0500, "Tim Williams"
><tmoranwms@gmail.com> wrote:
>
>>VDMOS nonlinear capacitance is modeled in terms of Vgd.
>>
>>Too bad a real MOSFET doesn't show a steplike change in Ciss as Vgd changes
>>sign. (This is easily demonstrated with the gate charge test circuit,
>>watching the waveform at low Vdd. The cutoff slope depends only on Vds, not
>>Vgd.)
>>
>>So many decades of bullshit to sift through...
>>
>>Tim
>
>Fun quiz: find out how many things are wrong with this circuit:
>
>https://www.dropbox.com/s/54oianu85weidb3/IRFL210_Qg_Ckt.jpg?raw=1
I like it ;-)
Reply by Tim Williams●September 24, 20172017-09-24
"John Larkin" <jjlarkin@highlandtechnology.com> wrote in message
news:fr2esctegpl0lkci0se1vust4lf3ssrngm@4ax.com...
> You had a drain resistor, no? See my post below.
>
...
Is channel 1 the drain?
If so how come the drain is at zero volts before the Miller plateau on the gate (Ch3?)
If so there is no feedback through Cgd at that time.
thanks
kevin