How to determine Zin, Yout for RF transistor, from A parameters

On Wednesday, May 10, 2017 at 11:24:59 AM UTC-4, Phil Hobbs wrote:
> On 05/10/2017 11:19 AM, George Herold wrote:
> > On Wednesday, May 10, 2017 at 10:41:08 AM UTC-4, Phil Hobbs wrote:
> >> On 05/07/2017 04:27 PM, Jan Panteltje wrote:
> >>> On a sunny day (Sun, 7 May 2017 20:56:49 +0100) it happened "Kevin Aylward"
> >>> <kevinRemovAT@kevinaylward.co.uk> wrote in
> >>> <5qmdnXfOYaWf4ZLEnZ2dnUU7-YfNnZ2d@giganews.com>:
> >>>
> >>>> I wrote this over 15 yeas ago:
> >>>>
> >>>> http://www.kevinaylward.co.uk/gr/emc2/emc2.html
> >>>>
> >>>> again, now pay attention to the statement just before the summary.
> >>>
> >>> Interesting, a short wile ago I was discussing time change in gravity.
> >>> As you know clocks slow down in a stronger gravitational field.
> >>> The discussion went .. well anyways
> >>> I pointed out that time' is defined as definition of second is:
> >>>   "
> >>>    the duration of 9 192 631 770 periods of the radiation corresponding to the transition between
> >>>    the two hyperfine levels of the ground state of the caesium 133 atom
> >>>   "
> >>>   (from https://en.wikipedia.org/wiki/Second).
> >>> I mentioned I have this Rubidium frequency standard in the lab,
> >>> and wondered if anybody had brought that AND the caesium clock up to space,
> >>> and looked if there was a difference, and mathematicians could have a field day if there was or was not,
> >>> as it tells something about the change in electron orbits in a changing gravitational field.
> >>> But I guess the audience ...
> >>> Never mind.
> >>
> >> Sure, GPS satellites for instance.  There were Mossbauer effect
> >> experiments done in the '60s that showed gravitational time dilation
> >> going from the ground floor of a building up to the roof.
> >>
> >> Cheers
> >>
> >> Phil Hobbs
> > 
> > Robert Pound (etal) https://en.wikipedia.org/wiki/Robert_Pound
> > 
> > It's too bad he wasn't on the NMR Nobel prize.  
> > A extraordinary experimentalist.  
> > 
> > George H.
> 
> Thanks, I'd forgotten the name.  He didn't write a lore book like RW
> Jones's, by any chance?  Getting inside the heads of guys like that is
> always illuminating.
> 
> Cheers
> 
> Phil Hobbs
> 
> -- 
> Dr Philip C D Hobbs
> Principal Consultant
> ElectroOptical Innovations LLC
> Optics, Electro-optics, Photonics, Analog Electronics
> 
> 160 North State Road #203
> Briarcliff Manor NY 10510
> 
> hobbs at electrooptical dot net
> http://electrooptical.net

I don't know of any books, I read some of his papers (written 
with Purcell) on NMR.  Very nice stuff, much better than F. Bloch's 
IMHO.  But that is mostly likely was due to Purcell.

He (like me) may not have been a very good writer. 

George H.    

On a sunny day (Mon, 08 May 2017 15:25:24 -0700) it happened John Larkin
<jjlarkin@highland_snip_technology.com> wrote in
<qur1hc5cg8j466i7bhhuajsok2l39umc4g@4ax.com>:

>This program
>
>https://www.dropbox.com/s/ajmp4kbio1uf7qn/Rugrat.jpg?dl=0
>
>finds ratios based on the resistors that we have in stock.

I usually think in voltages,
say a divider, 2.5V across lower resistor, 1V across top.
That means 2k5 and 1k
Or 5k and 2k
or 500 versus 200 Ohm.
etc, depending on what loads it, smallest one is most important.
No software needed. 
I have boxes full of SMDs, I know the values by now...
You often see those volt calculations in the corner of my great artistic circuit diagrams ;-)
But I have only a few resistors with wires that I use for testing over and over again in a box on the table..
When one value of SMD runs out I switch to an other...

On Thu, 11 May 2017 13:08:33 GMT, Jan Panteltje
<pNa0nStpealmtje@yahoo.com> wrote:

>On a sunny day (Mon, 08 May 2017 15:25:24 -0700) it happened John Larkin
><jjlarkin@highland_snip_technology.com> wrote in
><qur1hc5cg8j466i7bhhuajsok2l39umc4g@4ax.com>:
>
>>This program
>>
>>https://www.dropbox.com/s/ajmp4kbio1uf7qn/Rugrat.jpg?dl=0
>>
>>finds ratios based on the resistors that we have in stock.
>
>I usually think in voltages,
>say a divider, 2.5V across lower resistor, 1V across top.
>That means 2k5 and 1k
>Or 5k and 2k
>or 500 versus 200 Ohm.
>etc, depending on what loads it, smallest one is most important.
>No software needed. 

We must have a thousand resistors in stock, from 5% to 0.05%, various
case sizes and tempcos. If I want some ratio, with some precision, I
could spend hours with the stock listing and a calculator. It's more
fun to write a program.

Some of our precision resistors are not standard E96 values, like 2.2K
0.1% for example. Just having a few oddballs in stock opens up a huge
range of possible ratios that are impossible in E96.


-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics 

"Jan Panteltje"  wrote in message news:oerpvd$1lsj$1@gioia.aioe.org...

On a sunny day (Mon, 8 May 2017 21:15:52 +0100) it happened "Kevin Aylward"
<kevinRemovAT@kevinaylward.co.uk> wrote in
<i96dnaqjedtkTI3EnZ2dnUU7-VPNnZ2d@giganews.com>:

>wrote in message news:10gvgcdc7nt8r70tcdn5iibeepqfoor1c7@4ax.com...
>
>On Sun, 7 May 2017 20:52:06 +0100, "Kevin Aylward"
><kevinRemovAT@kevinaylward.co.uk> wrote:
>
>>"Jan Panteltje"  wrote in message news:oekvo1$jak$1@news.datemas.de...
>>
>>On a sunny day (Sat, 6 May 2017 11:24:14 -0500) it happened "Tim Williams"
>
>
>>There is a big difference between chip and board level design.
>
>My basic point through all of this was to dismiss this general idea of
>"spice isn't about the real world.... isn't good enough etc...etc..."
>
>>Pretty much every modern product today, exists because of the ics in them.
>>All ic design is done in the virtual world. Only a tiny minority of ic
>>designs have any dependence on unknown board level issues.
>
>>Sure, I am not an RF specialist.  However, I have done a few bits and bobs
>>at the several GHz region. I have also spoken to RF specialists. Most have
>>missed the boat. They think in ways passed on from their fore fathers, 
>>that
>>were passed down from their forefathers.
>
>>The days of graphical techniques and manual equation solving are gone.
>>Whether its electronics, designing the same bloody energy efficient car 
>>body
>>shape, trading stocks and shares, its all done by running millions of
>>simulations. It what TFlop computers are very good at. You just need to
>>learn how to drive them correctly. Unfortunatly, as far a board level 
>>spice
>>users go, most don't know how.

>It think there is something very bad about that trend,

That is really the Luddite approach.

It is a truly great approach. It would be impossible to have what we have 
today without such an approach.

>and in fact I think it is not really happening that way.

Of course it is. I already explained. Its a fact. Period. Every single 
modern IC you buy today has been designed in the virtual world.


>Problem with mathematicians is that they tend to take formulas that are an 
>approximation of reality
>and build their own universe on that.

I agree many mathematicians and applied mathematicians that refer to 
themselves as physicists, have lost the plot.


-- Kevin Aylward
http://www.anasoft.co.uk - SuperSpice
http://www.kevinaylward.co.uk/ee/index.html 

wrote in message news:e633hcttjkngghqdp9jp9j1kqued9fcj9f@4ax.com...

On Mon, 8 May 2017 20:44:24 +0100, "Kevin Aylward"
<kevinRemovAT@kevinaylward.co.uk> wrote:

>"Jan Panteltje"  wrote in message news:oeo0db$vsh$1@news.datemas.de...
>
>On a sunny day (Sun, 7 May 2017 20:55:15 +0100) it happened "Kevin Aylward"
><kevinRemovAT@kevinaylward.co.uk> wrote in
><BIqdnXfG6Yo55pLEnZ2dnUU7-UPNnZ2d@giganews.com>:


>>>However, I do have an OCXO asic  in production that runs up to 100MHz, 
>>>has
>>>a
>>>few ppb stability, and flat band phase noise approaching -165db, in a 
>>>very
>>>small package.
>
>>>Very impressive,. -165 dB wonder how you measure that.
>
>>Should have said dBc, but I guess you knowing all about oscillators, would
>>know the standard terminology.
>
>>I should expand on this. This is the noise after the limiter/squarer. Raw
>>oscillator designs can be -190dBc to -180dBc. A key point is that this is
>>with an internal 2.5V supply, in a package of 7mmx5mm. Any mere mortal can
>>get that sort of performance in a 1" square with 12V.

>At what offset from carrier are those figures measured ?


I did said flatband. For oscillators in the 10MHz to 50MHz range, this is of 
the order of 100Khz+ offset. This is range where xtals work best.


>Since we are measuring noise, density, what is the measurement
>bandwidth, ? 1 Hz?

Its always 1Hz BW

>Apparently the carrier power is something like +15 dBm, going -190 dB
>down from that would be -175 dBm.

PN is always specified relative to carrier in  dBc. The actual power/voltage 
is a separate spec.

If noise in dB is written, it means dBc.

>The _input_ related thermal noise _density_ for a good amplifier is
>about -174 dBm/Hz, the _output_ related thermal noise density has been
>amplified by the power gain. For oscillators, the noise floor is often
>worse.

Note we are talking about phase noise, not amplitude or additive noise. 
Oscillators can get very good flat band phase noise, but the majority of 
systems require a square wave. The limiter always dominates flatband noise.

>It appears that those noise figures are quoted at large offsets from
>the carrier, when the output phase noise density has dropped into the
>broadband noise density.

Close in PN is highly dependant on the c1 of the xtal. That is the same 
design will give vastly different results for a fundamental with a series c1 
of 5ff verses a 3rd overtone with 0.3ff.

A 10MHz fundamental design, in a small package, low current, might be say 
100dBc at 10Hz offset.  3rd OT, -120 dBc.

My pn papers are at :

http://www.kevinaylward.co.uk/ee/phasenoise/phasenoise.html


-- Kevin Aylward
http://www.anasoft.co.uk - SuperSpice
http://www.kevinaylward.co.uk/ee/index.html 

>"Jan Panteltje"  wrote in message news:oerq1e$1lvb$1@gioia.aioe.org...

>On a sunny day (Mon, 8 May 2017 20:45:18 +0100) it happened "Kevin Aylward"
><kevinRemovAT@kevinaylward.co.uk> wrote in
><7cOdnYebo-VSV43EnZ2dnUU7-fvNnZ2d@giganews.com>:

>It is impossible to do modern competitive design using just intuition. Its
>too complicated. You need to have an understanding as to what to randomly
>fiddle...

>Randomly fiddling with anything is bad.

Oh dear..., you do realise that that was  tongue in cheek comment?

There are systematic ways to design by simulation by varying components.

>I presume you mean Monte Carlo or something.

Actually no. Monte Carlo is useful for severeal things, but in general, its 
not a main driver. Most ic blocks do not require MC at all. The most 
important design process is worst case WC

http://www.anasoft.co.uk/worstcase.htm

and multivariable parameter sweeps.

As an example. Suppose its an LDO. One needs to theoretically know where to 
put compensation networks,  and an understanding of how the poles and zeros 
should be placed.

Say, there are 3 comp caps and two comp resistors, and the load cap is to be 
10n to 10uf at load currents from zero to 1A.

One sets up parameter sweeps to vary these components in a systematic way 
whilst outputting at loop gain and phase margins. This is all done all over 
again using transient runs. This is done while also examining the results 
over process corners and temperature.

That is for stability. Other issues are PSRR. This requires technical 
knowledge of what determines PSRR. Its usually a rock and a hard place. 
Getting the right device sizes and operating voltages, so devices don't 
crush, are not too large, etc...

Typically it takes 10,000s of runs to converge to an acceptable solution. 
There is still an art in it in choosing the best runs though. Grads and the 
majority that gain 1 year of experience 20 times over, typically take 3 
months for such a task, those like me and Jim T, might take a day or so, 
depending on spec.


>Even then you need some intelligent design to run you stuff on.
>But.. I am not denying that it is absolutely possible that life
>formed when accidentally some chemicals interacted in the oceans near a hot 
>vent.
>that would explain a lot ;-)
>It is in our genes to tinker...

The route explanation of all of this, is random.   Once one really thinks 
about the problem, there is only one rational solution. Essentially, an 
infinite number of universes each with different laws of physics, we just 
happen to be in one where the laws allow us to exist.

-- Kevin Aylward
http://www.anasoft.co.uk - SuperSpice
http://www.kevinaylward.co.uk/ee/index.html

On Thu, 11 May 2017 19:05:06 +0100, "Kevin Aylward"
<kevinRemovAT@kevinaylward.co.uk> wrote:

>>"Jan Panteltje"  wrote in message news:oerq1e$1lvb$1@gioia.aioe.org...
>
>>On a sunny day (Mon, 8 May 2017 20:45:18 +0100) it happened "Kevin Aylward"
>><kevinRemovAT@kevinaylward.co.uk> wrote in
>><7cOdnYebo-VSV43EnZ2dnUU7-fvNnZ2d@giganews.com>:

[snip]
>
>There are systematic ways to design by simulation by varying components.
>
>>I presume you mean Monte Carlo or something.
>
>Actually no. Monte Carlo is useful for severeal things, but in general, its 
>not a main driver. Most ic blocks do not require MC at all. The most 
>important design process is worst case WC
>
>http://www.anasoft.co.uk/worstcase.htm
>
>and multivariable parameter sweeps.
>
>As an example. Suppose its an LDO. One needs to theoretically know where to 
>put compensation networks,  and an understanding of how the poles and zeros 
>should be placed.
>
>Say, there are 3 comp caps and two comp resistors, and the load cap is to be 
>10n to 10uf at load currents from zero to 1A.
>
>One sets up parameter sweeps to vary these components in a systematic way 
>whilst outputting at loop gain and phase margins. This is all done all over 
>again using transient runs. This is done while also examining the results 
>over process corners and temperature.
>
>That is for stability. Other issues are PSRR. This requires technical 
>knowledge of what determines PSRR. Its usually a rock and a hard place. 
>Getting the right device sizes and operating voltages, so devices don't 
>crush, are not too large, etc...
>
>Typically it takes 10,000s of runs to converge to an acceptable solution. 
>There is still an art in it in choosing the best runs though. Grads and the 
>majority that gain 1 year of experience 20 times over, typically take 3 
>months for such a task, those like me and Jim T, might take a day or so, 
>depending on spec.
>

[snip]

My typical TOTAL design time for a relatively complex
Analog/Mixed-Signal chip is only 3-4 months, including interim and
final design reviews... all by my lonesome, except for my layout
associate.

Some un-named "teams" take longer than that cutting and pasting from
existing IP and text-book "solutions"... AND have a high rate of
"re-spins" >:-}
		
                                        ...Jim Thompson
-- 
| James E.Thompson                                 |    mens     |
| Analog Innovations                               |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

     Thinking outside the box... producing elegant solutions.

"It is not in doing what you like, but in liking what you do that
is the secret of happiness."  -James Barrie

On a sunny day (Thu, 11 May 2017 19:05:06 +0100) it happened "Kevin Aylward"
<kevinRemovAT@kevinaylward.co.uk> wrote in
<1t-dnbJ6redOOonEnZ2dnUU7-Q3NnZ2d@giganews.com>:

>>"Jan Panteltje"  wrote in message news:oerq1e$1lvb$1@gioia.aioe.org...
>
>>On a sunny day (Mon, 8 May 2017 20:45:18 +0100) it happened "Kevin Aylward"
>><kevinRemovAT@kevinaylward.co.uk> wrote in
>><7cOdnYebo-VSV43EnZ2dnUU7-fvNnZ2d@giganews.com>:
>
>>It is impossible to do modern competitive design using just intuition. Its
>>too complicated. You need to have an understanding as to what to randomly
>>fiddle...
>
>>Randomly fiddling with anything is bad.
>
>Oh dear..., you do realise that that was  tongue in cheek comment?
>
>There are systematic ways to design by simulation by varying components.
>
>>I presume you mean Monte Carlo or something.
>
>Actually no. Monte Carlo is useful for severeal things, but in general, its 
>not a main driver. Most ic blocks do not require MC at all. The most 
>important design process is worst case WC
>
>http://www.anasoft.co.uk/worstcase.htm
>
>and multivariable parameter sweeps.
>
>As an example. Suppose its an LDO. One needs to theoretically know where to 
>put compensation networks,  and an understanding of how the poles and zeros 
>should be placed.
>
>Say, there are 3 comp caps and two comp resistors, and the load cap is to be 
>10n to 10uf at load currents from zero to 1A.
>
>One sets up parameter sweeps to vary these components in a systematic way 
>whilst outputting at loop gain and phase margins. This is all done all over 
>again using transient runs. This is done while also examining the results 
>over process corners and temperature.
>
>That is for stability. Other issues are PSRR. This requires technical 
>knowledge of what determines PSRR. Its usually a rock and a hard place. 
>Getting the right device sizes and operating voltages, so devices don't 
>crush, are not too large, etc...
>
>Typically it takes 10,000s of runs to converge to an acceptable solution. 
>There is still an art in it in choosing the best runs though. Grads and the 
>majority that gain 1 year of experience 20 times over, typically take 3 
>months for such a task, those like me and Jim T, might take a day or so, 
>depending on spec.
>
>
>>Even then you need some intelligent design to run you stuff on.
>>But.. I am not denying that it is absolutely possible that life
>>formed when accidentally some chemicals interacted in the oceans near a hot 
>>vent.
>>that would explain a lot ;-)
>>It is in our genes to tinker...
>
>The route explanation of all of this, is random.   Once one really thinks 
>about the problem, there is only one rational solution. Essentially, an 
>infinite number of universes each with different laws of physics, we just 
>happen to be in one where the laws allow us to exist.

Na, I could follow you for most parts up to here.
But the infinite universes thingy does not jive with me.
Apart from the fact that if one says 'Universe' everybody has his / her own ideas...
I do not think the laws of physics are that different..
If you define 'universe' as that what we currently can see (detect), yes
then there can be many big bangs, _could_ have happened, just like there are many stars etc.
But in each of those similar matter and laws as there are in each star we observe.
Some basic constants may be very different in those 'bangs',
or maybe even have been very different in our own bang (think speed of light for example).
There are several theories, like for example tired light, to explain the redshift,
but maybe the medium changed, that what the EM waves propagate in.
maybe u0, there are plenty of unsolved problems, dark force, dark matter, what not.
but that takes us to physics.
Back to the MOSFETs :-)
 

"Jim Thompson"  wrote in message 
news:iva9hc5t59m8qfo3medh69t0e8e01a08it@4ax.com...

On Thu, 11 May 2017 19:05:06 +0100, "Kevin Aylward"
<kevinRemovAT@kevinaylward.co.uk> wrote:

>>"Jan Panteltje"  wrote in message news:oerq1e$1lvb$1@gioia.aioe.org...
>
>>On a sunny day (Mon, 8 May 2017 20:45:18 +0100) it happened "Kevin 
>>Aylward"
>><kevinRemovAT@kevinaylward.co.uk> wrote in
>><7cOdnYebo-VSV43EnZ2dnUU7-fvNnZ2d@giganews.com>:

[snip]
>
>>There are systematic ways to design by simulation by varying components.
>
>>>I presume you mean Monte Carlo or something.
>
>>Actually no. Monte Carlo is useful for severeal things, but in general, 
>>its
>>not a main driver. Most ic blocks do not require MC at all. The most
>>important design process is worst case WC
>
>>http://www.anasoft.co.uk/worstcase.htm
>
>>and multivariable parameter sweeps.
>
>>As an example. Suppose its an LDO. One needs to theoretically know where 
>>to
>>put compensation networks,  and an understanding of how the poles and 
>>zeros
>>should be placed.
>
>>Say, there are 3 comp caps and two comp resistors, and the load cap is to 
>>be
>>10n to 10uf at load currents from zero to 1A.
>
>One sets up parameter sweeps to vary these components in a systematic way
>whilst outputting at loop gain and phase margins. This is all done all over
>again using transient runs. This is done while also examining the results
>over process corners and temperature.
>
>>That is for stability. Other issues are PSRR. This requires technical
>>knowledge of what determines PSRR. Its usually a rock and a hard place.
>>Getting the right device sizes and operating voltages, so devices don't
>>crush, are not too large, etc...
>
>>Typically it takes 10,000s of runs to converge to an acceptable solution.
>>There is still an art in it in choosing the best runs though. Grads and 
>>the
>>majority that gain 1 year of experience 20 times over, typically take 3
>>months for such a task, those like me and Jim T, might take a day or so,
>>depending on spec.
>

[snip]

>My typical TOTAL design time for a relatively complex
>Analog/Mixed-Signal chip is only 3-4 months, including interim and
>final design reviews... all by my lonesome, except for my layout
>associate.

It is interesting that most hirers simply don't understand that there are 
those that are 10+ times as productive as others.

I would say I average out at 100 blocks, 50 transistors per block, per year. 
I would say most do about 4-5, if that, and those still have problems and 
re-spins.

Some blocks might take me an hour or so.

>Some un-named "teams" take longer than that cutting and pasting from
>existing IP and text-book "solutions"... AND have a high rate of
>"re-spins" >:-}

Yeah... Have a look at my linked in profile :-)


-- Kevin Aylward
http://www.anasoft.co.uk - SuperSpice
http://www.kevinaylward.co.uk/ee/index.html 

On Thu, 11 May 2017 19:04:06 +0100, "Kevin Aylward"
<kevinRemovAT@kevinaylward.co.uk> wrote:

>wrote in message news:e633hcttjkngghqdp9jp9j1kqued9fcj9f@4ax.com...
>
>On Mon, 8 May 2017 20:44:24 +0100, "Kevin Aylward"
><kevinRemovAT@kevinaylward.co.uk> wrote:
>
>>"Jan Panteltje"  wrote in message news:oeo0db$vsh$1@news.datemas.de...
>>
>>On a sunny day (Sun, 7 May 2017 20:55:15 +0100) it happened "Kevin Aylward"
>><kevinRemovAT@kevinaylward.co.uk> wrote in
>><BIqdnXfG6Yo55pLEnZ2dnUU7-UPNnZ2d@giganews.com>:
>
>
>>>>However, I do have an OCXO asic  in production that runs up to 100MHz, 
>>>>has
>>>>a
>>>>few ppb stability, and flat band phase noise approaching -165db, in a 
>>>>very
>>>>small package.
>>
>>>>Very impressive,. -165 dB wonder how you measure that.
>>
>>>Should have said dBc, but I guess you knowing all about oscillators, would
>>>know the standard terminology.
>>
>>>I should expand on this. This is the noise after the limiter/squarer. Raw
>>>oscillator designs can be -190dBc to -180dBc. A key point is that this is
>>>with an internal 2.5V supply, in a package of 7mmx5mm. Any mere mortal can
>>>get that sort of performance in a 1" square with 12V.
>
>>At what offset from carrier are those figures measured ?
>
>
>I did said flatband. For oscillators in the 10MHz to 50MHz range, this is of 
>the order of 100Khz+ offset. This is range where xtals work best.

Such huge offsets are of interest mainly with half-duplex repeaters.
 
Commercial half-duplex repeater stations usually work with several MHz
duplex intervals. However amateur radio repeaters usually work with
only 100 kHz @29 MHz and 600 kHz @51 and 145 MHz bands. 

When a common Rx/Tx antenna is used, of course the receiver needs a
notch (several cavity resonators) tuned to the Tx frequency, but in
practice, you also need one or more cavity resonators in the Tx chain
to notch out the phase noise from the Tx falling on to the Rx
passband. The aim should be that the Tx phase noise leaking into the
receiver should be less than the receiver thermal noise and the band
noise (which is huge at 29 and 51 MHz).

For this kind of applications, your figures are impressive, making it
possible to drop one or perhaps all cavity Rx notch filters from the
design.

However, for general receiver design, the local oscillator (LO) phase
noise has an other nasty feature. If there is a very strong (say 1 MW)
transmitter station close to the desired weak station, the phase noise
from the LO and the strong unwanted signal will form _reverse_ mixing
products falling into the pass band of the receiver. Thus strong
signals at the nearby channel can be quite harmful. for LF/MF/HF
signals  the nearby signal can be 5/9/10 kHz, for aviation 8.33/25 kHz
and for general FM service 12.5 or 25 kHz away. 

For this reason, the phase noise at 5-25 kHz offset is of great
interest.

>>Since we are measuring noise, density, what is the measurement
>>bandwidth, ? 1 Hz?
>
>Its always 1Hz BW

So did I assume, but you never know, which tricks specification
writers use these days :-)

>>Apparently the carrier power is something like +15 dBm, going -190 dB
>>down from that would be -175 dBm.
>
>PN is always specified relative to carrier in  dBc. The actual power/voltage 
>is a separate spec.
>
>If noise in dB is written, it means dBc.

For practical purposes, the interesting offset is when the oscillator
phase noise is drowned by the thermal noise and for LF/MF/HF/VHF
receivers, when it drops below the band noise.

For this reason, you really need significant power levels in order to
stay away from the thermal noise floor. For low power designs, the
maximum dBc figures are simply limited by the thermal noise.

>>The _input_ related thermal noise _density_ for a good amplifier is
>>about -174 dBm/Hz, the _output_ related thermal noise density has been
>>amplified by the power gain. For oscillators, the noise floor is often
>>worse.
>
>Note we are talking about phase noise, not amplitude or additive noise. 
>Oscillators can get very good flat band phase noise, but the majority of 
>systems require a square wave. The limiter always dominates flatband noise.

I assume that by flatband noise you are referring to the thermal noise
floor ?

>
>>It appears that those noise figures are quoted at large offsets from
>>the carrier, when the output phase noise density has dropped into the
>>broadband noise density.
>
>Close in PN is highly dependant on the c1 of the xtal. That is the same 
>design will give vastly different results for a fundamental with a series c1 
>of 5ff verses a 3rd overtone with 0.3ff.
>
>A 10MHz fundamental design, in a small package, low current, might be say 
>100dBc at 10Hz offset.  3rd OT, -120 dBc.
>
>My pn papers are at :
>
>http://www.kevinaylward.co.uk/ee/phasenoise/phasenoise.html
>
>
>-- Kevin Aylward
>http://www.anasoft.co.uk - SuperSpice
>http://www.kevinaylward.co.uk/ee/index.html