On Friday, 5 December 2014 23:15:56 UTC+11, Tom Swift wrote:> Tom Swift <spam@me.com> wrote: > > > Phil Hobbs <hobbs@electrooptical.net> wrote: > > > >> On 12/4/2014 7:44 PM, Joe Gwinn wrote: > > > >>> Also beware phase jumps when the DDS phase wheel rolls over. > > > >> Could you elaborate a bit? I thought the whole idea was to keep > >> phase continuity. > > > >> Thanks > > > >> Phil Hobbs > > > Time-Nuts has a number of threads discussing this issue. I could not > > find the particular thread I was looking for, > > I found it. > > An (unknown?) nasty feature of the DDS principle for time nuts applications > > https://www.febo.com/pipermail/time-nuts/2011-January/053863.htmlThe AD9850 is a very old DDS. Some more recent parts http://www.analog.com/static/imported-files/data_sheets/AD9913.pdf offer a "programmable modulus module" that lets you get away from powers of two. See page 14 of the AD9913 data sheet. -- Bill Sloman, Sydney
DDS wisdom
Started by ●December 4, 2014
Reply by ●December 5, 20142014-12-05
Reply by ●December 5, 20142014-12-05
Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:> What I'm less sure about is being able to keep the two channels > sufficiently isolated to be able to maintain 12 or ideally 14 bits of > phase accuracy. Even with a full-scale input, I'll need 85 dB of > isolation to get 14 bits, and it gets harder with weaker signals. > (There'll be a DLVA/limiter ahead of the phase detector, which will > help.)You might look at the AD9959. It has 4 synchronized DDS with 14 bit phase resolution. The channel isolation is >65dB but they don't specify the frequency range. Maybe it's better at lower frequencies. Having all the DDS in one package should give better tracking and lower drift. Here's the main features: FEATURES 4 synchronized DDS channels @ 500 MSPS Independent frequency/phase/amplitude control between channels Matched latencies for frequency/phase/amplitude changes Excellent channel-to-channel isolation (>65 dB) Linear frequency/phase/amplitude sweeping capability Up to 16 levels of frequency/phase/amplitude modulation (pin-selectable) 4 integrated 10-bit digital-to-analog converters (DACs) Individually programmable DAC full-scale currents 0.12 Hz or better frequency tuning resolution 14-bit phase offset resolution 10-bit output amplitude scaling resolution Serial I/O port interface (SPI) with enhanced data throughput Here's the Octopart price and datasheet. Not cheap, but it works out to $19.33 each if you end up using three. http://octopart.com/partsearch#!?q=ad9959 http://datasheet.octopart.com/AD9959BCPZ-Analog-Devices-datasheet- 8548345.pdf The AD9913 offers programmable modulus which might help. It's only $17 http://octopart.com/partsearch#!?q=ad9913 http://datasheet.octopart.com/AD9913BCPZ-Analog-Devices-datasheet- 5334308.pdf> I've never used DDSes before, and I'd appreciate some wisdom from > folks who have. How hard is that likely to be, and what should I > particularly watch out for?> Thanks> Phil Hobbs
Reply by ●December 5, 20142014-12-05
Den fredag den 5. december 2014 13.54.58 UTC+1 skrev Bill Sloman:> On Friday, 5 December 2014 14:27:37 UTC+11, Phil Hobbs wrote: > > On 12/4/2014 7:10 PM, rickman wrote: > > > On 12/4/2014 3:04 PM, Phil Hobbs wrote: > > >> Hi, all, > > >> > > >> I have a gig coming in that will have me revisiting my thesis resear=ch> > >> from nearly 30 years ago, on interferometric laser microscopes. (Fu=n.)> > >> > > >> Back in the day, I made a nulling-type phase digitizer at 60 MHz by > > >> driving a phase shifter with a 12-bit DAC (AD-DAC80), and wrapping a > > >> 13-bit successive approximation loop round it (AM2904 with an extra > > >> flipflop). With quite a lot of calibration, that got me a 13-bit, 2=-pi,> > >> 50 ks/s phase measurement that I was pretty happy with. (The extra =bit> > >> came from deciding which null to head for, which is why I needed the > > >> extra FF.) It was all interfaced to an HP 9816 computer via a GPIO > > >> card, and (eventually) worked great. I published one of my only two > > >> instruments papers on it (this was before I realized the total futil=ity> > >> of almost all instruments papers). > > >> > > >> The advantage of nulling detection is that you only need 1-D calibra=tion> > >> tables for phase shift and amplitude, whereas getting that sort of > > >> accuracy with I/Q techniques requires a 2-D calibration table, which=is> > >> a gigantic pain. > > >> > > >> I need to do this again, 2015 style. The speed requirements are set=by> > >> the acoustic delay in the AO scanner, so 50-100 ks/s is about all I =can> > >> use. Rather than all that squishy analogue stuff, I'm planning to d=o> > >> the SAR in software and use a pair of AD9951 DDS chips, one to gener=ate> > >> the desired signal and one to be the phase shifted comparison signal=.> > >> > > >> So far so straightforward. > > >> > > >> What I'm less sure about is being able to keep the two channels > > >> sufficiently isolated to be able to maintain 12 or ideally 14 bits o=f> > >> phase accuracy. Even with a full-scale input, I'll need 85 dB of > > >> isolation to get 14 bits, and it gets harder with weaker signals. > > >> (There'll be a DLVA/limiter ahead of the phase detector, which will > > >> help.) > > >> > > >> I've never used DDSes before, and I'd appreciate some wisdom from fo=lks> > >> who have. How hard is that likely to be, and what should I particul=arly> > >> watch out for? > > > > > > I've read all the posts so far and it seems you are generating a VHF > > > sine wave to compare to a VHF signal you wish to measure the phase an=d> > > amplitude of. I think I get that. But it seems the modulation of th=e> > > VHF signal is pretty low rate so that 50 kSPS is good enough. > > > > > > Then you ask about how to maintain enough isolation to preserve 14 bi=ts> > > of phase measurement. I think the isolation you are worried about it=in> > > the VHF range, no? That is the domain of RF design and not at all > > > trivial. I think you will need to provide more info on design specif=ics.> > > > > > I'm not clear on how you plan to do the phase detector. Is this just > > > subtracting the reference signal from the signal being measured? You > > > then scan the phase of the reference to find the null, scan the > > > amplitude of the reference to optimize the null and then possibly > > > repeat? Otherwise I'm not sure how you get both phase and amplitude =out> > > of this. > > > > > The phase detector will probably be a diode bridge type, e.g. a Mini=20 > > Circuits MPD-1. It's approximately a multiplier. >=20 > Why not use a real multiplier? Analog Devices have a couple of pretty goo=d analog multiplier chips. AD734 and AD834 come to mind.>=20 > And if you are working at a fixed frequency, running the DDS staircase ap=proximation to a sine wave through an integrator (with the right gain) turn= s it into a straight-line interpolation approximation to a sine wave, which= is a lot nicer, (and slightly easier to filter).>=20 > --=20 > Bill Sloman, Sydneyan integrator is just a bad filter, why should a bad filter in front of a g= ood filter suddenly make things better?=20 -Lasse
Reply by ●December 5, 20142014-12-05
On 2014-12-05 13:54, Bill Sloman wrote:> On Friday, 5 December 2014 14:27:37 UTC+11, Phil Hobbs wrote: >> On 12/4/2014 7:10 PM, rickman wrote: >>> On 12/4/2014 3:04 PM, Phil Hobbs wrote: >>>> Hi, all, >>>> >>>> I have a gig coming in that will have me revisiting my thesis >>>> research from nearly 30 years ago, on interferometric laser >>>> microscopes. (Fun.) >>>> >>>> Back in the day, I made a nulling-type phase digitizer at 60 >>>> MHz by driving a phase shifter with a 12-bit DAC (AD-DAC80), >>>> and wrapping a 13-bit successive approximation loop round it >>>> (AM2904 with an extra flipflop). With quite a lot of >>>> calibration, that got me a 13-bit, 2-pi, 50 ks/s phase >>>> measurement that I was pretty happy with. (The extra bit came >>>> from deciding which null to head for, which is why I needed >>>> the extra FF.) It was all interfaced to an HP 9816 computer >>>> via a GPIO card, and (eventually) worked great. I published >>>> one of my only two instruments papers on it (this was before I >>>> realized the total futility of almost all instruments papers). >>>> >>>> The advantage of nulling detection is that you only need 1-D >>>> calibration tables for phase shift and amplitude, whereas >>>> getting that sort of accuracy with I/Q techniques requires a >>>> 2-D calibration table, which is a gigantic pain. >>>> >>>> I need to do this again, 2015 style. The speed requirements >>>> are set by the acoustic delay in the AO scanner, so 50-100 ks/s >>>> is about all I can use. Rather than all that squishy analogue >>>> stuff, I'm planning to do the SAR in software and use a pair of >>>> AD9951 DDS chips, one to generate the desired signal and one to >>>> be the phase shifted comparison signal. >>>> >>>> So far so straightforward. >>>> >>>> What I'm less sure about is being able to keep the two >>>> channels sufficiently isolated to be able to maintain 12 or >>>> ideally 14 bits of phase accuracy. Even with a full-scale >>>> input, I'll need 85 dB of isolation to get 14 bits, and it gets >>>> harder with weaker signals. (There'll be a DLVA/limiter ahead >>>> of the phase detector, which will help.) >>>> >>>> I've never used DDSes before, and I'd appreciate some wisdom >>>> from folks who have. How hard is that likely to be, and what >>>> should I particularly watch out for? >>> >>> I've read all the posts so far and it seems you are generating a >>> VHF sine wave to compare to a VHF signal you wish to measure the >>> phase and amplitude of. I think I get that. But it seems the >>> modulation of the VHF signal is pretty low rate so that 50 kSPS >>> is good enough. >>> >>> Then you ask about how to maintain enough isolation to preserve >>> 14 bits of phase measurement. I think the isolation you are >>> worried about it in the VHF range, no? That is the domain of RF >>> design and not at all trivial. I think you will need to provide >>> more info on design specifics. >>> >>> I'm not clear on how you plan to do the phase detector. Is this >>> just subtracting the reference signal from the signal being >>> measured? You then scan the phase of the reference to find the >>> null, scan the amplitude of the reference to optimize the null >>> and then possibly repeat? Otherwise I'm not sure how you get >>> both phase and amplitude out of this. >>> >> The phase detector will probably be a diode bridge type, e.g. a >> Mini Circuits MPD-1. It's approximately a multiplier. > > Why not use a real multiplier? Analog Devices have a couple of pretty > good analog multiplier chips. AD734 and AD834 come to mind. > > And if you are working at a fixed frequency, running the DDS > staircase approximation to a sine wave through an integrator (with > the right gain) turns it into a straight-line interpolation > approximation to a sine wave, which is a lot nicer, (and slightly > easier to filter). >Och, passive double-balanced mixers make excellent phase detectors, much better than analog multipliers in most applications. An integrator is merely one more reconstruction filter pole. There is no particular incentive to put it at zero frequency and probably several reasons not to. Jeroen Belleman
Reply by ●December 5, 20142014-12-05
On 12/5/2014 3:47 AM, rickman wrote:> On 12/4/2014 10:27 PM, Phil Hobbs wrote: >> On 12/4/2014 7:10 PM, rickman wrote: >>> On 12/4/2014 3:04 PM, Phil Hobbs wrote: >>>> Hi, all, >>>> >>>> I have a gig coming in that will have me revisiting my thesis research >>>> from nearly 30 years ago, on interferometric laser microscopes. (Fun.) >>>> >>>> Back in the day, I made a nulling-type phase digitizer at 60 MHz by >>>> driving a phase shifter with a 12-bit DAC (AD-DAC80), and wrapping a >>>> 13-bit successive approximation loop round it (AM2904 with an extra >>>> flipflop). With quite a lot of calibration, that got me a 13-bit, >>>> 2-pi, >>>> 50 ks/s phase measurement that I was pretty happy with. (The extra bit >>>> came from deciding which null to head for, which is why I needed the >>>> extra FF.) It was all interfaced to an HP 9816 computer via a GPIO >>>> card, and (eventually) worked great. I published one of my only two >>>> instruments papers on it (this was before I realized the total futility >>>> of almost all instruments papers). >>>> >>>> The advantage of nulling detection is that you only need 1-D >>>> calibration >>>> tables for phase shift and amplitude, whereas getting that sort of >>>> accuracy with I/Q techniques requires a 2-D calibration table, which is >>>> a gigantic pain. >>>> >>>> I need to do this again, 2015 style. The speed requirements are set by >>>> the acoustic delay in the AO scanner, so 50-100 ks/s is about all I can >>>> use. Rather than all that squishy analogue stuff, I'm planning to do >>>> the SAR in software and use a pair of AD9951 DDS chips, one to generate >>>> the desired signal and one to be the phase shifted comparison signal. >>>> >>>> So far so straightforward. >>>> >>>> What I'm less sure about is being able to keep the two channels >>>> sufficiently isolated to be able to maintain 12 or ideally 14 bits of >>>> phase accuracy. Even with a full-scale input, I'll need 85 dB of >>>> isolation to get 14 bits, and it gets harder with weaker signals. >>>> (There'll be a DLVA/limiter ahead of the phase detector, which will >>>> help.) >>>> >>>> I've never used DDSes before, and I'd appreciate some wisdom from folks >>>> who have. How hard is that likely to be, and what should I >>>> particularly >>>> watch out for? >>> >>> I've read all the posts so far and it seems you are generating a VHF >>> sine wave to compare to a VHF signal you wish to measure the phase and >>> amplitude of. I think I get that. But it seems the modulation of the >>> VHF signal is pretty low rate so that 50 kSPS is good enough. >>> >>> Then you ask about how to maintain enough isolation to preserve 14 bits >>> of phase measurement. I think the isolation you are worried about it in >>> the VHF range, no? That is the domain of RF design and not at all >>> trivial. I think you will need to provide more info on design >>> specifics. >>> >>> I'm not clear on how you plan to do the phase detector. Is this just >>> subtracting the reference signal from the signal being measured? You >>> then scan the phase of the reference to find the null, scan the >>> amplitude of the reference to optimize the null and then possibly >>> repeat? Otherwise I'm not sure how you get both phase and amplitude out >>> of this. >>> >> The phase detector will probably be a diode bridge type, e.g. a Mini >> Circuits MPD-1. It's approximately a multiplier. > > I'm not familiar with that type of detector. Will that give you an > output related to phase and also proportional to amplitude? >Yes, it's basically a double-balanced mixer run with its IF at DC, with some hacks to increase output voltage and reduce DC offset. There's also a DLVA (detector & log video amplifier) in there, which gets rid of the amplitude information and produces a logarithmic AM output. (I usually use SA604As for that, but this application needs something a bit better than that.) Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Reply by ●December 5, 20142014-12-05
On 12/5/2014 7:54 AM, Bill Sloman wrote:> On Friday, 5 December 2014 14:27:37 UTC+11, Phil Hobbs wrote: >> On 12/4/2014 7:10 PM, rickman wrote: >>> On 12/4/2014 3:04 PM, Phil Hobbs wrote: >>>> Hi, all, >>>> >>>> I have a gig coming in that will have me revisiting my thesis >>>> research from nearly 30 years ago, on interferometric laser >>>> microscopes. (Fun.) >>>> >>>> Back in the day, I made a nulling-type phase digitizer at 60 >>>> MHz by driving a phase shifter with a 12-bit DAC (AD-DAC80), >>>> and wrapping a 13-bit successive approximation loop round it >>>> (AM2904 with an extra flipflop). With quite a lot of >>>> calibration, that got me a 13-bit, 2-pi, 50 ks/s phase >>>> measurement that I was pretty happy with. (The extra bit came >>>> from deciding which null to head for, which is why I needed >>>> the extra FF.) It was all interfaced to an HP 9816 computer >>>> via a GPIO card, and (eventually) worked great. I published >>>> one of my only two instruments papers on it (this was before I >>>> realized the total futility of almost all instruments papers). >>>> >>>> The advantage of nulling detection is that you only need 1-D >>>> calibration tables for phase shift and amplitude, whereas >>>> getting that sort of accuracy with I/Q techniques requires a >>>> 2-D calibration table, which is a gigantic pain. >>>> >>>> I need to do this again, 2015 style. The speed requirements >>>> are set by the acoustic delay in the AO scanner, so 50-100 ks/s >>>> is about all I can use. Rather than all that squishy analogue >>>> stuff, I'm planning to do the SAR in software and use a pair of >>>> AD9951 DDS chips, one to generate the desired signal and one to >>>> be the phase shifted comparison signal. >>>> >>>> So far so straightforward. >>>> >>>> What I'm less sure about is being able to keep the two >>>> channels sufficiently isolated to be able to maintain 12 or >>>> ideally 14 bits of phase accuracy. Even with a full-scale >>>> input, I'll need 85 dB of isolation to get 14 bits, and it gets >>>> harder with weaker signals. (There'll be a DLVA/limiter ahead >>>> of the phase detector, which will help.) >>>> >>>> I've never used DDSes before, and I'd appreciate some wisdom >>>> from folks who have. How hard is that likely to be, and what >>>> should I particularly watch out for? >>> >>> I've read all the posts so far and it seems you are generating a >>> VHF sine wave to compare to a VHF signal you wish to measure the >>> phase and amplitude of. I think I get that. But it seems the >>> modulation of the VHF signal is pretty low rate so that 50 kSPS >>> is good enough. >>> >>> Then you ask about how to maintain enough isolation to preserve >>> 14 bits of phase measurement. I think the isolation you are >>> worried about it in the VHF range, no? That is the domain of RF >>> design and not at all trivial. I think you will need to provide >>> more info on design specifics. >>> >>> I'm not clear on how you plan to do the phase detector. Is this >>> just subtracting the reference signal from the signal being >>> measured? You then scan the phase of the reference to find the >>> null, scan the amplitude of the reference to optimize the null >>> and then possibly repeat? Otherwise I'm not sure how you get >>> both phase and amplitude out of this. >>> >> The phase detector will probably be a diode bridge type, e.g. a >> Mini Circuits MPD-1. It's approximately a multiplier. > > Why not use a real multiplier? Analog Devices have a couple of pretty > good analog multiplier chips. AD734 and AD834 come to mind.The beauty of the nulling technique is that you don't depend on the accuracy of the phase detector characteristic--it just has to have stable nulls, which the MPD-1 has. I'll always be winding up at almost exactly the same relative phase, i.e. at the null.> > And if you are working at a fixed frequency, running the DDS > staircase approximation to a sine wave through an integrator (with > the right gain) turns it into a straight-line interpolation > approximation to a sine wave, which is a lot nicer, (and slightly > easier to filter).I've been reading the references everybody's been citing, and they're pretty illuminating. Re: subharmonics due to residual phase accumulator values Since I can pick the LO any way I like, I'll just use an integer multiple of f_clock / 2**14, which ought to get rid of the subharmonic problem, since the value in the phase accumulator will be the same at the beginning of each cycle, to the bit width of the lookup table. With a 400-MHz DDS, those are only 24 kHz apart, so there will be no problem finding one inside whatever filter passband I wind up with. I've often used 10.7 MHz ceramic IF filters (as Rick Karlquist suggests in that excellent paper referenced upthread), so I might do that again, although I'll need a wider one after the variable phase oscillator, because a 14-bit conversion at 100 kHz would leave me only about 7 cycles per bit. I'd probably need to resynchronize the comparator output anyway, to make sure I'm always sampling at the null of the residual phase detector ripple. Or maybe I should just use one of JL's ECLiPS Lite D-flops for the phase detector instead. With a 1-ps decision time, that would be good for N = -log_2(10.7 MHz * 1 ps) = 16.5 bits per cycle, with no waiting. I might put both on the board, just for educational purposes. (They may or may not use this exact board for the product, but a pop option is cheap anyway.) There will be a bit of phase nonlinearity due to the phase shifting action interacting with the lookup table, but I can probably live with that OK. A Karlquist-esque approach to fixing that would be to use a higher frequency DDS followed by a pulse-swallowing counter, but with a 14-bit DDS and a bit of averaging, I doubt I'll need it. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Reply by ●December 5, 20142014-12-05
On 12/5/2014 1:26 AM, Tom Swift wrote:> Phil Hobbs <hobbs@electrooptical.net> wrote: > >> On 12/4/2014 7:44 PM, Joe Gwinn wrote: > >>> Also beware phase jumps when the DDS phase wheel rolls over. > >> Could you elaborate a bit? I thought the whole idea was to keep phase >> continuity. > >> Thanks > >> Phil Hobbs > > Joe is right. Most DDS are 32 bits. As I understand it, when you program > in a frequency, there are some bits left over. When the counter rolls > over, these do not align with the starting phase. Depending on the clock > and output frequencies, there will be a phase bump every several seconds > or so. > > Time-Nuts has a number of threads discussing this issue. I could not find > the particular thread I was looking for, but you might be interested in > this one that has some very useful information buried in various posts. > > The thread is "DDS in GPSDO design?", at > > https://www.febo.com/pipermail/time-nuts/2012-May/067573.html > > There are several more threads on the same issue. You can search the > archives using > > https://www.febo.com/pipermail/time-nuts/ "Your Search String" >Thanks, that's interesting. Sticking to integer multiples of f_clock / 2**14 should fix it, no? Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Reply by ●December 5, 20142014-12-05
On Fri, 05 Dec 2014 10:32:04 -0500, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>On 12/5/2014 7:54 AM, Bill Sloman wrote: >> On Friday, 5 December 2014 14:27:37 UTC+11, Phil Hobbs wrote: >>> On 12/4/2014 7:10 PM, rickman wrote: >>>> On 12/4/2014 3:04 PM, Phil Hobbs wrote: >>>>> Hi, all, >>>>> >>>>> I have a gig coming in that will have me revisiting my thesis >>>>> research from nearly 30 years ago, on interferometric laser >>>>> microscopes. (Fun.) >>>>> >>>>> Back in the day, I made a nulling-type phase digitizer at 60 >>>>> MHz by driving a phase shifter with a 12-bit DAC (AD-DAC80), >>>>> and wrapping a 13-bit successive approximation loop round it >>>>> (AM2904 with an extra flipflop). With quite a lot of >>>>> calibration, that got me a 13-bit, 2-pi, 50 ks/s phase >>>>> measurement that I was pretty happy with. (The extra bit came >>>>> from deciding which null to head for, which is why I needed >>>>> the extra FF.) It was all interfaced to an HP 9816 computer >>>>> via a GPIO card, and (eventually) worked great. I published >>>>> one of my only two instruments papers on it (this was before I >>>>> realized the total futility of almost all instruments papers). >>>>> >>>>> The advantage of nulling detection is that you only need 1-D >>>>> calibration tables for phase shift and amplitude, whereas >>>>> getting that sort of accuracy with I/Q techniques requires a >>>>> 2-D calibration table, which is a gigantic pain. >>>>> >>>>> I need to do this again, 2015 style. The speed requirements >>>>> are set by the acoustic delay in the AO scanner, so 50-100 ks/s >>>>> is about all I can use. Rather than all that squishy analogue >>>>> stuff, I'm planning to do the SAR in software and use a pair of >>>>> AD9951 DDS chips, one to generate the desired signal and one to >>>>> be the phase shifted comparison signal. >>>>> >>>>> So far so straightforward. >>>>> >>>>> What I'm less sure about is being able to keep the two >>>>> channels sufficiently isolated to be able to maintain 12 or >>>>> ideally 14 bits of phase accuracy. Even with a full-scale >>>>> input, I'll need 85 dB of isolation to get 14 bits, and it gets >>>>> harder with weaker signals. (There'll be a DLVA/limiter ahead >>>>> of the phase detector, which will help.) >>>>> >>>>> I've never used DDSes before, and I'd appreciate some wisdom >>>>> from folks who have. How hard is that likely to be, and what >>>>> should I particularly watch out for? >>>> >>>> I've read all the posts so far and it seems you are generating a >>>> VHF sine wave to compare to a VHF signal you wish to measure the >>>> phase and amplitude of. I think I get that. But it seems the >>>> modulation of the VHF signal is pretty low rate so that 50 kSPS >>>> is good enough. >>>> >>>> Then you ask about how to maintain enough isolation to preserve >>>> 14 bits of phase measurement. I think the isolation you are >>>> worried about it in the VHF range, no? That is the domain of RF >>>> design and not at all trivial. I think you will need to provide >>>> more info on design specifics. >>>> >>>> I'm not clear on how you plan to do the phase detector. Is this >>>> just subtracting the reference signal from the signal being >>>> measured? You then scan the phase of the reference to find the >>>> null, scan the amplitude of the reference to optimize the null >>>> and then possibly repeat? Otherwise I'm not sure how you get >>>> both phase and amplitude out of this. >>>> >>> The phase detector will probably be a diode bridge type, e.g. a >>> Mini Circuits MPD-1. It's approximately a multiplier. >> >> Why not use a real multiplier? Analog Devices have a couple of pretty >> good analog multiplier chips. AD734 and AD834 come to mind. > >The beauty of the nulling technique is that you don't depend on the >accuracy of the phase detector characteristic--it just has to have >stable nulls, which the MPD-1 has. I'll always be winding up at almost >exactly the same relative phase, i.e. at the null. > >> >> And if you are working at a fixed frequency, running the DDS >> staircase approximation to a sine wave through an integrator (with >> the right gain) turns it into a straight-line interpolation >> approximation to a sine wave, which is a lot nicer, (and slightly >> easier to filter). > >I've been reading the references everybody's been citing, and they're >pretty illuminating. > >Re: subharmonics due to residual phase accumulator values > >Since I can pick the LO any way I like, I'll just use an integer >multiple of f_clock / 2**14, which ought to get rid of the subharmonic >problem, since the value in the phase accumulator will be the same at >the beginning of each cycle, to the bit width of the lookup table. With >a 400-MHz DDS, those are only 24 kHz apart, so there will be no problem >finding one inside whatever filter passband I wind up with.Right. That amounts to a counter/lookup-table/DAC. Seweet spots in the DDS frequency list. No squirmies.> >I've often used 10.7 MHz ceramic IF filters (as Rick Karlquist suggests >in that excellent paper referenced upthread), so I might do that again, >although I'll need a wider one after the variable phase oscillator, >because a 14-bit conversion at 100 kHz would leave me only about 7 >cycles per bit. > >I'd probably need to resynchronize the comparator output anyway, to make >sure I'm always sampling at the null of the residual phase detector >ripple. > >Or maybe I should just use one of JL's ECLiPS Lite D-flops for the phase >detector instead. With a 1-ps decision time, that would be good for > >N = -log_2(10.7 MHz * 1 ps) = 16.5 bitsEven better with averaging! You can make a sampling oscilloscope, too, with a minor variant of the bang-bang phase detector, using very few parts. -- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by ●December 5, 20142014-12-05
On Fri, 05 Dec 2014 09:43:14 -0800, John Larkin wrote:> On Fri, 05 Dec 2014 10:32:04 -0500, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > >>On 12/5/2014 7:54 AM, Bill Sloman wrote: >>> On Friday, 5 December 2014 14:27:37 UTC+11, Phil Hobbs wrote: >>>> On 12/4/2014 7:10 PM, rickman wrote: >>>>> On 12/4/2014 3:04 PM, Phil Hobbs wrote: >>>>>> Hi, all, >>>>>> >>>>>> I have a gig coming in that will have me revisiting my thesis >>>>>> research from nearly 30 years ago, on interferometric laser >>>>>> microscopes. (Fun.) >>>>>> >>>>>> Back in the day, I made a nulling-type phase digitizer at 60 MHz by >>>>>> driving a phase shifter with a 12-bit DAC (AD-DAC80), and wrapping >>>>>> a 13-bit successive approximation loop round it (AM2904 with an >>>>>> extra flipflop). With quite a lot of calibration, that got me a >>>>>> 13-bit, 2-pi, 50 ks/s phase measurement that I was pretty happy >>>>>> with. (The extra bit came from deciding which null to head for, >>>>>> which is why I needed the extra FF.) It was all interfaced to an >>>>>> HP 9816 computer via a GPIO card, and (eventually) worked great. I >>>>>> published one of my only two instruments papers on it (this was >>>>>> before I realized the total futility of almost all instruments >>>>>> papers). >>>>>> >>>>>> The advantage of nulling detection is that you only need 1-D >>>>>> calibration tables for phase shift and amplitude, whereas getting >>>>>> that sort of accuracy with I/Q techniques requires a 2-D >>>>>> calibration table, which is a gigantic pain. >>>>>> >>>>>> I need to do this again, 2015 style. The speed requirements are >>>>>> set by the acoustic delay in the AO scanner, so 50-100 ks/s is >>>>>> about all I can use. Rather than all that squishy analogue stuff, >>>>>> I'm planning to do the SAR in software and use a pair of AD9951 DDS >>>>>> chips, one to generate the desired signal and one to be the phase >>>>>> shifted comparison signal. >>>>>> >>>>>> So far so straightforward. >>>>>> >>>>>> What I'm less sure about is being able to keep the two channels >>>>>> sufficiently isolated to be able to maintain 12 or ideally 14 bits >>>>>> of phase accuracy. Even with a full-scale input, I'll need 85 dB >>>>>> of isolation to get 14 bits, and it gets harder with weaker >>>>>> signals. (There'll be a DLVA/limiter ahead of the phase detector, >>>>>> which will help.) >>>>>> >>>>>> I've never used DDSes before, and I'd appreciate some wisdom from >>>>>> folks who have. How hard is that likely to be, and what should I >>>>>> particularly watch out for? >>>>> >>>>> I've read all the posts so far and it seems you are generating a VHF >>>>> sine wave to compare to a VHF signal you wish to measure the phase >>>>> and amplitude of. I think I get that. But it seems the modulation >>>>> of the VHF signal is pretty low rate so that 50 kSPS is good enough. >>>>> >>>>> Then you ask about how to maintain enough isolation to preserve 14 >>>>> bits of phase measurement. I think the isolation you are worried >>>>> about it in the VHF range, no? That is the domain of RF design and >>>>> not at all trivial. I think you will need to provide more info on >>>>> design specifics. >>>>> >>>>> I'm not clear on how you plan to do the phase detector. Is this >>>>> just subtracting the reference signal from the signal being >>>>> measured? You then scan the phase of the reference to find the >>>>> null, scan the amplitude of the reference to optimize the null and >>>>> then possibly repeat? Otherwise I'm not sure how you get both phase >>>>> and amplitude out of this. >>>>> >>>> The phase detector will probably be a diode bridge type, e.g. a Mini >>>> Circuits MPD-1. It's approximately a multiplier. >>> >>> Why not use a real multiplier? Analog Devices have a couple of pretty >>> good analog multiplier chips. AD734 and AD834 come to mind. >> >>The beauty of the nulling technique is that you don't depend on the >>accuracy of the phase detector characteristic--it just has to have >>stable nulls, which the MPD-1 has. I'll always be winding up at almost >>exactly the same relative phase, i.e. at the null. >> >> >>> And if you are working at a fixed frequency, running the DDS staircase >>> approximation to a sine wave through an integrator (with the right >>> gain) turns it into a straight-line interpolation approximation to a >>> sine wave, which is a lot nicer, (and slightly easier to filter). >> >>I've been reading the references everybody's been citing, and they're >>pretty illuminating. >> >>Re: subharmonics due to residual phase accumulator values >> >>Since I can pick the LO any way I like, I'll just use an integer >>multiple of f_clock / 2**14, which ought to get rid of the subharmonic >>problem, since the value in the phase accumulator will be the same at >>the beginning of each cycle, to the bit width of the lookup table. With >>a 400-MHz DDS, those are only 24 kHz apart, so there will be no problem >>finding one inside whatever filter passband I wind up with. > > Right. That amounts to a counter/lookup-table/DAC. Seweet spots in the > DDS frequency list. No squirmies. > > > >>I've often used 10.7 MHz ceramic IF filters (as Rick Karlquist suggests >>in that excellent paper referenced upthread), so I might do that again, >>although I'll need a wider one after the variable phase oscillator, >>because a 14-bit conversion at 100 kHz would leave me only about 7 >>cycles per bit. >> >>I'd probably need to resynchronize the comparator output anyway, to make >>sure I'm always sampling at the null of the residual phase detector >>ripple. >> >>Or maybe I should just use one of JL's ECLiPS Lite D-flops for the phase >>detector instead. With a 1-ps decision time, that would be good for >> >>N = -log_2(10.7 MHz * 1 ps) = 16.5 bits > > Even better with averaging! > > You can make a sampling oscilloscope, too, with a minor variant of the > bang-bang phase detector, using very few parts.I was wondering if perhaps making a sampler to work at your frequency, running into an ADC that can be trusted to 16 bits and thence to a micro, might not work well. If you're picking your frequencies it should be easy to get a sampling ratio that'll give you reasonable frequencies at the ADC. The older I get, the less I want to have DC-coupled analog circuitry for high-precision applications. AC-coupled into an ADC, and then processing in digital-land where it's easy to buy as much precision as you need, seems to work well for me. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by ●December 5, 20142014-12-05
On 12/5/2014 12:43 PM, John Larkin wrote:> On Fri, 05 Dec 2014 10:32:04 -0500, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> On 12/5/2014 7:54 AM, Bill Sloman wrote: >>> On Friday, 5 December 2014 14:27:37 UTC+11, Phil Hobbs wrote: >>>> On 12/4/2014 7:10 PM, rickman wrote: >>>>> On 12/4/2014 3:04 PM, Phil Hobbs wrote: >>>>>> Hi, all, >>>>>> >>>>>> I have a gig coming in that will have me revisiting my thesis >>>>>> research from nearly 30 years ago, on interferometric laser >>>>>> microscopes. (Fun.) >>>>>> >>>>>> Back in the day, I made a nulling-type phase digitizer at 60 >>>>>> MHz by driving a phase shifter with a 12-bit DAC (AD-DAC80), >>>>>> and wrapping a 13-bit successive approximation loop round it >>>>>> (AM2904 with an extra flipflop). With quite a lot of >>>>>> calibration, that got me a 13-bit, 2-pi, 50 ks/s phase >>>>>> measurement that I was pretty happy with. (The extra bit came >>>>>> from deciding which null to head for, which is why I needed >>>>>> the extra FF.) It was all interfaced to an HP 9816 computer >>>>>> via a GPIO card, and (eventually) worked great. I published >>>>>> one of my only two instruments papers on it (this was before I >>>>>> realized the total futility of almost all instruments papers). >>>>>> >>>>>> The advantage of nulling detection is that you only need 1-D >>>>>> calibration tables for phase shift and amplitude, whereas >>>>>> getting that sort of accuracy with I/Q techniques requires a >>>>>> 2-D calibration table, which is a gigantic pain. >>>>>> >>>>>> I need to do this again, 2015 style. The speed requirements >>>>>> are set by the acoustic delay in the AO scanner, so 50-100 ks/s >>>>>> is about all I can use. Rather than all that squishy analogue >>>>>> stuff, I'm planning to do the SAR in software and use a pair of >>>>>> AD9951 DDS chips, one to generate the desired signal and one to >>>>>> be the phase shifted comparison signal. >>>>>> >>>>>> So far so straightforward. >>>>>> >>>>>> What I'm less sure about is being able to keep the two >>>>>> channels sufficiently isolated to be able to maintain 12 or >>>>>> ideally 14 bits of phase accuracy. Even with a full-scale >>>>>> input, I'll need 85 dB of isolation to get 14 bits, and it gets >>>>>> harder with weaker signals. (There'll be a DLVA/limiter ahead >>>>>> of the phase detector, which will help.) >>>>>> >>>>>> I've never used DDSes before, and I'd appreciate some wisdom >>>>>> from folks who have. How hard is that likely to be, and what >>>>>> should I particularly watch out for? >>>>> >>>>> I've read all the posts so far and it seems you are generating a >>>>> VHF sine wave to compare to a VHF signal you wish to measure the >>>>> phase and amplitude of. I think I get that. But it seems the >>>>> modulation of the VHF signal is pretty low rate so that 50 kSPS >>>>> is good enough. >>>>> >>>>> Then you ask about how to maintain enough isolation to preserve >>>>> 14 bits of phase measurement. I think the isolation you are >>>>> worried about it in the VHF range, no? That is the domain of RF >>>>> design and not at all trivial. I think you will need to provide >>>>> more info on design specifics. >>>>> >>>>> I'm not clear on how you plan to do the phase detector. Is this >>>>> just subtracting the reference signal from the signal being >>>>> measured? You then scan the phase of the reference to find the >>>>> null, scan the amplitude of the reference to optimize the null >>>>> and then possibly repeat? Otherwise I'm not sure how you get >>>>> both phase and amplitude out of this. >>>>> >>>> The phase detector will probably be a diode bridge type, e.g. a >>>> Mini Circuits MPD-1. It's approximately a multiplier. >>> >>> Why not use a real multiplier? Analog Devices have a couple of pretty >>> good analog multiplier chips. AD734 and AD834 come to mind. >> >> The beauty of the nulling technique is that you don't depend on the >> accuracy of the phase detector characteristic--it just has to have >> stable nulls, which the MPD-1 has. I'll always be winding up at almost >> exactly the same relative phase, i.e. at the null. >> >>> >>> And if you are working at a fixed frequency, running the DDS >>> staircase approximation to a sine wave through an integrator (with >>> the right gain) turns it into a straight-line interpolation >>> approximation to a sine wave, which is a lot nicer, (and slightly >>> easier to filter). >> >> I've been reading the references everybody's been citing, and they're >> pretty illuminating. >> >> Re: subharmonics due to residual phase accumulator values >> >> Since I can pick the LO any way I like, I'll just use an integer >> multiple of f_clock / 2**14, which ought to get rid of the subharmonic >> problem, since the value in the phase accumulator will be the same at >> the beginning of each cycle, to the bit width of the lookup table. With >> a 400-MHz DDS, those are only 24 kHz apart, so there will be no problem >> finding one inside whatever filter passband I wind up with. > > Right. That amounts to a counter/lookup-table/DAC. Seweet spots in the > DDS frequency list. No squirmies. > > >> >> I've often used 10.7 MHz ceramic IF filters (as Rick Karlquist suggests >> in that excellent paper referenced upthread), so I might do that again, >> although I'll need a wider one after the variable phase oscillator, >> because a 14-bit conversion at 100 kHz would leave me only about 7 >> cycles per bit. >> >> I'd probably need to resynchronize the comparator output anyway, to make >> sure I'm always sampling at the null of the residual phase detector >> ripple. >> >> Or maybe I should just use one of JL's ECLiPS Lite D-flops for the phase >> detector instead. With a 1-ps decision time, that would be good for >> >> N = -log_2(10.7 MHz * 1 ps) = 16.5 bits > > Even better with averaging! > > You can make a sampling oscilloscope, too, with a minor variant of the > bang-bang phase detector, using very few parts.Averaging would be pretty simple--use its output to gate the 10.7 MHz into a counter input of the MCU. With 7 cycles per bit, I'd theoretically get 19 bits. Awesome. Which leads to the next question, namely layout and clock distribution. In my original setup, I built a calibrator that was much more complicated than the digitizer itself. It had two separate 60 MHz synthesizers, running at a reference frequency of 600 kHz (divide-by-100). One of them used a 10/11 dual modulus prescaler, so that I could swallow individual pulses and so make the phase walk around by 3.6-degree steps. Before using the microscope, I ran the phase shifter calibration and did a normal cubic spline fit to the results, which worked fine as long as everything was well warmed up. That strategy lives and dies by the isolation between channels. I used a bunch of isolation amps, based on MRF966 dual-gate GaAs FETs, which were good enough for 70-dB isolation at 100 MHz in one stage--and the whole thing was a dead-bug proto. It used a lot of bolted-together aluminum boxes and double-shielded coax, and was about 18 inches square. But the isolation was very good--when I leaned on the "pulse swallow" button, which moved one synthesizer off by 600 kHz, I could see on the spectrum analyzer that the leakage was at the -90 dBc level. This one is going to be on the same board, talking to the same processor, and so on. I'm planning to run the two synths on their own power supplies, with buffers on the digital lines that are also run from those supplies, and run all their traces on interior levels between two ground pours with via stitching. It's really the clock distribution and especially the local grounding and decoupling at the DDSes that I'm worried about. You're generally a fan of just connecting all the flavours of ground to a single featureless plane, with an equally featureless supply plane next to it. Is that the right answer here as well, or do I risk extra spurs that way? Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
