Forums

DDS wisdom

Started by Phil Hobbs December 4, 2014
On 12/5/2014 1:36 PM, Tim Wescott wrote:
> On Fri, 05 Dec 2014 09:43:14 -0800, John Larkin wrote: > >> On Fri, 05 Dec 2014 10:32:04 -0500, Phil Hobbs >> <pcdhSpamMeSenseless@electrooptical.net> wrote: >> >>> On 12/5/2014 7:54 AM, Bill Sloman wrote: >>>> On Friday, 5 December 2014 14:27:37 UTC+11, Phil Hobbs wrote: >>>>> On 12/4/2014 7:10 PM, rickman wrote: >>>>>> On 12/4/2014 3:04 PM, Phil Hobbs wrote: >>>>>>> Hi, all, >>>>>>> >>>>>>> I have a gig coming in that will have me revisiting my >>>>>>> thesis research from nearly 30 years ago, on >>>>>>> interferometric laser microscopes. (Fun.) >>>>>>> >>>>>>> Back in the day, I made a nulling-type phase digitizer >>>>>>> at 60 MHz by driving a phase shifter with a 12-bit DAC >>>>>>> (AD-DAC80), and wrapping a 13-bit successive >>>>>>> approximation loop round it (AM2904 with an extra >>>>>>> flipflop). With quite a lot of calibration, that got me >>>>>>> a 13-bit, 2-pi, 50 ks/s phase measurement that I was >>>>>>> pretty happy with. (The extra bit came from deciding >>>>>>> which null to head for, which is why I needed the extra >>>>>>> FF.) It was all interfaced to an HP 9816 computer via a >>>>>>> GPIO card, and (eventually) worked great. I published >>>>>>> one of my only two instruments papers on it (this was >>>>>>> before I realized the total futility of almost all >>>>>>> instruments papers). >>>>>>> >>>>>>> The advantage of nulling detection is that you only need >>>>>>> 1-D calibration tables for phase shift and amplitude, >>>>>>> whereas getting that sort of accuracy with I/Q >>>>>>> techniques requires a 2-D calibration table, which is a >>>>>>> gigantic pain. >>>>>>> >>>>>>> I need to do this again, 2015 style. The speed >>>>>>> requirements are set by the acoustic delay in the AO >>>>>>> scanner, so 50-100 ks/s is about all I can use. Rather >>>>>>> than all that squishy analogue stuff, I'm planning to do >>>>>>> the SAR in software and use a pair of AD9951 DDS chips, >>>>>>> one to generate the desired signal and one to be the >>>>>>> phase shifted comparison signal. >>>>>>> >>>>>>> So far so straightforward. >>>>>>> >>>>>>> What I'm less sure about is being able to keep the two >>>>>>> channels sufficiently isolated to be able to maintain 12 >>>>>>> or ideally 14 bits of phase accuracy. Even with a >>>>>>> full-scale input, I'll need 85 dB of isolation to get 14 >>>>>>> bits, and it gets harder with weaker signals. (There'll >>>>>>> be a DLVA/limiter ahead of the phase detector, which will >>>>>>> help.) >>>>>>> >>>>>>> I've never used DDSes before, and I'd appreciate some >>>>>>> wisdom from folks who have. How hard is that likely to >>>>>>> be, and what should I particularly watch out for? >>>>>> >>>>>> I've read all the posts so far and it seems you are >>>>>> generating a VHF sine wave to compare to a VHF signal you >>>>>> wish to measure the phase and amplitude of. I think I get >>>>>> that. But it seems the modulation of the VHF signal is >>>>>> pretty low rate so that 50 kSPS is good enough. >>>>>> >>>>>> Then you ask about how to maintain enough isolation to >>>>>> preserve 14 bits of phase measurement. I think the >>>>>> isolation you are worried about it in the VHF range, no? >>>>>> That is the domain of RF design and not at all trivial. I >>>>>> think you will need to provide more info on design >>>>>> specifics. >>>>>> >>>>>> I'm not clear on how you plan to do the phase detector. Is >>>>>> this just subtracting the reference signal from the signal >>>>>> being measured? You then scan the phase of the reference >>>>>> to find the null, scan the amplitude of the reference to >>>>>> optimize the null and then possibly repeat? Otherwise I'm >>>>>> not sure how you get both phase and amplitude out of this. >>>>>> >>>>> The phase detector will probably be a diode bridge type, >>>>> e.g. a Mini Circuits MPD-1. It's approximately a >>>>> multiplier. >>>> >>>> Why not use a real multiplier? Analog Devices have a couple of >>>> pretty good analog multiplier chips. AD734 and AD834 come to >>>> mind. >>> >>> The beauty of the nulling technique is that you don't depend on >>> the accuracy of the phase detector characteristic--it just has >>> to have stable nulls, which the MPD-1 has. I'll always be winding >>> up at almost exactly the same relative phase, i.e. at the null. >>> >>> >>>> And if you are working at a fixed frequency, running the DDS >>>> staircase approximation to a sine wave through an integrator >>>> (with the right gain) turns it into a straight-line >>>> interpolation approximation to a sine wave, which is a lot >>>> nicer, (and slightly easier to filter). >>> >>> I've been reading the references everybody's been citing, and >>> they're pretty illuminating. >>> >>> Re: subharmonics due to residual phase accumulator values >>> >>> Since I can pick the LO any way I like, I'll just use an integer >>> multiple of f_clock / 2**14, which ought to get rid of the >>> subharmonic problem, since the value in the phase accumulator >>> will be the same at the beginning of each cycle, to the bit >>> width of the lookup table. With a 400-MHz DDS, those are only 24 >>> kHz apart, so there will be no problem finding one inside >>> whatever filter passband I wind up with. >> >> Right. That amounts to a counter/lookup-table/DAC. Seweet spots in >> the DDS frequency list. No squirmies. >> >> >> >>> I've often used 10.7 MHz ceramic IF filters (as Rick Karlquist >>> suggests in that excellent paper referenced upthread), so I >>> might do that again, although I'll need a wider one after the >>> variable phase oscillator, because a 14-bit conversion at 100 kHz >>> would leave me only about 7 cycles per bit. >>> >>> I'd probably need to resynchronize the comparator output anyway, >>> to make sure I'm always sampling at the null of the residual >>> phase detector ripple. >>> >>> Or maybe I should just use one of JL's ECLiPS Lite D-flops for >>> the phase detector instead. With a 1-ps decision time, that >>> would be good for >>> >>> N = -log_2(10.7 MHz * 1 ps) = 16.5 bits >> >> Even better with averaging! >> >> You can make a sampling oscilloscope, too, with a minor variant of >> the bang-bang phase detector, using very few parts. > > I was wondering if perhaps making a sampler to work at your > frequency, running into an ADC that can be trusted to 16 bits and > thence to a micro, might not work well. > > If you're picking your frequencies it should be easy to get a > sampling ratio that'll give you reasonable frequencies at the ADC. > > The older I get, the less I want to have DC-coupled analog circuitry > for high-precision applications. AC-coupled into an ADC, and then > processing in digital-land where it's easy to buy as much precision > as you need, seems to work well for me.
If there were more time available, that might be a good approach. As I say, though, I'm a one man band on this whole thing, and building a sampler that good (5 ps or so jitter) would be a bit of a science project for me. (I wouldn't mind having a go some time, but a board turn would be a Very Bad Thing on this job.) Phase detectors operated at null, I'm happy with, and doing the sampling digitally with a D-flop would be pretty simple too, though I haven't used ECL since the MC10K days, and not much even then. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
On Fri, 05 Dec 2014 13:51:32 -0500, Phil Hobbs
<hobbs@electrooptical.net> wrote:

>On 12/5/2014 1:36 PM, Tim Wescott wrote: >> On Fri, 05 Dec 2014 09:43:14 -0800, John Larkin wrote: >> >>> On Fri, 05 Dec 2014 10:32:04 -0500, Phil Hobbs >>> <pcdhSpamMeSenseless@electrooptical.net> wrote: >>> >>>> On 12/5/2014 7:54 AM, Bill Sloman wrote: >>>>> On Friday, 5 December 2014 14:27:37 UTC+11, Phil Hobbs wrote: >>>>>> On 12/4/2014 7:10 PM, rickman wrote: >>>>>>> On 12/4/2014 3:04 PM, Phil Hobbs wrote: >>>>>>>> Hi, all, >>>>>>>> >>>>>>>> I have a gig coming in that will have me revisiting my >>>>>>>> thesis research from nearly 30 years ago, on >>>>>>>> interferometric laser microscopes. (Fun.) >>>>>>>> >>>>>>>> Back in the day, I made a nulling-type phase digitizer >>>>>>>> at 60 MHz by driving a phase shifter with a 12-bit DAC >>>>>>>> (AD-DAC80), and wrapping a 13-bit successive >>>>>>>> approximation loop round it (AM2904 with an extra >>>>>>>> flipflop). With quite a lot of calibration, that got me >>>>>>>> a 13-bit, 2-pi, 50 ks/s phase measurement that I was >>>>>>>> pretty happy with. (The extra bit came from deciding >>>>>>>> which null to head for, which is why I needed the extra >>>>>>>> FF.) It was all interfaced to an HP 9816 computer via a >>>>>>>> GPIO card, and (eventually) worked great. I published >>>>>>>> one of my only two instruments papers on it (this was >>>>>>>> before I realized the total futility of almost all >>>>>>>> instruments papers). >>>>>>>> >>>>>>>> The advantage of nulling detection is that you only need >>>>>>>> 1-D calibration tables for phase shift and amplitude, >>>>>>>> whereas getting that sort of accuracy with I/Q >>>>>>>> techniques requires a 2-D calibration table, which is a >>>>>>>> gigantic pain. >>>>>>>> >>>>>>>> I need to do this again, 2015 style. The speed >>>>>>>> requirements are set by the acoustic delay in the AO >>>>>>>> scanner, so 50-100 ks/s is about all I can use. Rather >>>>>>>> than all that squishy analogue stuff, I'm planning to do >>>>>>>> the SAR in software and use a pair of AD9951 DDS chips, >>>>>>>> one to generate the desired signal and one to be the >>>>>>>> phase shifted comparison signal. >>>>>>>> >>>>>>>> So far so straightforward. >>>>>>>> >>>>>>>> What I'm less sure about is being able to keep the two >>>>>>>> channels sufficiently isolated to be able to maintain 12 >>>>>>>> or ideally 14 bits of phase accuracy. Even with a >>>>>>>> full-scale input, I'll need 85 dB of isolation to get 14 >>>>>>>> bits, and it gets harder with weaker signals. (There'll >>>>>>>> be a DLVA/limiter ahead of the phase detector, which will >>>>>>>> help.) >>>>>>>> >>>>>>>> I've never used DDSes before, and I'd appreciate some >>>>>>>> wisdom from folks who have. How hard is that likely to >>>>>>>> be, and what should I particularly watch out for? >>>>>>> >>>>>>> I've read all the posts so far and it seems you are >>>>>>> generating a VHF sine wave to compare to a VHF signal you >>>>>>> wish to measure the phase and amplitude of. I think I get >>>>>>> that. But it seems the modulation of the VHF signal is >>>>>>> pretty low rate so that 50 kSPS is good enough. >>>>>>> >>>>>>> Then you ask about how to maintain enough isolation to >>>>>>> preserve 14 bits of phase measurement. I think the >>>>>>> isolation you are worried about it in the VHF range, no? >>>>>>> That is the domain of RF design and not at all trivial. I >>>>>>> think you will need to provide more info on design >>>>>>> specifics. >>>>>>> >>>>>>> I'm not clear on how you plan to do the phase detector. Is >>>>>>> this just subtracting the reference signal from the signal >>>>>>> being measured? You then scan the phase of the reference >>>>>>> to find the null, scan the amplitude of the reference to >>>>>>> optimize the null and then possibly repeat? Otherwise I'm >>>>>>> not sure how you get both phase and amplitude out of this. >>>>>>> >>>>>> The phase detector will probably be a diode bridge type, >>>>>> e.g. a Mini Circuits MPD-1. It's approximately a >>>>>> multiplier. >>>>> >>>>> Why not use a real multiplier? Analog Devices have a couple of >>>>> pretty good analog multiplier chips. AD734 and AD834 come to >>>>> mind. >>>> >>>> The beauty of the nulling technique is that you don't depend on >>>> the accuracy of the phase detector characteristic--it just has >>>> to have stable nulls, which the MPD-1 has. I'll always be winding >>>> up at almost exactly the same relative phase, i.e. at the null. >>>> >>>> >>>>> And if you are working at a fixed frequency, running the DDS >>>>> staircase approximation to a sine wave through an integrator >>>>> (with the right gain) turns it into a straight-line >>>>> interpolation approximation to a sine wave, which is a lot >>>>> nicer, (and slightly easier to filter). >>>> >>>> I've been reading the references everybody's been citing, and >>>> they're pretty illuminating. >>>> >>>> Re: subharmonics due to residual phase accumulator values >>>> >>>> Since I can pick the LO any way I like, I'll just use an integer >>>> multiple of f_clock / 2**14, which ought to get rid of the >>>> subharmonic problem, since the value in the phase accumulator >>>> will be the same at the beginning of each cycle, to the bit >>>> width of the lookup table. With a 400-MHz DDS, those are only 24 >>>> kHz apart, so there will be no problem finding one inside >>>> whatever filter passband I wind up with. >>> >>> Right. That amounts to a counter/lookup-table/DAC. Seweet spots in >>> the DDS frequency list. No squirmies. >>> >>> >>> >>>> I've often used 10.7 MHz ceramic IF filters (as Rick Karlquist >>>> suggests in that excellent paper referenced upthread), so I >>>> might do that again, although I'll need a wider one after the >>>> variable phase oscillator, because a 14-bit conversion at 100 kHz >>>> would leave me only about 7 cycles per bit. >>>> >>>> I'd probably need to resynchronize the comparator output anyway, >>>> to make sure I'm always sampling at the null of the residual >>>> phase detector ripple. >>>> >>>> Or maybe I should just use one of JL's ECLiPS Lite D-flops for >>>> the phase detector instead. With a 1-ps decision time, that >>>> would be good for >>>> >>>> N = -log_2(10.7 MHz * 1 ps) = 16.5 bits >>> >>> Even better with averaging! >>> >>> You can make a sampling oscilloscope, too, with a minor variant of >>> the bang-bang phase detector, using very few parts. >> >> I was wondering if perhaps making a sampler to work at your >> frequency, running into an ADC that can be trusted to 16 bits and >> thence to a micro, might not work well. >> >> If you're picking your frequencies it should be easy to get a >> sampling ratio that'll give you reasonable frequencies at the ADC. >> >> The older I get, the less I want to have DC-coupled analog circuitry >> for high-precision applications. AC-coupled into an ADC, and then >> processing in digital-land where it's easy to buy as much precision >> as you need, seems to work well for me. > >If there were more time available, that might be a good approach. As I >say, though, I'm a one man band on this whole thing, and building a >sampler that good (5 ps or so jitter) would be a bit of a science >project for me. (I wouldn't mind having a go some time, but a board >turn would be a Very Bad Thing on this job.) > >Phase detectors operated at null, I'm happy with, and doing the sampling >digitally with a D-flop would be pretty simple too, though I haven't >used ECL since the MC10K days, and not much even then. > >Cheers > >Phil Hobbs
You could use one of the ADI blinding-fast analog comparators, gating on the strobe input. That would have analog precision and be simple and very low risk. A 1-bit detector allows fun algorithms, like SAR acquisition and then averaging or up/down counter tracking. Check out ADCMP567 or the more expensive, shockingly fast ADCMP582. Hmmm... strobe the comparators at the (relatively pig-slow) RF frequency, lowpass filter and digitize the comparator outputs, and you get zillions of averaged events into a cheap uP ADC. Get rid of all that old-fashioned mixer stuff. If you do something like that, I could review the schematic and layout of the board if you want. Even *I* occasionally make mistakes (yes, hard to believe) so we always have design reviews. I tend to get the hard stuff right and mess up the silly things. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Fri, 05 Dec 2014 13:42:04 -0500, Phil Hobbs
<hobbs@electrooptical.net> wrote:

>On 12/5/2014 12:43 PM, John Larkin wrote: >> On Fri, 05 Dec 2014 10:32:04 -0500, Phil Hobbs >> <pcdhSpamMeSenseless@electrooptical.net> wrote: >> >>> On 12/5/2014 7:54 AM, Bill Sloman wrote: >>>> On Friday, 5 December 2014 14:27:37 UTC+11, Phil Hobbs wrote: >>>>> On 12/4/2014 7:10 PM, rickman wrote: >>>>>> On 12/4/2014 3:04 PM, Phil Hobbs wrote: >>>>>>> Hi, all, >>>>>>> >>>>>>> I have a gig coming in that will have me revisiting my thesis >>>>>>> research from nearly 30 years ago, on interferometric laser >>>>>>> microscopes. (Fun.) >>>>>>> >>>>>>> Back in the day, I made a nulling-type phase digitizer at 60 >>>>>>> MHz by driving a phase shifter with a 12-bit DAC (AD-DAC80), >>>>>>> and wrapping a 13-bit successive approximation loop round it >>>>>>> (AM2904 with an extra flipflop). With quite a lot of >>>>>>> calibration, that got me a 13-bit, 2-pi, 50 ks/s phase >>>>>>> measurement that I was pretty happy with. (The extra bit came >>>>>>> from deciding which null to head for, which is why I needed >>>>>>> the extra FF.) It was all interfaced to an HP 9816 computer >>>>>>> via a GPIO card, and (eventually) worked great. I published >>>>>>> one of my only two instruments papers on it (this was before I >>>>>>> realized the total futility of almost all instruments papers). >>>>>>> >>>>>>> The advantage of nulling detection is that you only need 1-D >>>>>>> calibration tables for phase shift and amplitude, whereas >>>>>>> getting that sort of accuracy with I/Q techniques requires a >>>>>>> 2-D calibration table, which is a gigantic pain. >>>>>>> >>>>>>> I need to do this again, 2015 style. The speed requirements >>>>>>> are set by the acoustic delay in the AO scanner, so 50-100 ks/s >>>>>>> is about all I can use. Rather than all that squishy analogue >>>>>>> stuff, I'm planning to do the SAR in software and use a pair of >>>>>>> AD9951 DDS chips, one to generate the desired signal and one to >>>>>>> be the phase shifted comparison signal. >>>>>>> >>>>>>> So far so straightforward. >>>>>>> >>>>>>> What I'm less sure about is being able to keep the two >>>>>>> channels sufficiently isolated to be able to maintain 12 or >>>>>>> ideally 14 bits of phase accuracy. Even with a full-scale >>>>>>> input, I'll need 85 dB of isolation to get 14 bits, and it gets >>>>>>> harder with weaker signals. (There'll be a DLVA/limiter ahead >>>>>>> of the phase detector, which will help.) >>>>>>> >>>>>>> I've never used DDSes before, and I'd appreciate some wisdom >>>>>>> from folks who have. How hard is that likely to be, and what >>>>>>> should I particularly watch out for? >>>>>> >>>>>> I've read all the posts so far and it seems you are generating a >>>>>> VHF sine wave to compare to a VHF signal you wish to measure the >>>>>> phase and amplitude of. I think I get that. But it seems the >>>>>> modulation of the VHF signal is pretty low rate so that 50 kSPS >>>>>> is good enough. >>>>>> >>>>>> Then you ask about how to maintain enough isolation to preserve >>>>>> 14 bits of phase measurement. I think the isolation you are >>>>>> worried about it in the VHF range, no? That is the domain of RF >>>>>> design and not at all trivial. I think you will need to provide >>>>>> more info on design specifics. >>>>>> >>>>>> I'm not clear on how you plan to do the phase detector. Is this >>>>>> just subtracting the reference signal from the signal being >>>>>> measured? You then scan the phase of the reference to find the >>>>>> null, scan the amplitude of the reference to optimize the null >>>>>> and then possibly repeat? Otherwise I'm not sure how you get >>>>>> both phase and amplitude out of this. >>>>>> >>>>> The phase detector will probably be a diode bridge type, e.g. a >>>>> Mini Circuits MPD-1. It's approximately a multiplier. >>>> >>>> Why not use a real multiplier? Analog Devices have a couple of pretty >>>> good analog multiplier chips. AD734 and AD834 come to mind. >>> >>> The beauty of the nulling technique is that you don't depend on the >>> accuracy of the phase detector characteristic--it just has to have >>> stable nulls, which the MPD-1 has. I'll always be winding up at almost >>> exactly the same relative phase, i.e. at the null. >>> >>>> >>>> And if you are working at a fixed frequency, running the DDS >>>> staircase approximation to a sine wave through an integrator (with >>>> the right gain) turns it into a straight-line interpolation >>>> approximation to a sine wave, which is a lot nicer, (and slightly >>>> easier to filter). >>> >>> I've been reading the references everybody's been citing, and they're >>> pretty illuminating. >>> >>> Re: subharmonics due to residual phase accumulator values >>> >>> Since I can pick the LO any way I like, I'll just use an integer >>> multiple of f_clock / 2**14, which ought to get rid of the subharmonic >>> problem, since the value in the phase accumulator will be the same at >>> the beginning of each cycle, to the bit width of the lookup table. With >>> a 400-MHz DDS, those are only 24 kHz apart, so there will be no problem >>> finding one inside whatever filter passband I wind up with. >> >> Right. That amounts to a counter/lookup-table/DAC. Seweet spots in the >> DDS frequency list. No squirmies. >> >> >>> >>> I've often used 10.7 MHz ceramic IF filters (as Rick Karlquist suggests >>> in that excellent paper referenced upthread), so I might do that again, >>> although I'll need a wider one after the variable phase oscillator, >>> because a 14-bit conversion at 100 kHz would leave me only about 7 >>> cycles per bit. >>> >>> I'd probably need to resynchronize the comparator output anyway, to make >>> sure I'm always sampling at the null of the residual phase detector >>> ripple. >>> >>> Or maybe I should just use one of JL's ECLiPS Lite D-flops for the phase >>> detector instead. With a 1-ps decision time, that would be good for >>> >>> N = -log_2(10.7 MHz * 1 ps) = 16.5 bits >> >> Even better with averaging! >> >> You can make a sampling oscilloscope, too, with a minor variant of the >> bang-bang phase detector, using very few parts. > >Averaging would be pretty simple--use its output to gate the 10.7 MHz >into a counter input of the MCU. With 7 cycles per bit, I'd >theoretically get 19 bits. Awesome. > >Which leads to the next question, namely layout and clock distribution. > >In my original setup, I built a calibrator that was much more >complicated than the digitizer itself. It had two separate 60 MHz >synthesizers, running at a reference frequency of 600 kHz >(divide-by-100). One of them used a 10/11 dual modulus prescaler, so >that I could swallow individual pulses and so make the phase walk around >by 3.6-degree steps. Before using the microscope, I ran the phase >shifter calibration and did a normal cubic spline fit to the results, >which worked fine as long as everything was well warmed up. > >That strategy lives and dies by the isolation between channels. I used >a bunch of isolation amps, based on MRF966 dual-gate GaAs FETs, which >were good enough for 70-dB isolation at 100 MHz in one stage--and the >whole thing was a dead-bug proto. It used a lot of bolted-together >aluminum boxes and double-shielded coax, and was about 18 inches square. > But the isolation was very good--when I leaned on the "pulse swallow" >button, which moved one synthesizer off by 600 kHz, I could see on the >spectrum analyzer that the leakage was at the -90 dBc level. > >This one is going to be on the same board, talking to the same >processor, and so on. I'm planning to run the two synths on their own >power supplies, with buffers on the digital lines that are also run from >those supplies, and run all their traces on interior levels between two >ground pours with via stitching. > >It's really the clock distribution and especially the local grounding >and decoupling at the DDSes that I'm worried about. You're generally a >fan of just connecting all the flavours of ground to a single >featureless plane, with an equally featureless supply plane next to it. > Is that the right answer here as well, or do I risk extra spurs that way? > >Cheers > >Phil Hobbs
If my comparator idea is of any interest, the isolation situation is vastly improved. Differential PECL signals with 35 ps rise/fall times don't crosstalk much. The two DDSs could be kept far apart and converted to PECL before converging into the phase comparators. We have a sample kit from Autosplice of really cool surface-mount shield clips. A standard (or etched, custom folded Fotofab) shield box would plug onto them, as needed. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
>"Phil Hobbs" wrote in message >news:cYydnTNwFPGvIx3JnZ2dnUU7-W-dnZ2d@supernews.com...
> It was all interfaced to an HP 9816 computer
it is "to a HP 9816" You yanks should learn that it is an "a" before any word that does not start with a vowel. It is an "an" for words starting with vowels. This seems to be a pretty universal error that you guys make. It is teeth gritting to hear these persistent "an historical event" instead of "a historical event". That's my wisdom for the day. Kevin Aylward www.kevinaylward.co.uk www.anasoft.co.uk - SuperSpice
On Fri, 05 Dec 2014 20:03:32 +0000, Kevin Aylward wrote:

>>"Phil Hobbs" wrote in message >>news:cYydnTNwFPGvIx3JnZ2dnUU7-W-dnZ2d@supernews.com... > >> It was all interfaced to an HP 9816 computer > > it is "to a HP 9816" > > You yanks should learn that it is an "a" before any word that does not > start with a vowel. It is an "an" for words starting with vowels. > > This seems to be a pretty universal error that you guys make. It is > teeth gritting to hear these persistent "an historical event" instead of > "a historical event". > > That's my wisdom for the day. > > Kevin Aylward www.kevinaylward.co.uk www.anasoft.co.uk - SuperSpice
'H' is pronounced "ach" starts with an a, which is a vowel. You limeys need to learn how to read what you write _out loud_ before you get on a tirade. And that's _my_ wisdom for the day! -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
On Fri, 05 Dec 2014 14:07:37 -0600, Tim Wescott wrote:

> On Fri, 05 Dec 2014 20:03:32 +0000, Kevin Aylward wrote: > >>>"Phil Hobbs" wrote in message >>>news:cYydnTNwFPGvIx3JnZ2dnUU7-W-dnZ2d@supernews.com... >> >>> It was all interfaced to an HP 9816 computer >> >> it is "to a HP 9816" >> >> You yanks should learn that it is an "a" before any word that does not >> start with a vowel. It is an "an" for words starting with vowels. >> >> This seems to be a pretty universal error that you guys make. It is >> teeth gritting to hear these persistent "an historical event" instead >> of "a historical event". >> >> That's my wisdom for the day. >> >> Kevin Aylward www.kevinaylward.co.uk www.anasoft.co.uk - SuperSpice > > 'H' is pronounced "ach" starts with an a, which is a vowel. > > You limeys need to learn how to read what you write _out loud_ before > you get on a tirade. > > And that's _my_ wisdom for the day!
Said wisdom is even complete with a missing ", which" to keep you on your toes! -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

> Thanks, that's interesting. Sticking to integer multiples of > f_clock / 2**14 should fix it, no?
I'm not completely sure. There is also mention of using variable modulus DDS chips like the AD9913, AD9914 and AD9915 to help reduce spurs, but I can't seem to find a direct statement that they would eliminate the phase bump. There are a number of articles mentioned in the Time-Nuts archives on ultra low phase noise DDS algorithms that can be used in fpgas. There is a lot of material to cover, and I plan on building and testing each approach to find the best one. This will require oscillators with ADEV down in the 1e-13 or better, which is awfully hard to do without a hydrogen maser, which can cost upwards of $500K. There is another approach used by SRS in the SG384 signal generator. It's called "Rational Approximation". The article is available at <http://defenseelectronicsmag.com/military-defense- electronics/presenting-novel-synthesis-approach> Further description is available in "Appendix A : Rational Approximation Synthesis", starting on Page 151 of the SG384M User Manual available at http://www.thinksrs.com/downloads/PDFs/Manuals/SG380m.pdf There is another problem that might affect your precision measurements and that is phase/frequency jumps due to the crystal in the reference oscillator. These are random and can be severe. Apparently due to some kind of contamination or stress issue, and some vendors are much worse than others. Again, it takes pretty good instrumentation to find them unambiguously and not be a problem in the instrumentation itself.
> Cheers
> Phil Hobbs
On 12/5/2014 3:03 PM, Kevin Aylward wrote:
>> "Phil Hobbs" wrote in message >> news:cYydnTNwFPGvIx3JnZ2dnUU7-W-dnZ2d@supernews.com... > >> It was all interfaced to an HP 9816 computer > > it is "to a HP 9816" > > You yanks should learn that it is an "a" before any word that does not > start with a vowel. It is an "an" for words starting with vowels. > > This seems to be a pretty universal error that you guys make. It is > teeth gritting to hear these persistent "an historical event" instead of > "a historical event". > > That's my wisdom for the day. >
We all drop our haitches over 'ere, gov. ;) Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
On 12/5/2014 3:11 PM, Tom Swift wrote:
> Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> Thanks, that's interesting. Sticking to integer multiples of >> f_clock / 2**14 should fix it, no? > > I'm not completely sure. There is also mention of using variable modulus > DDS chips like the AD9913, AD9914 and AD9915 to help reduce spurs, but I > can't seem to find a direct statement that they would eliminate the phase > bump. There are a number of articles mentioned in the Time-Nuts archives > on ultra low phase noise DDS algorithms that can be used in fpgas.
What "phase bump" are you referring to? I didn't see anything mentioned I would call a "phase bump". Everything I read was about the spurs created by the limited resolution when converting the phase into the sine values. The variable modulus of the phase accumulator doesn't address the spurs at all. Using a variable modulus allows you to set the frequency exactly as long as it can be represented by the ratio of two integers and the reference clock frequency. Fout = Clock * PhaseStep / Modulus. The spurs come from the fact that the rather large phase accumulator is shortened, either by truncation or rounding to a smaller number of bits to suit the sine conversion and/or the DAC resolution. -- Rick
On 12/5/2014 3:03 PM, Kevin Aylward wrote:
>> "Phil Hobbs" wrote in message >> news:cYydnTNwFPGvIx3JnZ2dnUU7-W-dnZ2d@supernews.com... > >> It was all interfaced to an HP 9816 computer > > it is "to a HP 9816" > > You yanks should learn that it is an "a" before any word that does not > start with a vowel. It is an "an" for words starting with vowels. > > This seems to be a pretty universal error that you guys make. It is > teeth gritting to hear these persistent "an historical event" instead of > "a historical event". > > That's my wisdom for the day.
Except that rule is wrong. Using "an" is about making speech easier. Using "a" in front of a vowel sound is awkward, so "a" is changed to "an" which flows from the tongue more easily. The rule is to use "an" when the following word starts with a vowel *sound*, like honor and... istorical. lol While honor has an unsound H and so starts with a vowel sound, historical starts with a sounded H. But when used with "an" the H sound is truncated so it then fits the rule. Rather a way of backing into it, eh? I'm not saying this is "correct". But personally I don't give a rats ass about "correctness" in this case. Language is alive and rules change. This is one that is already fuzzy and using "an historical" is within the fuzz factor these days. If your teeth grit, you should talk to your dentist about bruxism. That's *my* wisdom for the day. -- Rick