DDS wisdom

On 12/5/2014 7:44 PM, Joe Gwinn wrote:
> In article <5481273A.6010107@electrooptical.net>, Phil Hobbs
> <hobbs@electrooptical.net> wrote:
>
>> On 12/4/2014 7:44 PM, Joe Gwinn wrote:
>>> In article <cYydnTNwFPGvIx3JnZ2dnUU7-W-dnZ2d@supernews.com>, Phil Hobbs
>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>
>>>> Hi, all,
>>>>
>>>> I have a gig coming in that will have me revisiting my thesis research
>>>> from nearly 30 years ago, on interferometric laser microscopes.  (Fun.)
>>>>
>>>> Back in the day, I made a nulling-type phase digitizer at 60 MHz by
>>>> driving a phase shifter with a 12-bit DAC (AD-DAC80), and wrapping a
>>>> 13-bit successive approximation loop round it (AM2904 with an extra
>>>> flipflop).  With quite a lot of calibration, that got me a 13-bit, 2-pi,
>>>> 50 ks/s phase measurement that I was pretty happy with.  (The extra bit
>>>> came from deciding which null to head for, which is why I needed the
>>>> extra FF.)  It was all interfaced to an HP 9816 computer via a GPIO
>>>> card, and (eventually) worked great.  I published one of my only two
>>>> instruments papers on it (this was before I realized the total futility
>>>> of almost all instruments papers).
>>>>
>>>> The advantage of nulling detection is that you only need 1-D calibration
>>>> tables for phase shift and amplitude, whereas getting that sort of
>>>> accuracy with I/Q techniques requires a 2-D calibration table, which is
>>>> a gigantic pain.
>>>>
>>>> I need to do this again, 2015 style.  The speed requirements are set by
>>>> the acoustic delay in the AO scanner, so 50-100 ks/s is about all I can
>>>> use.  Rather than all that squishy analogue stuff, I'm planning to do
>>>> the SAR in software and use a pair of AD9951 DDS chips, one to generate
>>>> the desired signal and one to be the phase shifted comparison signal.
>>>>
>>>> So far so straightforward.
>>>>
>>>> What I'm less sure about is being able to keep the two channels
>>>> sufficiently isolated to be able to maintain 12 or ideally 14 bits of
>>>> phase accuracy.  Even with a full-scale input, I'll need 85 dB of
>>>> isolation to get 14 bits, and it gets harder with weaker signals.
>>>> (There'll be a DLVA/limiter ahead of the phase detector, which will help.)
>>>>
>>>> I've never used DDSes before, and I'd appreciate some wisdom from folks
>>>> who have.  How hard is that likely to be, and what should I particularly
>>>> watch out for?
>>>
>>> DDSs have a forest of rational-multiple (but not necessarily harmonic)
>>> spurs, and it can be difficult to get them below -60 dBc unless you can
>>> place some restrictions on the frequency resolution.
>>
>> I can pick my IF to be anything I like, which I expect will help.
>>>
>>> Also beware phase jumps when the DDS phase wheel rolls over.
>>
>> Could you elaborate a bit?  I thought the whole idea was to keep phase
>> continuity.
>
> Lots of people have elaborated on the point, so I won't recite it.

Actually, *no one* has elaborated on a "phase jump" on the "wheel 
rolling" over.  I have no idea what is being described with this and I 
think no one else does either.  From the references given this is a 
misunderstanding from the discussion of the spurs and how they relate to 
the phase step size and the modulus of the counter.


> It's true that choosing tuning words with the lower k (one chooses a
> suitable value such that nothing is truncated in lookup tables) bits
> zero will greatly reduce the number of spurs, and get rid of the phase
> bump when the phase wheel rolls over, but there will still be lots of
> spurs from the limited width of the lookup tables and DACs.

What?  First you say to choose a step size (I assume that's what 'k' is) 
so the lower bits are zero precluding truncation in the lookup table 
then you say the lookup tables will still give spurs.  Do you mean the 
fact that while the phase is now exact (although the frequency choices 
are very limited) the resolution of the DAC still creates spurs?  Yes, 
that is pretty obvious actually.  The lookup table doesn't need to be a 
problem as nearly any width DAC can be matched by the lookup table.  But 
even if a DAC had huge resolution, there will always be distortion in 
any analog component giving rise to harmonics and spurs.


> So, the question is if your application is bothered by a bunch of
> spurs, some near in, at about -60 dBc.  This is the key analysis to
> perform.  If the answer is no problem, then life is simple.  If it is a
> problem, there is a longer discussion in store.

What are your assumptions for this number?  The paper you reference 
below shows examples with spurs below -90 dBc for a 15 bit phase input 
to the lookup table.  The spurs for the amplitude truncation at the 
output of the table depend on the value chosen for that word width.


> ADI has a very good tutorial on DDS theory, "MT-085: Fundamentals of
> Direct Digital Synthesis (DDS)".  I'd read it.

I've read this and nowhere does it mention "phase jumps".  I've asked 
more than once for someone to explain what they mean by this and no one 
has stepped forward.  I have to assume it is a term showing a 
misunderstanding of what is going on.

-- 

Rick

On Saturday, 6 December 2014 00:08:38 UTC+11, Lasse Langwadt Christensen  w=
rote:
> Den fredag den 5. december 2014 13.54.58 UTC+1 skrev Bill Sloman:
> > On Friday, 5 December 2014 14:27:37 UTC+11, Phil Hobbs  wrote:
> > > On 12/4/2014 7:10 PM, rickman wrote:
> > > > On 12/4/2014 3:04 PM, Phil Hobbs wrote:
> > > >> Hi, all,
> > > >>
> > > >> I have a gig coming in that will have me revisiting my thesis rese=
arch
> > > >> from nearly 30 years ago, on interferometric laser microscopes.  (=
Fun.)
> > > >>
> > > >> Back in the day, I made a nulling-type phase digitizer at 60 MHz b=
y
> > > >> driving a phase shifter with a 12-bit DAC (AD-DAC80), and wrapping=
 a
> > > >> 13-bit successive approximation loop round it (AM2904 with an extr=
a
> > > >> flipflop).  With quite a lot of calibration, that got me a 13-bit,=
 2-pi,
> > > >> 50 ks/s phase measurement that I was pretty happy with.  (The extr=
a bit
> > > >> came from deciding which null to head for, which is why I needed t=
he
> > > >> extra FF.)  It was all interfaced to an HP 9816 computer via a GPI=
O
> > > >> card, and (eventually) worked great.  I published one of my only t=
wo
> > > >> instruments papers on it (this was before I realized the total fut=
ility
> > > >> of almost all instruments papers).
> > > >>
> > > >> The advantage of nulling detection is that you only need 1-D calib=
ration
> > > >> tables for phase shift and amplitude, whereas getting that sort of
> > > >> accuracy with I/Q techniques requires a 2-D calibration table, whi=
ch is
> > > >> a gigantic pain.
> > > >>
> > > >> I need to do this again, 2015 style.  The speed requirements are s=
et by
> > > >> the acoustic delay in the AO scanner, so 50-100 ks/s is about all =
I can
> > > >> use.  Rather than all that squishy analogue stuff, I'm planning to=
 do
> > > >> the SAR in software and use a pair of AD9951 DDS chips, one to gen=
erate
> > > >> the desired signal and one to be the phase shifted comparison sign=
al.
> > > >>
> > > >> So far so straightforward.
> > > >>
> > > >> What I'm less sure about is being able to keep the two channels
> > > >> sufficiently isolated to be able to maintain 12 or ideally 14 bits=
 of
> > > >> phase accuracy.  Even with a full-scale input, I'll need 85 dB of
> > > >> isolation to get 14 bits, and it gets harder with weaker signals.
> > > >> (There'll be a DLVA/limiter ahead of the phase detector, which wil=
l
> > > >> help.)
> > > >>
> > > >> I've never used DDSes before, and I'd appreciate some wisdom from =
folks
> > > >> who have.  How hard is that likely to be, and what should I partic=
ularly
> > > >> watch out for?
> > > >
> > > > I've read all the posts so far and it seems you are generating a VH=
F
> > > > sine wave to compare to a VHF signal you wish to measure the phase =
and
> > > > amplitude of.  I think I get that.  But it seems the modulation of =
the
> > > > VHF signal is pretty low rate so that 50 kSPS is good enough.
> > > >
> > > > Then you ask about how to maintain enough isolation to preserve 14 =
bits
> > > > of phase measurement.  I think the isolation you are worried about =
it in
> > > > the VHF range, no?  That is the domain of RF design and not at all
> > > > trivial.  I think you will need to provide more info on design spec=
ifics.
> > > >
> > > > I'm not clear on how you plan to do the phase detector.  Is this ju=
st
> > > > subtracting the reference signal from the signal being measured?  Y=
ou
> > > > then scan the phase of the reference to find the null, scan the
> > > > amplitude of the reference to optimize the null and then possibly
> > > > repeat?  Otherwise I'm not sure how you get both phase and amplitud=
e out
> > > > of this.
> > > >
> > > The phase detector will probably be a diode bridge type, e.g. a Mini=
=20
> > > Circuits MPD-1.  It's approximately a multiplier.
> >=20
> > Why not use a real multiplier? Analog Devices have a couple of pretty g=
ood analog multiplier chips. AD734 and AD834 come to mind.
> >=20
> > And if you are working at a fixed frequency, running the DDS staircase =
approximation to a sine wave through an integrator (with the right gain) tu=
rns it into a straight-line interpolation approximation to a sine wave, whi=
ch is a lot nicer, (and slightly easier to filter).
>=20
> an integrator is just a bad filter, why should a bad filter in front of a=
 good filter suddenly make things better?=20

An integrator converts the sawtooth error signal implicit in a staircase ap=
proximation to a sine wave to a series of much smaller of continuous arcs.

You've still got a high frequency error signal to filter out, but pretty mu=
ch all of the higher frequency content (at multiples of DDS update rate) ha=
s gone away.

The integrator isn't functioning as a bad filter here - it's a device to im=
prove the quality of the approximation to the desired sine wave.

--=20
Bill Sloman, Sydney

On Saturday, 6 December 2014 05:42:06 UTC+11, Phil Hobbs  wrote:
> On 12/5/2014 12:43 PM, John Larkin wrote:
> > On Fri, 05 Dec 2014 10:32:04 -0500, Phil Hobbs
> > <pcdhSpamMeSenseless@electrooptical.net> wrote:
> >
> >> On 12/5/2014 7:54 AM, Bill Sloman wrote:
> >>> On Friday, 5 December 2014 14:27:37 UTC+11, Phil Hobbs  wrote:
> >>>> On 12/4/2014 7:10 PM, rickman wrote:
> >>>>> On 12/4/2014 3:04 PM, Phil Hobbs wrote:
> >>>>>> Hi, all,
> >>>>>>
> >>>>>> I have a gig coming in that will have me revisiting my thesis
> >>>>>> research from nearly 30 years ago, on interferometric laser
> >>>>>> microscopes.  (Fun.)
> >>>>>>
> >>>>>> Back in the day, I made a nulling-type phase digitizer at 60
> >>>>>> MHz by driving a phase shifter with a 12-bit DAC (AD-DAC80),
> >>>>>> and wrapping a 13-bit successive approximation loop round it
> >>>>>> (AM2904 with an extra flipflop).  With quite a lot of
> >>>>>> calibration, that got me a 13-bit, 2-pi, 50 ks/s phase
> >>>>>> measurement that I was pretty happy with.  (The extra bit came
> >>>>>> from deciding which null to head for, which is why I needed
> >>>>>> the extra FF.)  It was all interfaced to an HP 9816 computer
> >>>>>> via a GPIO card, and (eventually) worked great.  I published
> >>>>>> one of my only two instruments papers on it (this was before I
> >>>>>> realized the total futility of almost all instruments papers).
> >>>>>>
> >>>>>> The advantage of nulling detection is that you only need 1-D
> >>>>>> calibration tables for phase shift and amplitude, whereas
> >>>>>> getting that sort of accuracy with I/Q techniques requires a
> >>>>>> 2-D calibration table, which is a gigantic pain.
> >>>>>>
> >>>>>> I need to do this again, 2015 style.  The speed requirements
> >>>>>> are set by the acoustic delay in the AO scanner, so 50-100 ks/s
> >>>>>> is about all I can use.  Rather than all that squishy analogue
> >>>>>> stuff, I'm planning to do the SAR in software and use a pair of
> >>>>>> AD9951 DDS chips, one to generate the desired signal and one to
> >>>>>> be the phase shifted comparison signal.
> >>>>>>
> >>>>>> So far so straightforward.
> >>>>>>
> >>>>>> What I'm less sure about is being able to keep the two
> >>>>>> channels sufficiently isolated to be able to maintain 12 or
> >>>>>> ideally 14 bits of phase accuracy.  Even with a full-scale
> >>>>>> input, I'll need 85 dB of isolation to get 14 bits, and it gets
> >>>>>> harder with weaker signals. (There'll be a DLVA/limiter ahead
> >>>>>> of the phase detector, which will help.)
> >>>>>>
> >>>>>> I've never used DDSes before, and I'd appreciate some wisdom
> >>>>>> from folks who have.  How hard is that likely to be, and what
> >>>>>> should I particularly watch out for?
> >>>>>
> >>>>> I've read all the posts so far and it seems you are generating a
> >>>>> VHF sine wave to compare to a VHF signal you wish to measure the
> >>>>> phase and amplitude of.  I think I get that.  But it seems the
> >>>>> modulation of the VHF signal is pretty low rate so that 50 kSPS
> >>>>> is good enough.
> >>>>>
> >>>>> Then you ask about how to maintain enough isolation to preserve
> >>>>> 14 bits of phase measurement.  I think the isolation you are
> >>>>> worried about it in the VHF range, no?  That is the domain of RF
> >>>>> design and not at all trivial.  I think you will need to provide
> >>>>> more info on design specifics.
> >>>>>
> >>>>> I'm not clear on how you plan to do the phase detector.  Is this
> >>>>> just subtracting the reference signal from the signal being
> >>>>> measured?  You then scan the phase of the reference to find the
> >>>>> null, scan the amplitude of the reference to optimize the null
> >>>>> and then possibly repeat?  Otherwise I'm not sure how you get
> >>>>> both phase and amplitude out of this.
> >>>>>
> >>>> The phase detector will probably be a diode bridge type, e.g. a
> >>>> Mini Circuits MPD-1.  It's approximately a multiplier.
> >>>
> >>> Why not use a real multiplier? Analog Devices have a couple of pretty
> >>> good analog multiplier chips. AD734 and AD834 come to mind.
> >>
> >> The beauty of the nulling technique is that you don't depend on the
> >> accuracy of the phase detector characteristic--it just has to have
> >> stable nulls, which the MPD-1 has. I'll always be winding up at almost
> >> exactly the same relative phase, i.e. at the null.
> >>
> >>>
> >>> And if you are working at a fixed frequency, running the DDS
> >>> staircase approximation to a sine wave through an integrator (with
> >>> the right gain) turns it into a straight-line interpolation
> >>> approximation to a sine wave, which is a lot nicer, (and slightly
> >>> easier to filter).
> >>
> >> I've been reading the references everybody's been citing, and they're
> >> pretty illuminating.
> >>
> >> Re: subharmonics due to residual phase accumulator values
> >>
> >> Since I can pick the LO any way I like, I'll just use an integer
> >> multiple of f_clock / 2**14, which ought to get rid of the subharmonic
> >> problem, since the value in the phase accumulator will be the same at
> >> the beginning of each cycle, to the bit width of the lookup table.  Wi=
th
> >> a 400-MHz DDS, those are only 24 kHz apart, so there will be no proble=
m
> >> finding one inside whatever filter passband I wind up with.
> >
> > Right. That amounts to a counter/lookup-table/DAC. Seweet spots in the
> > DDS frequency list. No squirmies.
> >
> >
> >>
> >> I've often used 10.7 MHz ceramic IF filters (as Rick Karlquist suggest=
s
> >> in that excellent paper referenced upthread), so I might do that again=
,
> >> although I'll need a wider one after the variable phase oscillator,
> >> because a 14-bit conversion at 100 kHz would leave me only about 7
> >> cycles per bit.
> >>
> >> I'd probably need to resynchronize the comparator output anyway, to ma=
ke
> >> sure I'm always sampling at the null of the residual phase detector
> >> ripple.
> >>
> >> Or maybe I should just use one of JL's ECLiPS Lite D-flops for the pha=
se
> >> detector instead.  With a 1-ps decision time, that would be good for
> >>
> >> N =3D -log_2(10.7 MHz * 1 ps) =3D 16.5 bits
> >
> > Even better with averaging!
> >
> > You can make a sampling oscilloscope, too, with a minor variant of the
> > bang-bang phase detector, using very few parts.
>=20
> Averaging would be pretty simple--use its output to gate the 10.7 MHz=20
> into a counter input of the MCU. With 7 cycles per bit, I'd=20
> theoretically get 19 bits.  Awesome.
>=20
> Which leads to the next question, namely layout and clock distribution.
>=20
> In my original setup, I built a calibrator that was much more=20
> complicated than the digitizer itself.  It had two separate 60 MHz=20
> synthesizers, running at a reference frequency of 600 kHz=20
> (divide-by-100).  One of them used a 10/11 dual modulus prescaler, so=20
> that I could swallow individual pulses and so make the phase walk around=
=20
> by 3.6-degree steps.  Before using the microscope, I ran the phase=20
> shifter calibration and did a normal cubic spline fit to the results,=20
> which worked fine as long as everything was well warmed up.
>=20
> That strategy lives and dies by the isolation between channels.  I used=
=20
> a bunch of isolation amps, based on MRF966 dual-gate GaAs FETs, which=20
> were good enough for 70-dB isolation at 100 MHz in one stage--and the=20
> whole thing was a dead-bug proto.  It used a lot of bolted-together=20
> aluminum boxes and double-shielded coax, and was about 18 inches square.=
=20
>   But the isolation was very good--when I leaned on the "pulse swallow"=
=20
> button, which moved one synthesizer off by 600 kHz, I could see on the=20
> spectrum analyzer that the leakage was at the -90 dBc level.
>=20
> This one is going to be on the same board, talking to the same=20
> processor, and so on.  I'm planning to run the two synths on their own=20
> power supplies, with buffers on the digital lines that are also run from=
=20
> those supplies, and run all their traces on interior levels between two=
=20
> ground pours with via stitching.
>=20
> It's really the clock distribution and especially the local grounding=20
> and decoupling at the DDSes that I'm worried about.  You're generally a=
=20
> fan of just connecting all the flavours of ground to a single=20
> featureless plane, with an equally featureless supply plane next to it.=
=20
>   Is that the right answer here as well, or do I risk extra spurs that wa=
y?

One strategy that can help - and is easy to implement with ECL, which tends=
 off balanced outputs - is to make all your signal chains balanced, so you =
generate both the in-phase and the 180 degree out of phase version of every=
 clock, and ship them around to balanced lie receivers.

This means much less higher-frequecy return current circulating through you=
r plane, and, you get the common mode rejection of your line receivers to g=
et rid of any residual potential differences across your ground plane.

For stubborn problems you can invoke 1:1 transmission line transformers - t=
he side to side capacitance is always nasty (tens of picofarads) but they c=
an offer useful extra attentuation.

Watch out for gate-input interaction in gated - AM685 -style comparators

http://www.analog.com/static/imported-files/data_sheets/AD96685_96687.pdf

The SPAD guy in Milan used them, but found it necessary to gate them on som=
e 10nsec early, and delay closing the gate for 10nsec after the - possible =
- event.

There wasn't much interaction between the long-tailed pair detecting the si=
gnal of interest and the gating signal, but there was enough to worry about=
.

--=20
Bill Sloman, Sydney

On Saturday, 6 December 2014 08:06:30 UTC+11, John Larkin  wrote:
> On Fri, 05 Dec 2014 06:26:40 GMT, Tom Swift <spam@me.com> wrote:
> 
> >Phil Hobbs <hobbs@electrooptical.net> wrote:
> >
> >> On 12/4/2014 7:44 PM, Joe Gwinn wrote:
> >
> >>> Also beware phase jumps when the DDS phase wheel rolls over.
> > 
> >> Could you elaborate a bit?  I thought the whole idea was to keep phase
> >> continuity.
> > 
> >> Thanks
> > 
> >> Phil Hobbs
> >
> >Joe is right. Most DDS are 32 bits. As I understand it, when you program 
> >in a frequency, there are some bits left over. When the counter rolls 
> >over, these do not align with the starting phase. Depending on the clock 
> >and output frequencies, there will be a phase bump every several seconds 
> >or so.
> 
> A binary-radix DDS, the only kind you can buy,

Wrong. Tom Swift mentions "variable modulus DDS chips like the AD9913, AD9914 and AD9915" so he seems to share my opinion that Analog Devices does offer non-binary radix DDS chips.

If the binary-radix DDS chips are the only parts you can buy, you need a better buyer.

<snip>

-- 
Bill Sloman, Sydney

On 12/5/2014 7:44 PM, Joe Gwinn wrote:
> In article <5481273A.6010107@electrooptical.net>, Phil Hobbs
> <hobbs@electrooptical.net> wrote:
>
>> On 12/4/2014 7:44 PM, Joe Gwinn wrote:
>>> In article <cYydnTNwFPGvIx3JnZ2dnUU7-W-dnZ2d@supernews.com>, Phil Hobbs
>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>
>>>> Hi, all,
>>>>
>>>> I have a gig coming in that will have me revisiting my thesis research
>>>> from nearly 30 years ago, on interferometric laser microscopes.  (Fun.)
>>>>
>>>> Back in the day, I made a nulling-type phase digitizer at 60 MHz by
>>>> driving a phase shifter with a 12-bit DAC (AD-DAC80), and wrapping a
>>>> 13-bit successive approximation loop round it (AM2904 with an extra
>>>> flipflop).  With quite a lot of calibration, that got me a 13-bit, 2-pi,
>>>> 50 ks/s phase measurement that I was pretty happy with.  (The extra bit
>>>> came from deciding which null to head for, which is why I needed the
>>>> extra FF.)  It was all interfaced to an HP 9816 computer via a GPIO
>>>> card, and (eventually) worked great.  I published one of my only two
>>>> instruments papers on it (this was before I realized the total futility
>>>> of almost all instruments papers).
>>>>
>>>> The advantage of nulling detection is that you only need 1-D calibration
>>>> tables for phase shift and amplitude, whereas getting that sort of
>>>> accuracy with I/Q techniques requires a 2-D calibration table, which is
>>>> a gigantic pain.
>>>>
>>>> I need to do this again, 2015 style.  The speed requirements are set by
>>>> the acoustic delay in the AO scanner, so 50-100 ks/s is about all I can
>>>> use.  Rather than all that squishy analogue stuff, I'm planning to do
>>>> the SAR in software and use a pair of AD9951 DDS chips, one to generate
>>>> the desired signal and one to be the phase shifted comparison signal.
>>>>
>>>> So far so straightforward.
>>>>
>>>> What I'm less sure about is being able to keep the two channels
>>>> sufficiently isolated to be able to maintain 12 or ideally 14 bits of
>>>> phase accuracy.  Even with a full-scale input, I'll need 85 dB of
>>>> isolation to get 14 bits, and it gets harder with weaker signals.
>>>> (There'll be a DLVA/limiter ahead of the phase detector, which will help.)
>>>>
>>>> I've never used DDSes before, and I'd appreciate some wisdom from folks
>>>> who have.  How hard is that likely to be, and what should I particularly
>>>> watch out for?
>>>
>>> DDSs have a forest of rational-multiple (but not necessarily harmonic)
>>> spurs, and it can be difficult to get them below -60 dBc unless you can
>>> place some restrictions on the frequency resolution.
>>
>> I can pick my IF to be anything I like, which I expect will help.
>>>
>>> Also beware phase jumps when the DDS phase wheel rolls over.
>>
>> Could you elaborate a bit?  I thought the whole idea was to keep phase
>> continuity.
>
> Lots of people have elaborated on the point, so I won't recite it.
>
> It's true that choosing tuning words with the lower k (one chooses a
> suitable value such that nothing is truncated in lookup tables) bits
> zero will greatly reduce the number of spurs, and get rid of the phase
> bump when the phase wheel rolls over, but there will still be lots of
> spurs from the limited width of the lookup tables and DACs.

If the 'hidden' bits in the phase register are always zero, then the 
output of the DAC should be strictly periodic at f_out.  That means that 
all, and I mean *all*, of the artifacts will be harmonics of f_out. 
Isn't that so?


> So, the question is if your application is bothered by a bunch of
> spurs, some near in, at about -60 dBc.  This is the key analysis to
> perform.  If the answer is no problem, then life is simple.  If it is a
> problem, there is a longer discussion in store.

-60 dBc is pretty crappy.

>
> ADI has a very good tutorial on DDS theory, "MT-085: Fundamentals of
> Direct Digital Synthesis (DDS)".  I'd read it.

Thanks.  I did read it, but it didn't say what you said.

Cheers

Phil Hobbs

-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

On 12/5/2014 7:12 PM, George Herold wrote:
> On Thursday, December 4, 2014 3:04:06 PM UTC-5, Phil Hobbs wrote:
>> Hi, all,
>>
>> I have a gig coming in that will have me revisiting my thesis research
>> from nearly 30 years ago, on interferometric laser microscopes.  (Fun.)
>>
>> Back in the day, I made a nulling-type phase digitizer at 60 MHz by
>> driving a phase shifter with a 12-bit DAC (AD-DAC80), and wrapping a
>> 13-bit successive approximation loop round it (AM2904 with an extra
>> flipflop).  With quite a lot of calibration, that got me a 13-bit, 2-pi,
>> 50 ks/s phase measurement that I was pretty happy with.  (The extra bit
>> came from deciding which null to head for, which is why I needed the
>> extra FF.)  It was all interfaced to an HP 9816 computer via a GPIO
>> card, and (eventually) worked great.  I published one of my only two
>> instruments papers on it (this was before I realized the total futility
>> of almost all instruments papers).
>
> Hi Phil, I've been sorta half following this thread,
> and I wonder if you could tell me what a nulling type phase digitizer is?
> (I "turn" the phase knob of a lockin type mixer/detector till the signal goes to zero?)
> Maybe just a reference to your instrument paper...?
>
> George H.


Hi, George,

The idea is to use a phase detector wrapped in a successive 
approximation loop.  Like other SAR ADCs, you run the register to null 
out the error signal to N bits' accuracy, and read off the value from 
the DAC control word corresponding to the null.  In this case, the 'DAC' 
is a phase shifter.

I looked around for a copy of the instruments paper, but couldn't find 
it--it predates my earliest digital archives, having been published in 
1987.  It's at http://dx.doi.org/10.1063/1.1139391 .

Cheers

Phil Hobbs



-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

On 12/5/2014 9:29 PM, Phil Hobbs wrote:
> On 12/5/2014 7:44 PM, Joe Gwinn wrote:
>> In article <5481273A.6010107@electrooptical.net>, Phil Hobbs
>> <hobbs@electrooptical.net> wrote:
>>
>>> On 12/4/2014 7:44 PM, Joe Gwinn wrote:
>>>> In article <cYydnTNwFPGvIx3JnZ2dnUU7-W-dnZ2d@supernews.com>, Phil Hobbs
>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>>
>>>>> Hi, all,
>>>>>
>>>>> I have a gig coming in that will have me revisiting my thesis research
>>>>> from nearly 30 years ago, on interferometric laser microscopes.
>>>>> (Fun.)
>>>>>
>>>>> Back in the day, I made a nulling-type phase digitizer at 60 MHz by
>>>>> driving a phase shifter with a 12-bit DAC (AD-DAC80), and wrapping a
>>>>> 13-bit successive approximation loop round it (AM2904 with an extra
>>>>> flipflop).  With quite a lot of calibration, that got me a 13-bit,
>>>>> 2-pi,
>>>>> 50 ks/s phase measurement that I was pretty happy with.  (The extra
>>>>> bit
>>>>> came from deciding which null to head for, which is why I needed the
>>>>> extra FF.)  It was all interfaced to an HP 9816 computer via a GPIO
>>>>> card, and (eventually) worked great.  I published one of my only two
>>>>> instruments papers on it (this was before I realized the total
>>>>> futility
>>>>> of almost all instruments papers).
>>>>>
>>>>> The advantage of nulling detection is that you only need 1-D
>>>>> calibration
>>>>> tables for phase shift and amplitude, whereas getting that sort of
>>>>> accuracy with I/Q techniques requires a 2-D calibration table,
>>>>> which is
>>>>> a gigantic pain.
>>>>>
>>>>> I need to do this again, 2015 style.  The speed requirements are
>>>>> set by
>>>>> the acoustic delay in the AO scanner, so 50-100 ks/s is about all I
>>>>> can
>>>>> use.  Rather than all that squishy analogue stuff, I'm planning to do
>>>>> the SAR in software and use a pair of AD9951 DDS chips, one to
>>>>> generate
>>>>> the desired signal and one to be the phase shifted comparison signal.
>>>>>
>>>>> So far so straightforward.
>>>>>
>>>>> What I'm less sure about is being able to keep the two channels
>>>>> sufficiently isolated to be able to maintain 12 or ideally 14 bits of
>>>>> phase accuracy.  Even with a full-scale input, I'll need 85 dB of
>>>>> isolation to get 14 bits, and it gets harder with weaker signals.
>>>>> (There'll be a DLVA/limiter ahead of the phase detector, which will
>>>>> help.)
>>>>>
>>>>> I've never used DDSes before, and I'd appreciate some wisdom from
>>>>> folks
>>>>> who have.  How hard is that likely to be, and what should I
>>>>> particularly
>>>>> watch out for?
>>>>
>>>> DDSs have a forest of rational-multiple (but not necessarily harmonic)
>>>> spurs, and it can be difficult to get them below -60 dBc unless you can
>>>> place some restrictions on the frequency resolution.
>>>
>>> I can pick my IF to be anything I like, which I expect will help.
>>>>
>>>> Also beware phase jumps when the DDS phase wheel rolls over.
>>>
>>> Could you elaborate a bit?  I thought the whole idea was to keep phase
>>> continuity.
>>
>> Lots of people have elaborated on the point, so I won't recite it.
>>
>> It's true that choosing tuning words with the lower k (one chooses a
>> suitable value such that nothing is truncated in lookup tables) bits
>> zero will greatly reduce the number of spurs, and get rid of the phase
>> bump when the phase wheel rolls over, but there will still be lots of
>> spurs from the limited width of the lookup tables and DACs.
>
> If the 'hidden' bits in the phase register are always zero, then the
> output of the DAC should be strictly periodic at f_out.  That means that
> all, and I mean *all*, of the artifacts will be harmonics of f_out.
> Isn't that so?

I'm not sure that follows.  There are still spurs related to the clock 
rate which may not be a harmonic of F_out.


>> So, the question is if your application is bothered by a bunch of
>> spurs, some near in, at about -60 dBc.  This is the key analysis to
>> perform.  If the answer is no problem, then life is simple.  If it is a
>> problem, there is a longer discussion in store.
>
> -60 dBc is pretty crappy.
>
>>
>> ADI has a very good tutorial on DDS theory, "MT-085: Fundamentals of
>> Direct Digital Synthesis (DDS)".  I'd read it.
>
> Thanks.  I did read it, but it didn't say what you said.
>
> Cheers
>
> Phil Hobbs
>


-- 

Rick

On 12/5/2014 9:37 PM, Phil Hobbs wrote:
> On 12/5/2014 7:12 PM, George Herold wrote:
>> On Thursday, December 4, 2014 3:04:06 PM UTC-5, Phil Hobbs wrote:
>>> Hi, all,
>>>
>>> I have a gig coming in that will have me revisiting my thesis research
>>> from nearly 30 years ago, on interferometric laser microscopes.  (Fun.)
>>>
>>> Back in the day, I made a nulling-type phase digitizer at 60 MHz by
>>> driving a phase shifter with a 12-bit DAC (AD-DAC80), and wrapping a
>>> 13-bit successive approximation loop round it (AM2904 with an extra
>>> flipflop).  With quite a lot of calibration, that got me a 13-bit, 2-pi,
>>> 50 ks/s phase measurement that I was pretty happy with.  (The extra bit
>>> came from deciding which null to head for, which is why I needed the
>>> extra FF.)  It was all interfaced to an HP 9816 computer via a GPIO
>>> card, and (eventually) worked great.  I published one of my only two
>>> instruments papers on it (this was before I realized the total futility
>>> of almost all instruments papers).
>>
>> Hi Phil, I've been sorta half following this thread,
>> and I wonder if you could tell me what a nulling type phase digitizer is?
>> (I "turn" the phase knob of a lockin type mixer/detector till the
>> signal goes to zero?)
>> Maybe just a reference to your instrument paper...?
>>
>> George H.
>
>
> Hi, George,
>
> The idea is to use a phase detector wrapped in a successive
> approximation loop.  Like other SAR ADCs, you run the register to null
> out the error signal to N bits' accuracy, and read off the value from
> the DAC control word corresponding to the null.  In this case, the 'DAC'
> is a phase shifter.

How do you get the amplitude?  Don't you need to work the two together? 
  Or I guess you can get the phase from the DAC setting at null and then 
calculate the amplitude from the depth of the null?

-- 

Rick

On 12/5/2014 10:06 PM, rickman wrote:
> On 12/5/2014 9:29 PM, Phil Hobbs wrote:
>> On 12/5/2014 7:44 PM, Joe Gwinn wrote:
>>> In article <5481273A.6010107@electrooptical.net>, Phil Hobbs
>>> <hobbs@electrooptical.net> wrote:
>>>
>>>> On 12/4/2014 7:44 PM, Joe Gwinn wrote:
>>>>> In article <cYydnTNwFPGvIx3JnZ2dnUU7-W-dnZ2d@supernews.com>, Phil
>>>>> Hobbs
>>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>>>
>>>>>> Hi, all,
>>>>>>
>>>>>> I have a gig coming in that will have me revisiting my thesis
>>>>>> research
>>>>>> from nearly 30 years ago, on interferometric laser microscopes.
>>>>>> (Fun.)
>>>>>>
>>>>>> Back in the day, I made a nulling-type phase digitizer at 60 MHz by
>>>>>> driving a phase shifter with a 12-bit DAC (AD-DAC80), and wrapping a
>>>>>> 13-bit successive approximation loop round it (AM2904 with an extra
>>>>>> flipflop).  With quite a lot of calibration, that got me a 13-bit,
>>>>>> 2-pi,
>>>>>> 50 ks/s phase measurement that I was pretty happy with.  (The extra
>>>>>> bit
>>>>>> came from deciding which null to head for, which is why I needed the
>>>>>> extra FF.)  It was all interfaced to an HP 9816 computer via a GPIO
>>>>>> card, and (eventually) worked great.  I published one of my only two
>>>>>> instruments papers on it (this was before I realized the total
>>>>>> futility
>>>>>> of almost all instruments papers).
>>>>>>
>>>>>> The advantage of nulling detection is that you only need 1-D
>>>>>> calibration
>>>>>> tables for phase shift and amplitude, whereas getting that sort of
>>>>>> accuracy with I/Q techniques requires a 2-D calibration table,
>>>>>> which is
>>>>>> a gigantic pain.
>>>>>>
>>>>>> I need to do this again, 2015 style.  The speed requirements are
>>>>>> set by
>>>>>> the acoustic delay in the AO scanner, so 50-100 ks/s is about all I
>>>>>> can
>>>>>> use.  Rather than all that squishy analogue stuff, I'm planning to do
>>>>>> the SAR in software and use a pair of AD9951 DDS chips, one to
>>>>>> generate
>>>>>> the desired signal and one to be the phase shifted comparison signal.
>>>>>>
>>>>>> So far so straightforward.
>>>>>>
>>>>>> What I'm less sure about is being able to keep the two channels
>>>>>> sufficiently isolated to be able to maintain 12 or ideally 14 bits of
>>>>>> phase accuracy.  Even with a full-scale input, I'll need 85 dB of
>>>>>> isolation to get 14 bits, and it gets harder with weaker signals.
>>>>>> (There'll be a DLVA/limiter ahead of the phase detector, which will
>>>>>> help.)
>>>>>>
>>>>>> I've never used DDSes before, and I'd appreciate some wisdom from
>>>>>> folks
>>>>>> who have.  How hard is that likely to be, and what should I
>>>>>> particularly
>>>>>> watch out for?
>>>>>
>>>>> DDSs have a forest of rational-multiple (but not necessarily harmonic)
>>>>> spurs, and it can be difficult to get them below -60 dBc unless you
>>>>> can
>>>>> place some restrictions on the frequency resolution.
>>>>
>>>> I can pick my IF to be anything I like, which I expect will help.
>>>>>
>>>>> Also beware phase jumps when the DDS phase wheel rolls over.
>>>>
>>>> Could you elaborate a bit?  I thought the whole idea was to keep phase
>>>> continuity.
>>>
>>> Lots of people have elaborated on the point, so I won't recite it.
>>>
>>> It's true that choosing tuning words with the lower k (one chooses a
>>> suitable value such that nothing is truncated in lookup tables) bits
>>> zero will greatly reduce the number of spurs, and get rid of the phase
>>> bump when the phase wheel rolls over, but there will still be lots of
>>> spurs from the limited width of the lookup tables and DACs.
>>
>> If the 'hidden' bits in the phase register are always zero, then the
>> output of the DAC should be strictly periodic at f_out.  That means that
>> all, and I mean *all*, of the artifacts will be harmonics of f_out.
>> Isn't that so?
>
> I'm not sure that follows.  There are still spurs related to the clock
> rate which may not be a harmonic of F_out.
>
Okay, maybe slightly overstated--the system is never exactly perfect. 
However, all the aliased higher-order products that show up as close-in 
spurs--the ones related to the hidden bits in the phase accumulator not 
being the same from cycle to cycle--should be gone.

Cheers

Phil Hobbs


-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

On Fri, 05 Dec 2014 21:29:46 -0500, Phil Hobbs
<hobbs@electrooptical.net> wrote:

>On 12/5/2014 7:44 PM, Joe Gwinn wrote:
>> In article <5481273A.6010107@electrooptical.net>, Phil Hobbs
>> <hobbs@electrooptical.net> wrote:
>>
>>> On 12/4/2014 7:44 PM, Joe Gwinn wrote:
>>>> In article <cYydnTNwFPGvIx3JnZ2dnUU7-W-dnZ2d@supernews.com>, Phil Hobbs
>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>>
>>>>> Hi, all,
>>>>>
>>>>> I have a gig coming in that will have me revisiting my thesis research
>>>>> from nearly 30 years ago, on interferometric laser microscopes.  (Fun.)
>>>>>
>>>>> Back in the day, I made a nulling-type phase digitizer at 60 MHz by
>>>>> driving a phase shifter with a 12-bit DAC (AD-DAC80), and wrapping a
>>>>> 13-bit successive approximation loop round it (AM2904 with an extra
>>>>> flipflop).  With quite a lot of calibration, that got me a 13-bit, 2-pi,
>>>>> 50 ks/s phase measurement that I was pretty happy with.  (The extra bit
>>>>> came from deciding which null to head for, which is why I needed the
>>>>> extra FF.)  It was all interfaced to an HP 9816 computer via a GPIO
>>>>> card, and (eventually) worked great.  I published one of my only two
>>>>> instruments papers on it (this was before I realized the total futility
>>>>> of almost all instruments papers).
>>>>>
>>>>> The advantage of nulling detection is that you only need 1-D calibration
>>>>> tables for phase shift and amplitude, whereas getting that sort of
>>>>> accuracy with I/Q techniques requires a 2-D calibration table, which is
>>>>> a gigantic pain.
>>>>>
>>>>> I need to do this again, 2015 style.  The speed requirements are set by
>>>>> the acoustic delay in the AO scanner, so 50-100 ks/s is about all I can
>>>>> use.  Rather than all that squishy analogue stuff, I'm planning to do
>>>>> the SAR in software and use a pair of AD9951 DDS chips, one to generate
>>>>> the desired signal and one to be the phase shifted comparison signal.
>>>>>
>>>>> So far so straightforward.
>>>>>
>>>>> What I'm less sure about is being able to keep the two channels
>>>>> sufficiently isolated to be able to maintain 12 or ideally 14 bits of
>>>>> phase accuracy.  Even with a full-scale input, I'll need 85 dB of
>>>>> isolation to get 14 bits, and it gets harder with weaker signals.
>>>>> (There'll be a DLVA/limiter ahead of the phase detector, which will help.)
>>>>>
>>>>> I've never used DDSes before, and I'd appreciate some wisdom from folks
>>>>> who have.  How hard is that likely to be, and what should I particularly
>>>>> watch out for?
>>>>
>>>> DDSs have a forest of rational-multiple (but not necessarily harmonic)
>>>> spurs, and it can be difficult to get them below -60 dBc unless you can
>>>> place some restrictions on the frequency resolution.
>>>
>>> I can pick my IF to be anything I like, which I expect will help.
>>>>
>>>> Also beware phase jumps when the DDS phase wheel rolls over.
>>>
>>> Could you elaborate a bit?  I thought the whole idea was to keep phase
>>> continuity.
>>
>> Lots of people have elaborated on the point, so I won't recite it.
>>
>> It's true that choosing tuning words with the lower k (one chooses a
>> suitable value such that nothing is truncated in lookup tables) bits
>> zero will greatly reduce the number of spurs, and get rid of the phase
>> bump when the phase wheel rolls over, but there will still be lots of
>> spurs from the limited width of the lookup tables and DACs.
>
>If the 'hidden' bits in the phase register are always zero, then the 
>output of the DAC should be strictly periodic at f_out.  That means that 
>all, and I mean *all*, of the artifacts will be harmonics of f_out. 
>Isn't that so?

Sure. Absolutely everything repeats at Fout.

>
>
>> So, the question is if your application is bothered by a bunch of
>> spurs, some near in, at about -60 dBc.  This is the key analysis to
>> perform.  If the answer is no problem, then life is simple.  If it is a
>> problem, there is a longer discussion in store.
>
>-60 dBc is pretty crappy.

Not for DDS at non-trivial frequencies! If the DAC doesn't getcha, the
opamps will. But you can bandpass filter.

And I've seen big-name RF signal generators that guarantee -20 dBc
harmonics!


-- 

John Larkin         Highland Technology, Inc
picosecond timing   laser drivers and controllers

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com