You're still fixated on clamping, which would make no sense whatsoever in a mixed signal low power digital environment. The high voltage tolerant inputs are a variation of the theme shown below in one form or another. Operation is self-explanatory:
Please view in a fixed-width font such as Courier.
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. EX High Voltage Tolerant Input
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. VDD
. | PMOS keeper
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. ||o----------.
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. input ___ | | \ | | \ pad
. pad ___ | | \ | | \ to core
. _ D | | S | | \ | | \ _
. |_| ------ ----+-----| o --+---| o----|_|
. | / | /
. series | / | / buffer
. NMOS | / Schmitt | / CMOS
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8051F020 series, 5V tolerant input schematic?
Started by ●June 25, 2013
Reply by ●June 25, 20132013-06-25
Reply by ●June 25, 20132013-06-25
Jim Thompson wrote:> On Tue, 25 Jun 2013 17:31:34 -0700, Joerg <invalid@invalid.invalid> > wrote: > >> Jim Thompson wrote: >>> On Tue, 25 Jun 2013 16:41:40 -0400, Spehro Pefhany >>> <speffSNIP@interlogDOTyou.knowwhat> wrote: >>> >>>> On Tue, 25 Jun 2013 11:02:06 -0700, Joerg <invalid@invalid.invalid> >>>> wrote: >>>> >>>>> Folks, >>>>> >>>>> Got a Silicon Labs 8051Fxxx with 5V-tolerant ports. In the abs max it >>>>> says 5.8V is the limit. Well, if one uses the typical diode against the >>>>> 5V rail it could go slightly above 6V in case of a really big jolt. >>>>> Since this 8051 does not have a 5V supply but just VDD (which hangs on >>>>> 3.3V in this case) there can't be any parasitic substrate diodes dumping >>>>> into a rail. >>>>> >>>>> Does anyone know the innards? Poly resistors? As usual, the datasheet is >>>>> silent about this. >>>> According to Xilinx, 5V tolerant pins can add a dozen or so components >>>> per pin. Probably, as Lasse says, it behaves something like a zener >>>> for inputs. >>>> >>>> If it's programmable as an output too, they have to add some parts to >>>> keep current from flowing back through the off p-channel. >>>> >>>> I don't think you'll find real schematics openly available for this >>>> stuff- on-chip ESD protection seems to be kind of a trade secret. >>> "5V-tolerant" pins function by disconnect, not by clamping (somewhat >>> like the schemes used in hi-Z when unpowered bus devices). The >>> voltage limit is determined by oxide breakdown. >>> >> So you mean like a linear regulator? Because a hard disconnect would >> cause the uC to read this pin wrongly, and it reads it correctly. Or do >> you mean it disconnects somewhere above 5V? > > 5V-tolerant INPUTS have no ESD diode to local VDD, just a "snap" diode > to ground. Thus only the input stage gate oxide has to stand-off the > 5V. > > 5V-tolerant OUTPUTS, that is outputs which also serve as INPUTS > (bi-directional bus I/O, etc.) use a disconnect above local VDD. > Visualize the dual series device with "body" at midpoint, that I've > shown here before as a battery-charge control device. >It's all I/O, since it's a 8051-family uC with regular cofigurable ports.> As in... > > http://www.analog-innovations.com/SED/PerfectDiodeForChargerIsolation.pdf >That would work, provided the comparator is past, has little or no hysteresis and the FETs are snappy. Because the signal integrity of an incoming 5V data stream must be maintained to full spec'd speed.>> If they say 5.8V, what's you gut feel it could really take if a surge or >> pulse salvo of a few msec comes through? It's amplitude would be >> slightly over 7V. because it leans into protective diodes we have up >> front of the uC port. Those are regular Si-diodes against the 5V rail >> and GND. > > DC over-voltage is a no-no... ESD only. >DC will never exceed 5V and abs max is 5.8V. So you think ESD or surges (the usual machine-gun style bursts in EMC tests) are ok? We have it clamped to a 5V rail but it could really lean into those clamp diodes. -- Regards, Joerg http://www.analogconsultants.com/
Reply by ●June 25, 20132013-06-25
On Tue, 25 Jun 2013 17:54:52 -0700, Joerg <invalid@invalid.invalid> wrote:>Jim Thompson wrote: >> On Tue, 25 Jun 2013 17:31:34 -0700, Joerg <invalid@invalid.invalid> >> wrote: >> >>> Jim Thompson wrote: >>>> On Tue, 25 Jun 2013 16:41:40 -0400, Spehro Pefhany >>>> <speffSNIP@interlogDOTyou.knowwhat> wrote: >>>> >>>>> On Tue, 25 Jun 2013 11:02:06 -0700, Joerg <invalid@invalid.invalid> >>>>> wrote: >>>>> >>>>>> Folks, >>>>>> >>>>>> Got a Silicon Labs 8051Fxxx with 5V-tolerant ports. In the abs max it >>>>>> says 5.8V is the limit. Well, if one uses the typical diode against the >>>>>> 5V rail it could go slightly above 6V in case of a really big jolt. >>>>>> Since this 8051 does not have a 5V supply but just VDD (which hangs on >>>>>> 3.3V in this case) there can't be any parasitic substrate diodes dumping >>>>>> into a rail. >>>>>> >>>>>> Does anyone know the innards? Poly resistors? As usual, the datasheet is >>>>>> silent about this. >>>>> According to Xilinx, 5V tolerant pins can add a dozen or so components >>>>> per pin. Probably, as Lasse says, it behaves something like a zener >>>>> for inputs. >>>>> >>>>> If it's programmable as an output too, they have to add some parts to >>>>> keep current from flowing back through the off p-channel. >>>>> >>>>> I don't think you'll find real schematics openly available for this >>>>> stuff- on-chip ESD protection seems to be kind of a trade secret. >>>> "5V-tolerant" pins function by disconnect, not by clamping (somewhat >>>> like the schemes used in hi-Z when unpowered bus devices). The >>>> voltage limit is determined by oxide breakdown. >>>> >>> So you mean like a linear regulator? Because a hard disconnect would >>> cause the uC to read this pin wrongly, and it reads it correctly. Or do >>> you mean it disconnects somewhere above 5V? >> >> 5V-tolerant INPUTS have no ESD diode to local VDD, just a "snap" diode >> to ground. Thus only the input stage gate oxide has to stand-off the >> 5V. >> >> 5V-tolerant OUTPUTS, that is outputs which also serve as INPUTS >> (bi-directional bus I/O, etc.) use a disconnect above local VDD. >> Visualize the dual series device with "body" at midpoint, that I've >> shown here before as a battery-charge control device. >> > >It's all I/O, since it's a 8051-family uC with regular cofigurable ports. > > >> As in... >> >> http://www.analog-innovations.com/SED/PerfectDiodeForChargerIsolation.pdf >> > >That would work, provided the comparator is past, has little or no >hysteresis and the FETs are snappy. Because the signal integrity of an >incoming 5V data stream must be maintained to full spec'd speed. > > >>> If they say 5.8V, what's you gut feel it could really take if a surge or >>> pulse salvo of a few msec comes through? It's amplitude would be >>> slightly over 7V. because it leans into protective diodes we have up >>> front of the uC port. Those are regular Si-diodes against the 5V rail >>> and GND. >> >> DC over-voltage is a no-no... ESD only. >> > >DC will never exceed 5V and abs max is 5.8V. So you think ESD or surges >(the usual machine-gun style bursts in EMC tests) are ok? We have it >clamped to a 5V rail but it could really lean into those clamp diodes.This thread rattles around avoiding specifics. Is the "5V-tolerant" input an input that has 3.3V as VDD? ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●June 25, 20132013-06-25
On Tue, 25 Jun 2013 17:42:32 -0700 (PDT), bloggs.fredbloggs.fred@gmail.com wrote:>You're still fixated on clamping, which would make no sense whatsoever in a mixed signal low power digital environment. The high voltage tolerant inputs are a variation of the theme shown below in one form or another. Operation is self-explanatory: > Please view in a fixed-width font such as Courier. > >. >. >. >. EX High Voltage Tolerant Input >. >. >. >. VDD >. | PMOS keeper >. - >. || >. ||o----------. >. VDD _|| | >. | | | >. | G | | >. input ___ | | \ | | \ pad >. pad ___ | | \ | | \ to core >. _ D | | S | | \ | | \ _ >. |_| ------ ----+-----| o --+---| o----|_| >. | / | / >. series | / | / buffer >. NMOS | / Schmitt | / CMOS >. >.That looks vaguely like my USB patent on the work I did for Intel. I'll dredge that up and post it. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●June 26, 20132013-06-26
[This followup was posted to sci.electronics.design and a copy was sent to the cited author.]>> >>DC will never exceed 5V and abs max is 5.8V. So you think ESD orsurges>>(the usual machine-gun style bursts in EMC tests) are ok? We have it >>clamped to a 5V rail but it could really lean into those clamp diodes. > >This thread rattles around avoiding specifics. Is the "5V-tolerant" >input an input that has 3.3V as VDD?Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the I/O Rail VDD. These pins default to typical 8051 style with quasi- bidirectional behavior with onboard pullup circuitry. The port pins can also be programmed to be output driven by a totem pole output to the VDD rail. -- Michael Karas Carousel Design Solutions http://www.carousel-design.com
Reply by ●June 26, 20132013-06-26
On Tue, 25 Jun 2013 22:21:52 -0700, Michael Karas <mkaras@carousel-design.com> wrote:>[This followup was posted to sci.electronics.design and a copy was sent >to the cited author.] > >>> >>>DC will never exceed 5V and abs max is 5.8V. So you think ESD or >surges >>>(the usual machine-gun style bursts in EMC tests) are ok? We have it >>>clamped to a 5V rail but it could really lean into those clamp diodes. >> >>This thread rattles around avoiding specifics. Is the "5V-tolerant" >>input an input that has 3.3V as VDD? > >Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the >I/O Rail VDD. These pins default to typical 8051 style with quasi- >bidirectional behavior with onboard pullup circuitry. The port pins can >also be programmed to be output driven by a totem pole output to the VDD >rail.I'd (thankfully) almost forgotten about those miserable quasi bi-directional port pins. The schematic on page 161 does not appear to show the brief hard (~100:1) pullup on 0->1 port-pin transition that old-skule 80C51s have. If it's present it would be back of the ESD circuitry anyway. https://www.silabs.com/Support%20Documents/TechnicalDocs/C8051F02x.pdf
Reply by ●June 26, 20132013-06-26
Jim Thompson wrote:> On Tue, 25 Jun 2013 17:54:52 -0700, Joerg <invalid@invalid.invalid> > wrote: > >> Jim Thompson wrote: >>> On Tue, 25 Jun 2013 17:31:34 -0700, Joerg <invalid@invalid.invalid> >>> wrote: >>> >>>> Jim Thompson wrote: >>>>> On Tue, 25 Jun 2013 16:41:40 -0400, Spehro Pefhany >>>>> <speffSNIP@interlogDOTyou.knowwhat> wrote: >>>>> >>>>>> On Tue, 25 Jun 2013 11:02:06 -0700, Joerg <invalid@invalid.invalid> >>>>>> wrote: >>>>>> >>>>>>> Folks, >>>>>>> >>>>>>> Got a Silicon Labs 8051Fxxx with 5V-tolerant ports. In the abs max it >>>>>>> says 5.8V is the limit. Well, if one uses the typical diode against the >>>>>>> 5V rail it could go slightly above 6V in case of a really big jolt. >>>>>>> Since this 8051 does not have a 5V supply but just VDD (which hangs on >>>>>>> 3.3V in this case) there can't be any parasitic substrate diodes dumping >>>>>>> into a rail. >>>>>>> >>>>>>> Does anyone know the innards? Poly resistors? As usual, the datasheet is >>>>>>> silent about this. >>>>>> According to Xilinx, 5V tolerant pins can add a dozen or so components >>>>>> per pin. Probably, as Lasse says, it behaves something like a zener >>>>>> for inputs. >>>>>> >>>>>> If it's programmable as an output too, they have to add some parts to >>>>>> keep current from flowing back through the off p-channel. >>>>>> >>>>>> I don't think you'll find real schematics openly available for this >>>>>> stuff- on-chip ESD protection seems to be kind of a trade secret. >>>>> "5V-tolerant" pins function by disconnect, not by clamping (somewhat >>>>> like the schemes used in hi-Z when unpowered bus devices). The >>>>> voltage limit is determined by oxide breakdown. >>>>> >>>> So you mean like a linear regulator? Because a hard disconnect would >>>> cause the uC to read this pin wrongly, and it reads it correctly. Or do >>>> you mean it disconnects somewhere above 5V? >>> 5V-tolerant INPUTS have no ESD diode to local VDD, just a "snap" diode >>> to ground. Thus only the input stage gate oxide has to stand-off the >>> 5V. >>> >>> 5V-tolerant OUTPUTS, that is outputs which also serve as INPUTS >>> (bi-directional bus I/O, etc.) use a disconnect above local VDD. >>> Visualize the dual series device with "body" at midpoint, that I've >>> shown here before as a battery-charge control device. >>> >> It's all I/O, since it's a 8051-family uC with regular cofigurable ports. >> >> >>> As in... >>> >>> http://www.analog-innovations.com/SED/PerfectDiodeForChargerIsolation.pdf >>> >> That would work, provided the comparator is past, has little or no >> hysteresis and the FETs are snappy. Because the signal integrity of an >> incoming 5V data stream must be maintained to full spec'd speed. >> >> >>>> If they say 5.8V, what's you gut feel it could really take if a surge or >>>> pulse salvo of a few msec comes through? It's amplitude would be >>>> slightly over 7V. because it leans into protective diodes we have up >>>> front of the uC port. Those are regular Si-diodes against the 5V rail >>>> and GND. >>> DC over-voltage is a no-no... ESD only. >>> >> DC will never exceed 5V and abs max is 5.8V. So you think ESD or surges >> (the usual machine-gun style bursts in EMC tests) are ok? We have it >> clamped to a 5V rail but it could really lean into those clamp diodes. > > This thread rattles around avoiding specifics. Is the "5V-tolerant" > input an input that has 3.3V as VDD? >Yes, it is, that's what I wrote in the original post :-) The uC has only a 3.3V supply, no 5V supply. But some lines coming in are from logic that is on 5V, so can't be ESD-clamped lower than 5V. -- Regards, Joerg http://www.analogconsultants.com/
Reply by ●June 26, 20132013-06-26
Spehro Pefhany wrote:> On Tue, 25 Jun 2013 22:21:52 -0700, Michael Karas > <mkaras@carousel-design.com> wrote: > >> [This followup was posted to sci.electronics.design and a copy was sent >> to the cited author.] >> >>>> DC will never exceed 5V and abs max is 5.8V. So you think ESD or >> surges >>>> (the usual machine-gun style bursts in EMC tests) are ok? We have it >>>> clamped to a 5V rail but it could really lean into those clamp diodes. >>> This thread rattles around avoiding specifics. Is the "5V-tolerant" >>> input an input that has 3.3V as VDD? >> >> Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the >> I/O Rail VDD. These pins default to typical 8051 style with quasi- >> bidirectional behavior with onboard pullup circuitry. The port pins can >> also be programmed to be output driven by a totem pole output to the VDD >> rail. > > I'd (thankfully) almost forgotten about those miserable quasi > bi-directional port pins. > > The schematic on page 161 does not appear to show the brief hard > (~100:1) pullup on 0->1 port-pin transition that old-skule 80C51s > have. If it's present it would be back of the ESD circuitry anyway. > > https://www.silabs.com/Support%20Documents/TechnicalDocs/C8051F02x.pdf >The problem is that, as usual, they write nothing about what's in the Schmitt buffer at the bottom of that schematic. Sometimes I wish IC designers were closer to the board level world and thus release more of the info that we really need. Because we board level guys have to deal with ESD pulses, RF bursts, nearby lightning, and whatnot. And then like in this case we have to get the whole thing through myriad agency certs which require good rationale and math. -- Regards, Joerg http://www.analogconsultants.com/
Reply by ●June 26, 20132013-06-26
On Wed, 26 Jun 2013 07:58:54 -0700, Joerg <invalid@invalid.invalid> wrote:>Spehro Pefhany wrote: >> On Tue, 25 Jun 2013 22:21:52 -0700, Michael Karas >> <mkaras@carousel-design.com> wrote: >> >>> [This followup was posted to sci.electronics.design and a copy was sent >>> to the cited author.] >>> >>>>> DC will never exceed 5V and abs max is 5.8V. So you think ESD or >>> surges >>>>> (the usual machine-gun style bursts in EMC tests) are ok? We have it >>>>> clamped to a 5V rail but it could really lean into those clamp diodes. >>>> This thread rattles around avoiding specifics. Is the "5V-tolerant" >>>> input an input that has 3.3V as VDD? >>> >>> Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the >>> I/O Rail VDD. These pins default to typical 8051 style with quasi- >>> bidirectional behavior with onboard pullup circuitry. The port pins can >>> also be programmed to be output driven by a totem pole output to the VDD >>> rail. >> >> I'd (thankfully) almost forgotten about those miserable quasi >> bi-directional port pins. >> >> The schematic on page 161 does not appear to show the brief hard >> (~100:1) pullup on 0->1 port-pin transition that old-skule 80C51s >> have. If it's present it would be back of the ESD circuitry anyway. >> >> https://www.silabs.com/Support%20Documents/TechnicalDocs/C8051F02x.pdf >> > >The problem is that, as usual, they write nothing about what's in the >Schmitt buffer at the bottom of that schematic. Sometimes I wish IC >designers were closer to the board level world and thus release more of >the info that we really need. Because we board level guys have to deal >with ESD pulses, RF bursts, nearby lightning, and whatnot. And then like >in this case we have to get the whole thing through myriad agency certs >which require good rationale and math.It's management. Note how LTspice is going all encrypted? And Analog Devices modeling efforts are now managed by a MARKETING VP, and they are ultimately heading to requiring simulation of their parts ONLY on their web-based simulator. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●June 26, 20132013-06-26
On Wed, 26 Jun 2013 07:52:30 -0700, Joerg <invalid@invalid.invalid> wrote:>Jim Thompson wrote: >> On Tue, 25 Jun 2013 17:54:52 -0700, Joerg <invalid@invalid.invalid> >> wrote: >> >>> Jim Thompson wrote: >>>> On Tue, 25 Jun 2013 17:31:34 -0700, Joerg <invalid@invalid.invalid> >>>> wrote: >>>> >>>>> Jim Thompson wrote: >>>>>> On Tue, 25 Jun 2013 16:41:40 -0400, Spehro Pefhany >>>>>> <speffSNIP@interlogDOTyou.knowwhat> wrote: >>>>>> >>>>>>> On Tue, 25 Jun 2013 11:02:06 -0700, Joerg <invalid@invalid.invalid> >>>>>>> wrote: >>>>>>> >>>>>>>> Folks, >>>>>>>> >>>>>>>> Got a Silicon Labs 8051Fxxx with 5V-tolerant ports. In the abs max it >>>>>>>> says 5.8V is the limit. Well, if one uses the typical diode against the >>>>>>>> 5V rail it could go slightly above 6V in case of a really big jolt. >>>>>>>> Since this 8051 does not have a 5V supply but just VDD (which hangs on >>>>>>>> 3.3V in this case) there can't be any parasitic substrate diodes dumping >>>>>>>> into a rail. >>>>>>>> >>>>>>>> Does anyone know the innards? Poly resistors? As usual, the datasheet is >>>>>>>> silent about this. >>>>>>> According to Xilinx, 5V tolerant pins can add a dozen or so components >>>>>>> per pin. Probably, as Lasse says, it behaves something like a zener >>>>>>> for inputs. >>>>>>> >>>>>>> If it's programmable as an output too, they have to add some parts to >>>>>>> keep current from flowing back through the off p-channel. >>>>>>> >>>>>>> I don't think you'll find real schematics openly available for this >>>>>>> stuff- on-chip ESD protection seems to be kind of a trade secret. >>>>>> "5V-tolerant" pins function by disconnect, not by clamping (somewhat >>>>>> like the schemes used in hi-Z when unpowered bus devices). The >>>>>> voltage limit is determined by oxide breakdown. >>>>>> >>>>> So you mean like a linear regulator? Because a hard disconnect would >>>>> cause the uC to read this pin wrongly, and it reads it correctly. Or do >>>>> you mean it disconnects somewhere above 5V? >>>> 5V-tolerant INPUTS have no ESD diode to local VDD, just a "snap" diode >>>> to ground. Thus only the input stage gate oxide has to stand-off the >>>> 5V. >>>> >>>> 5V-tolerant OUTPUTS, that is outputs which also serve as INPUTS >>>> (bi-directional bus I/O, etc.) use a disconnect above local VDD. >>>> Visualize the dual series device with "body" at midpoint, that I've >>>> shown here before as a battery-charge control device. >>>> >>> It's all I/O, since it's a 8051-family uC with regular cofigurable ports. >>> >>> >>>> As in... >>>> >>>> http://www.analog-innovations.com/SED/PerfectDiodeForChargerIsolation.pdf >>>> >>> That would work, provided the comparator is past, has little or no >>> hysteresis and the FETs are snappy. Because the signal integrity of an >>> incoming 5V data stream must be maintained to full spec'd speed. >>> >>> >>>>> If they say 5.8V, what's you gut feel it could really take if a surge or >>>>> pulse salvo of a few msec comes through? It's amplitude would be >>>>> slightly over 7V. because it leans into protective diodes we have up >>>>> front of the uC port. Those are regular Si-diodes against the 5V rail >>>>> and GND. >>>> DC over-voltage is a no-no... ESD only. >>>> >>> DC will never exceed 5V and abs max is 5.8V. So you think ESD or surges >>> (the usual machine-gun style bursts in EMC tests) are ok? We have it >>> clamped to a 5V rail but it could really lean into those clamp diodes. >> >> This thread rattles around avoiding specifics. Is the "5V-tolerant" >> input an input that has 3.3V as VDD? >> > >Yes, it is, that's what I wrote in the original post :-) > >The uC has only a 3.3V supply, no 5V supply. But some lines coming in >are from logic that is on 5V, so can't be ESD-clamped lower than 5V.OK. A "5V-tolerant" input accepts 5V signals because it has no ESD diode to VDD. ESD events are handled by what is called a "snap diode" to ground which avalanches at higher voltages. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
