Jim Thompson wrote:> On Wed, 26 Jun 2013 07:58:54 -0700, Joerg <invalid@invalid.invalid> > wrote: > >> Spehro Pefhany wrote: >>> On Tue, 25 Jun 2013 22:21:52 -0700, Michael Karas >>> <mkaras@carousel-design.com> wrote: >>> >>>> [This followup was posted to sci.electronics.design and a copy was sent >>>> to the cited author.] >>>> >>>>>> DC will never exceed 5V and abs max is 5.8V. So you think ESD or >>>> surges >>>>>> (the usual machine-gun style bursts in EMC tests) are ok? We have it >>>>>> clamped to a 5V rail but it could really lean into those clamp diodes. >>>>> This thread rattles around avoiding specifics. Is the "5V-tolerant" >>>>> input an input that has 3.3V as VDD? >>>> >>>> Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the >>>> I/O Rail VDD. These pins default to typical 8051 style with quasi- >>>> bidirectional behavior with onboard pullup circuitry. The port pins can >>>> also be programmed to be output driven by a totem pole output to the VDD >>>> rail. >>> I'd (thankfully) almost forgotten about those miserable quasi >>> bi-directional port pins. >>> >>> The schematic on page 161 does not appear to show the brief hard >>> (~100:1) pullup on 0->1 port-pin transition that old-skule 80C51s >>> have. If it's present it would be back of the ESD circuitry anyway. >>> >>> https://www.silabs.com/Support%20Documents/TechnicalDocs/C8051F02x.pdf >>> >> The problem is that, as usual, they write nothing about what's in the >> Schmitt buffer at the bottom of that schematic. Sometimes I wish IC >> designers were closer to the board level world and thus release more of >> the info that we really need. Because we board level guys have to deal >> with ESD pulses, RF bursts, nearby lightning, and whatnot. And then like >> in this case we have to get the whole thing through myriad agency certs >> which require good rationale and math. > > It's management. Note how LTspice is going all encrypted? >You meant damagement? :-)> And Analog Devices modeling efforts are now managed by a MARKETING VP, > and they are ultimately heading to requiring simulation of their parts > ONLY on their web-based simulator. >That would be a marketing decision that borders on stupid. -- Regards, Joerg http://www.analogconsultants.com/
8051F020 series, 5V tolerant input schematic?
Started by ●June 25, 2013
Reply by ●June 26, 20132013-06-26
Reply by ●June 26, 20132013-06-26
On Wed, 26 Jun 2013 09:08:52 -0700, Joerg <invalid@invalid.invalid> wrote:>Jim Thompson wrote: >> On Wed, 26 Jun 2013 07:58:54 -0700, Joerg <invalid@invalid.invalid> >> wrote: >> >>> Spehro Pefhany wrote: >>>> On Tue, 25 Jun 2013 22:21:52 -0700, Michael Karas >>>> <mkaras@carousel-design.com> wrote: >>>> >>>>> [This followup was posted to sci.electronics.design and a copy was sent >>>>> to the cited author.] >>>>> >>>>>>> DC will never exceed 5V and abs max is 5.8V. So you think ESD or >>>>> surges >>>>>>> (the usual machine-gun style bursts in EMC tests) are ok? We have it >>>>>>> clamped to a 5V rail but it could really lean into those clamp diodes. >>>>>> This thread rattles around avoiding specifics. Is the "5V-tolerant" >>>>>> input an input that has 3.3V as VDD? >>>>> >>>>> Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the >>>>> I/O Rail VDD. These pins default to typical 8051 style with quasi- >>>>> bidirectional behavior with onboard pullup circuitry. The port pins can >>>>> also be programmed to be output driven by a totem pole output to the VDD >>>>> rail. >>>> I'd (thankfully) almost forgotten about those miserable quasi >>>> bi-directional port pins. >>>> >>>> The schematic on page 161 does not appear to show the brief hard >>>> (~100:1) pullup on 0->1 port-pin transition that old-skule 80C51s >>>> have. If it's present it would be back of the ESD circuitry anyway. >>>> >>>> https://www.silabs.com/Support%20Documents/TechnicalDocs/C8051F02x.pdf >>>> >>> The problem is that, as usual, they write nothing about what's in the >>> Schmitt buffer at the bottom of that schematic. Sometimes I wish IC >>> designers were closer to the board level world and thus release more of >>> the info that we really need. Because we board level guys have to deal >>> with ESD pulses, RF bursts, nearby lightning, and whatnot. And then like >>> in this case we have to get the whole thing through myriad agency certs >>> which require good rationale and math. >> >> It's management. Note how LTspice is going all encrypted? >> > >You meant damagement? :-) > > >> And Analog Devices modeling efforts are now managed by a MARKETING VP, >> and they are ultimately heading to requiring simulation of their parts >> ONLY on their web-based simulator. >> > >That would be a marketing decision that borders on stupid.I was there (San Jose) last August trying to convince them of the best way to do modeling... let me see the real netlist and then I'd match it behaviorally. The MARKETING VP nixed the idea. (I even showed them various posts from this newsgroup complaining about model quality... did no good.) ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●June 26, 20132013-06-26
Jim Thompson wrote:> On Wed, 26 Jun 2013 09:08:52 -0700, Joerg <invalid@invalid.invalid> > wrote: > >> Jim Thompson wrote: >>> On Wed, 26 Jun 2013 07:58:54 -0700, Joerg <invalid@invalid.invalid> >>> wrote: >>> >>>> Spehro Pefhany wrote: >>>>> On Tue, 25 Jun 2013 22:21:52 -0700, Michael Karas >>>>> <mkaras@carousel-design.com> wrote: >>>>> >>>>>> [This followup was posted to sci.electronics.design and a copy was sent >>>>>> to the cited author.] >>>>>> >>>>>>>> DC will never exceed 5V and abs max is 5.8V. So you think ESD or >>>>>> surges >>>>>>>> (the usual machine-gun style bursts in EMC tests) are ok? We have it >>>>>>>> clamped to a 5V rail but it could really lean into those clamp diodes. >>>>>>> This thread rattles around avoiding specifics. Is the "5V-tolerant" >>>>>>> input an input that has 3.3V as VDD? >>>>>> >>>>>> Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the >>>>>> I/O Rail VDD. These pins default to typical 8051 style with quasi- >>>>>> bidirectional behavior with onboard pullup circuitry. The port pins can >>>>>> also be programmed to be output driven by a totem pole output to the VDD >>>>>> rail. >>>>> I'd (thankfully) almost forgotten about those miserable quasi >>>>> bi-directional port pins. >>>>> >>>>> The schematic on page 161 does not appear to show the brief hard >>>>> (~100:1) pullup on 0->1 port-pin transition that old-skule 80C51s >>>>> have. If it's present it would be back of the ESD circuitry anyway. >>>>> >>>>> https://www.silabs.com/Support%20Documents/TechnicalDocs/C8051F02x.pdf >>>>> >>>> The problem is that, as usual, they write nothing about what's in the >>>> Schmitt buffer at the bottom of that schematic. Sometimes I wish IC >>>> designers were closer to the board level world and thus release more of >>>> the info that we really need. Because we board level guys have to deal >>>> with ESD pulses, RF bursts, nearby lightning, and whatnot. And then like >>>> in this case we have to get the whole thing through myriad agency certs >>>> which require good rationale and math. >>> It's management. Note how LTspice is going all encrypted? >>> >> You meant damagement? :-) >> >> >>> And Analog Devices modeling efforts are now managed by a MARKETING VP, >>> and they are ultimately heading to requiring simulation of their parts >>> ONLY on their web-based simulator. >>> >> That would be a marketing decision that borders on stupid. > > I was there (San Jose) last August trying to convince them of the best > way to do modeling... let me see the real netlist and then I'd match > it behaviorally. The MARKETING VP nixed the idea. > > (I even showed them various posts from this newsgroup complaining > about model quality... did no good.) >Then I assume they'll never understand why, when it comes to performance and cost is not a major issue, I always default to LTC and never even look at AD unless I can't find a chip at LTC. This is because LTC has behavioral models that work in LTSpice and AD does not. Same with TI. Who in their right mind would install and learn half a dozen competing "free" simulators? If they can't understand that LTSpice is the de facto winner, oh well. -- Regards, Joerg http://www.analogconsultants.com/
Reply by ●June 26, 20132013-06-26
On Wed, 26 Jun 2013 09:26:58 -0700, Joerg <invalid@invalid.invalid> wrote:>Jim Thompson wrote: >> On Wed, 26 Jun 2013 09:08:52 -0700, Joerg <invalid@invalid.invalid> >> wrote: >> >>> Jim Thompson wrote: >>>> On Wed, 26 Jun 2013 07:58:54 -0700, Joerg <invalid@invalid.invalid> >>>> wrote: >>>> >>>>> Spehro Pefhany wrote: >>>>>> On Tue, 25 Jun 2013 22:21:52 -0700, Michael Karas >>>>>> <mkaras@carousel-design.com> wrote: >>>>>> >>>>>>> [This followup was posted to sci.electronics.design and a copy was sent >>>>>>> to the cited author.] >>>>>>> >>>>>>>>> DC will never exceed 5V and abs max is 5.8V. So you think ESD or >>>>>>> surges >>>>>>>>> (the usual machine-gun style bursts in EMC tests) are ok? We have it >>>>>>>>> clamped to a 5V rail but it could really lean into those clamp diodes. >>>>>>>> This thread rattles around avoiding specifics. Is the "5V-tolerant" >>>>>>>> input an input that has 3.3V as VDD? >>>>>>> >>>>>>> Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the >>>>>>> I/O Rail VDD. These pins default to typical 8051 style with quasi- >>>>>>> bidirectional behavior with onboard pullup circuitry. The port pins can >>>>>>> also be programmed to be output driven by a totem pole output to the VDD >>>>>>> rail. >>>>>> I'd (thankfully) almost forgotten about those miserable quasi >>>>>> bi-directional port pins. >>>>>> >>>>>> The schematic on page 161 does not appear to show the brief hard >>>>>> (~100:1) pullup on 0->1 port-pin transition that old-skule 80C51s >>>>>> have. If it's present it would be back of the ESD circuitry anyway. >>>>>> >>>>>> https://www.silabs.com/Support%20Documents/TechnicalDocs/C8051F02x.pdf >>>>>> >>>>> The problem is that, as usual, they write nothing about what's in the >>>>> Schmitt buffer at the bottom of that schematic. Sometimes I wish IC >>>>> designers were closer to the board level world and thus release more of >>>>> the info that we really need. Because we board level guys have to deal >>>>> with ESD pulses, RF bursts, nearby lightning, and whatnot. And then like >>>>> in this case we have to get the whole thing through myriad agency certs >>>>> which require good rationale and math. >>>> It's management. Note how LTspice is going all encrypted? >>>> >>> You meant damagement? :-) >>> >>> >>>> And Analog Devices modeling efforts are now managed by a MARKETING VP, >>>> and they are ultimately heading to requiring simulation of their parts >>>> ONLY on their web-based simulator. >>>> >>> That would be a marketing decision that borders on stupid. >> >> I was there (San Jose) last August trying to convince them of the best >> way to do modeling... let me see the real netlist and then I'd match >> it behaviorally. The MARKETING VP nixed the idea. >> >> (I even showed them various posts from this newsgroup complaining >> about model quality... did no good.) >> > >Then I assume they'll never understand why, when it comes to performance >and cost is not a major issue, I always default to LTC and never even >look at AD unless I can't find a chip at LTC. This is because LTC has >behavioral models that work in LTSpice and AD does not. > >Same with TI. Who in their right mind would install and learn half a >dozen competing "free" simulators? If they can't understand that LTSpice >is the de facto winner, oh well.PSpice will run ANY non-encrypted model, as will LTspice, HSpice, any Cadence tool, and most amateur spin-offs. Encrypting so a model will run only on the parent tool turns me off. What do you do if you want to mix LT and ADI and TI parts on your board? You're screwed. Joerg, sounds like LT is happy as a clam with you. You're a locked-in customer. Enjoy >:-} ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●June 26, 20132013-06-26
Jim Thompson wrote:> On Tue, 25 Jun 2013 17:42:32 -0700 (PDT), > bloggs.fredbloggs.fred@gmail.com wrote: >Fred, my news server did not carry your post. Maybe it came via google groups?>> You're still fixated on clamping, which would make no sensewhatsoever in a mixed signal low power digital environment. ... It makes perfect sense to clamp. Stuff operated in a rough environment has to have all inputs clamped or things will fry. Surges, bursts, Lighting, and so on.> ... The highvoltage tolerant inputs are a variation of the theme shown below in one form or another. Operation is self-explanatory:>> Please view in a fixed-width font such as Courier. >>Your line breaks don't work. Had to do a "selective re-wrap" or it wuold have garbled your ASCII schematic.>> . >> . >> . >> . EX High Voltage Tolerant Input >> . >> . >> . >> . VDD >> . | PMOS keeper >> . - >> . || >> . ||o----------. >> . VDD _|| | >> . | | | >> . | G | | >> . input ___ | | \ | | \ pad >> . pad ___ | | \ | | \ to core >> . _ D | | S | | \ | | \ _ >> . |_| ------ ----+-----| o --+---| o----|_| >> . | / | / >> . series | / | / buffer >> . NMOS | / Schmitt | / CMOS >> . >> . >The PMOS keeper would make for a pretty leaky input, drawing quite some current. Else it would become slow because the series NMOS loses steam as the input voltage approaches VDD.> That looks vaguely like my USB patent on the work I did for Intel. > I'll dredge that up and post it. >It's I/O lines in my case, pretty much all uC offer I/O on all ports except where comparators are piped out separately. So it may be more like in Jim's post yesterday, the classic double-FET "semiconductor relay". But all this doesn't really matter, since there isn't any data when the oxide or whatever is the weakest link will pop if abs max says 5.8V. For short spikes it will usually hold much higher but the datasheet is kind of incomplete in that domain. That's what I'd like to know, how high for spikes? -- Regards, Joerg http://www.analogconsultants.com/
Reply by ●June 26, 20132013-06-26
Jim Thompson wrote:> On Wed, 26 Jun 2013 09:26:58 -0700, Joerg <invalid@invalid.invalid> > wrote: > >> Jim Thompson wrote: >>> On Wed, 26 Jun 2013 09:08:52 -0700, Joerg <invalid@invalid.invalid> >>> wrote: >>> >>>> Jim Thompson wrote: >>>>> On Wed, 26 Jun 2013 07:58:54 -0700, Joerg <invalid@invalid.invalid> >>>>> wrote: >>>>> >>>>>> Spehro Pefhany wrote: >>>>>>> On Tue, 25 Jun 2013 22:21:52 -0700, Michael Karas >>>>>>> <mkaras@carousel-design.com> wrote: >>>>>>> >>>>>>>> [This followup was posted to sci.electronics.design and a copy was sent >>>>>>>> to the cited author.] >>>>>>>> >>>>>>>>>> DC will never exceed 5V and abs max is 5.8V. So you think ESD or >>>>>>>> surges >>>>>>>>>> (the usual machine-gun style bursts in EMC tests) are ok? We have it >>>>>>>>>> clamped to a 5V rail but it could really lean into those clamp diodes. >>>>>>>>> This thread rattles around avoiding specifics. Is the "5V-tolerant" >>>>>>>>> input an input that has 3.3V as VDD? >>>>>>>> >>>>>>>> Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the >>>>>>>> I/O Rail VDD. These pins default to typical 8051 style with quasi- >>>>>>>> bidirectional behavior with onboard pullup circuitry. The port pins can >>>>>>>> also be programmed to be output driven by a totem pole output to the VDD >>>>>>>> rail. >>>>>>> I'd (thankfully) almost forgotten about those miserable quasi >>>>>>> bi-directional port pins. >>>>>>> >>>>>>> The schematic on page 161 does not appear to show the brief hard >>>>>>> (~100:1) pullup on 0->1 port-pin transition that old-skule 80C51s >>>>>>> have. If it's present it would be back of the ESD circuitry anyway. >>>>>>> >>>>>>> https://www.silabs.com/Support%20Documents/TechnicalDocs/C8051F02x.pdf >>>>>>> >>>>>> The problem is that, as usual, they write nothing about what's in the >>>>>> Schmitt buffer at the bottom of that schematic. Sometimes I wish IC >>>>>> designers were closer to the board level world and thus release more of >>>>>> the info that we really need. Because we board level guys have to deal >>>>>> with ESD pulses, RF bursts, nearby lightning, and whatnot. And then like >>>>>> in this case we have to get the whole thing through myriad agency certs >>>>>> which require good rationale and math. >>>>> It's management. Note how LTspice is going all encrypted? >>>>> >>>> You meant damagement? :-) >>>> >>>> >>>>> And Analog Devices modeling efforts are now managed by a MARKETING VP, >>>>> and they are ultimately heading to requiring simulation of their parts >>>>> ONLY on their web-based simulator. >>>>> >>>> That would be a marketing decision that borders on stupid. >>> I was there (San Jose) last August trying to convince them of the best >>> way to do modeling... let me see the real netlist and then I'd match >>> it behaviorally. The MARKETING VP nixed the idea. >>> >>> (I even showed them various posts from this newsgroup complaining >>> about model quality... did no good.) >>> >> Then I assume they'll never understand why, when it comes to performance >> and cost is not a major issue, I always default to LTC and never even >> look at AD unless I can't find a chip at LTC. This is because LTC has >> behavioral models that work in LTSpice and AD does not. >> >> Same with TI. Who in their right mind would install and learn half a >> dozen competing "free" simulators? If they can't understand that LTSpice >> is the de facto winner, oh well. > > PSpice will run ANY non-encrypted model, as will LTspice, HSpice, any > Cadence tool, and most amateur spin-offs. >If you run a complicated switcher non-behavioral (and I had to do that) the sims take forever. For designing SMPS that clearly is not the most efficient method.> Encrypting so a model will run only on the parent tool turns me off.Me, too.> What do you do if you want to mix LT and ADI and TI parts on your > board? You're screwed. >On high end designs I never do that, and there is no need to. You can usually get everything at LTC. Except for some hardcore RF stuff and then that gets simulated separately. If it has to be cheap then no special ICs are used anyhow most of the time. For example, my first mass-produced device with a boost converter revolves around a CD40106 as the "highest-tech" chip. There is no dedicated PWM chip because that would have added at least 10c back in the early 90's.> Joerg, sounds like LT is happy as a clam with you. You're a locked-in > customer. Enjoy >:-} >Well, yeah, at some point you have to pick one and run with that. I have made my choice, and that choice is LTC. -- Regards, Joerg http://www.analogconsultants.com/
Reply by ●June 26, 20132013-06-26
On Wed, 26 Jun 2013 10:04:19 -0700, Joerg <invalid@invalid.invalid> wrote:>Jim Thompson wrote: >> On Wed, 26 Jun 2013 09:26:58 -0700, Joerg <invalid@invalid.invalid> >> wrote: >> >>> Jim Thompson wrote: >>>> On Wed, 26 Jun 2013 09:08:52 -0700, Joerg <invalid@invalid.invalid> >>>> wrote: >>>> >>>>> Jim Thompson wrote: >>>>>> On Wed, 26 Jun 2013 07:58:54 -0700, Joerg <invalid@invalid.invalid> >>>>>> wrote: >>>>>> >>>>>>> Spehro Pefhany wrote: >>>>>>>> On Tue, 25 Jun 2013 22:21:52 -0700, Michael Karas >>>>>>>> <mkaras@carousel-design.com> wrote: >>>>>>>> >>>>>>>>> [This followup was posted to sci.electronics.design and a copy was sent >>>>>>>>> to the cited author.] >>>>>>>>> >>>>>>>>>>> DC will never exceed 5V and abs max is 5.8V. So you think ESD or >>>>>>>>> surges >>>>>>>>>>> (the usual machine-gun style bursts in EMC tests) are ok? We have it >>>>>>>>>>> clamped to a 5V rail but it could really lean into those clamp diodes. >>>>>>>>>> This thread rattles around avoiding specifics. Is the "5V-tolerant" >>>>>>>>>> input an input that has 3.3V as VDD? >>>>>>>>> >>>>>>>>> Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the >>>>>>>>> I/O Rail VDD. These pins default to typical 8051 style with quasi- >>>>>>>>> bidirectional behavior with onboard pullup circuitry. The port pins can >>>>>>>>> also be programmed to be output driven by a totem pole output to the VDD >>>>>>>>> rail. >>>>>>>> I'd (thankfully) almost forgotten about those miserable quasi >>>>>>>> bi-directional port pins. >>>>>>>> >>>>>>>> The schematic on page 161 does not appear to show the brief hard >>>>>>>> (~100:1) pullup on 0->1 port-pin transition that old-skule 80C51s >>>>>>>> have. If it's present it would be back of the ESD circuitry anyway. >>>>>>>> >>>>>>>> https://www.silabs.com/Support%20Documents/TechnicalDocs/C8051F02x.pdf >>>>>>>> >>>>>>> The problem is that, as usual, they write nothing about what's in the >>>>>>> Schmitt buffer at the bottom of that schematic. Sometimes I wish IC >>>>>>> designers were closer to the board level world and thus release more of >>>>>>> the info that we really need. Because we board level guys have to deal >>>>>>> with ESD pulses, RF bursts, nearby lightning, and whatnot. And then like >>>>>>> in this case we have to get the whole thing through myriad agency certs >>>>>>> which require good rationale and math. >>>>>> It's management. Note how LTspice is going all encrypted? >>>>>> >>>>> You meant damagement? :-) >>>>> >>>>> >>>>>> And Analog Devices modeling efforts are now managed by a MARKETING VP, >>>>>> and they are ultimately heading to requiring simulation of their parts >>>>>> ONLY on their web-based simulator. >>>>>> >>>>> That would be a marketing decision that borders on stupid. >>>> I was there (San Jose) last August trying to convince them of the best >>>> way to do modeling... let me see the real netlist and then I'd match >>>> it behaviorally. The MARKETING VP nixed the idea. >>>> >>>> (I even showed them various posts from this newsgroup complaining >>>> about model quality... did no good.) >>>> >>> Then I assume they'll never understand why, when it comes to performance >>> and cost is not a major issue, I always default to LTC and never even >>> look at AD unless I can't find a chip at LTC. This is because LTC has >>> behavioral models that work in LTSpice and AD does not. >>> >>> Same with TI. Who in their right mind would install and learn half a >>> dozen competing "free" simulators? If they can't understand that LTSpice >>> is the de facto winner, oh well. >> >> PSpice will run ANY non-encrypted model, as will LTspice, HSpice, any >> Cadence tool, and most amateur spin-offs. >> > >If you run a complicated switcher non-behavioral (and I had to do that) >the sims take forever. For designing SMPS that clearly is not the most >efficient method. > > >> Encrypting so a model will run only on the parent tool turns me off. > > >Me, too. > > >> What do you do if you want to mix LT and ADI and TI parts on your >> board? You're screwed. >> > >On high end designs I never do that, and there is no need to. You can >usually get everything at LTC. Except for some hardcore RF stuff and >then that gets simulated separately. > >If it has to be cheap then no special ICs are used anyhow most of the >time. For example, my first mass-produced device with a boost converter >revolves around a CD40106 as the "highest-tech" chip. There is no >dedicated PWM chip because that would have added at least 10c back in >the early 90's. > > >> Joerg, sounds like LT is happy as a clam with you. You're a locked-in >> customer. Enjoy >:-} >> > >Well, yeah, at some point you have to pick one and run with that. I have >made my choice, and that choice is LTC."Most" of their stuff is good. I've had a recent situation where an encrypted model works just fine on LTspice, but not on a PCB. The FAE was flummoxed, referred the problem to factory... 4 months have passed, no solution. I posted the problem on the LTspice list, but was basically told, "LTspice, love it or leave it" :-( All I've been able to find out is that LTspice encrypted models are behavioral internally. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●June 26, 20132013-06-26
Jim Thompson wrote:> On Wed, 26 Jun 2013 10:04:19 -0700, Joerg <invalid@invalid.invalid> > wrote: > >> Jim Thompson wrote: >>> On Wed, 26 Jun 2013 09:26:58 -0700, Joerg <invalid@invalid.invalid> >>> wrote: >>> >>>> Jim Thompson wrote: >>>>> On Wed, 26 Jun 2013 09:08:52 -0700, Joerg <invalid@invalid.invalid> >>>>> wrote: >>>>> >>>>>> Jim Thompson wrote:[...]>>>>>>> And Analog Devices modeling efforts are now managed by a MARKETING VP, >>>>>>> and they are ultimately heading to requiring simulation of their parts >>>>>>> ONLY on their web-based simulator. >>>>>>> >>>>>> That would be a marketing decision that borders on stupid. >>>>> I was there (San Jose) last August trying to convince them of the best >>>>> way to do modeling... let me see the real netlist and then I'd match >>>>> it behaviorally. The MARKETING VP nixed the idea. >>>>> >>>>> (I even showed them various posts from this newsgroup complaining >>>>> about model quality... did no good.) >>>>> >>>> Then I assume they'll never understand why, when it comes to performance >>>> and cost is not a major issue, I always default to LTC and never even >>>> look at AD unless I can't find a chip at LTC. This is because LTC has >>>> behavioral models that work in LTSpice and AD does not. >>>> >>>> Same with TI. Who in their right mind would install and learn half a >>>> dozen competing "free" simulators? If they can't understand that LTSpice >>>> is the de facto winner, oh well. >>> PSpice will run ANY non-encrypted model, as will LTspice, HSpice, any >>> Cadence tool, and most amateur spin-offs. >>> >> If you run a complicated switcher non-behavioral (and I had to do that) >> the sims take forever. For designing SMPS that clearly is not the most >> efficient method. >> >> >>> Encrypting so a model will run only on the parent tool turns me off. >> >> Me, too. >> >> >>> What do you do if you want to mix LT and ADI and TI parts on your >>> board? You're screwed. >>> >> On high end designs I never do that, and there is no need to. You can >> usually get everything at LTC. Except for some hardcore RF stuff and >> then that gets simulated separately. >> >> If it has to be cheap then no special ICs are used anyhow most of the >> time. For example, my first mass-produced device with a boost converter >> revolves around a CD40106 as the "highest-tech" chip. There is no >> dedicated PWM chip because that would have added at least 10c back in >> the early 90's. >> >> >>> Joerg, sounds like LT is happy as a clam with you. You're a locked-in >>> customer. Enjoy >:-} >>> >> Well, yeah, at some point you have to pick one and run with that. I have >> made my choice, and that choice is LTC. > > "Most" of their stuff is good. I've had a recent situation where an > encrypted model works just fine on LTspice, but not on a PCB. >Same here, the LT6700 had a glitch on the chip and I was the unfortunate one who had to discover that the hard way.> The FAE was flummoxed, referred the problem to factory... 4 months > have passed, no solution. >In my case the LTC design engineers looked at it right away, found out that it was indeed a bug, fessed up, apologized, rolled up the sleeves and corrected things. That left a very positive impression with me. Over the years I experienced numerous similar situations with other, larger manufacturers. The classic solution was an attempt to cover it up.> I posted the problem on the LTspice list, but was basically told, > "LTspice, love it or leave it" :-( > > All I've been able to find out is that LTspice encrypted models are > behavioral internally. >They are, mostly. That is the reason why you can simulate switchers so blazingly fast. This does come with pitfalls and (minor) risks but it sure beats non-behavioral sims that take hours. -- Regards, Joerg http://www.analogconsultants.com/
Reply by ●June 26, 20132013-06-26
On Wed, 26 Jun 2013 10:54:54 -0700, Joerg <invalid@invalid.invalid> wrote:>Jim Thompson wrote: >> On Wed, 26 Jun 2013 10:04:19 -0700, Joerg <invalid@invalid.invalid> >> wrote: >> >>> Jim Thompson wrote: >>>> On Wed, 26 Jun 2013 09:26:58 -0700, Joerg <invalid@invalid.invalid> >>>> wrote: >>>> >>>>> Jim Thompson wrote: >>>>>> On Wed, 26 Jun 2013 09:08:52 -0700, Joerg <invalid@invalid.invalid> >>>>>> wrote: >>>>>> >>>>>>> Jim Thompson wrote: > >[...] > > >>>>>>>> And Analog Devices modeling efforts are now managed by a MARKETING VP, >>>>>>>> and they are ultimately heading to requiring simulation of their parts >>>>>>>> ONLY on their web-based simulator. >>>>>>>> >>>>>>> That would be a marketing decision that borders on stupid. >>>>>> I was there (San Jose) last August trying to convince them of the best >>>>>> way to do modeling... let me see the real netlist and then I'd match >>>>>> it behaviorally. The MARKETING VP nixed the idea. >>>>>> >>>>>> (I even showed them various posts from this newsgroup complaining >>>>>> about model quality... did no good.) >>>>>> >>>>> Then I assume they'll never understand why, when it comes to performance >>>>> and cost is not a major issue, I always default to LTC and never even >>>>> look at AD unless I can't find a chip at LTC. This is because LTC has >>>>> behavioral models that work in LTSpice and AD does not. >>>>> >>>>> Same with TI. Who in their right mind would install and learn half a >>>>> dozen competing "free" simulators? If they can't understand that LTSpice >>>>> is the de facto winner, oh well. >>>> PSpice will run ANY non-encrypted model, as will LTspice, HSpice, any >>>> Cadence tool, and most amateur spin-offs. >>>> >>> If you run a complicated switcher non-behavioral (and I had to do that) >>> the sims take forever. For designing SMPS that clearly is not the most >>> efficient method. >>> >>> >>>> Encrypting so a model will run only on the parent tool turns me off. >>> >>> Me, too. >>> >>> >>>> What do you do if you want to mix LT and ADI and TI parts on your >>>> board? You're screwed. >>>> >>> On high end designs I never do that, and there is no need to. You can >>> usually get everything at LTC. Except for some hardcore RF stuff and >>> then that gets simulated separately. >>> >>> If it has to be cheap then no special ICs are used anyhow most of the >>> time. For example, my first mass-produced device with a boost converter >>> revolves around a CD40106 as the "highest-tech" chip. There is no >>> dedicated PWM chip because that would have added at least 10c back in >>> the early 90's. >>> >>> >>>> Joerg, sounds like LT is happy as a clam with you. You're a locked-in >>>> customer. Enjoy >:-} >>>> >>> Well, yeah, at some point you have to pick one and run with that. I have >>> made my choice, and that choice is LTC. >> >> "Most" of their stuff is good. I've had a recent situation where an >> encrypted model works just fine on LTspice, but not on a PCB. >> > >Same here, the LT6700 had a glitch on the chip and I was the unfortunate >one who had to discover that the hard way. > > >> The FAE was flummoxed, referred the problem to factory... 4 months >> have passed, no solution. >> > >In my case the LTC design engineers looked at it right away, found out >that it was indeed a bug, fessed up, apologized, rolled up the sleeves >and corrected things. That left a very positive impression with me. > >Over the years I experienced numerous similar situations with other, >larger manufacturers. The classic solution was an attempt to cover it up. > > >> I posted the problem on the LTspice list, but was basically told, >> "LTspice, love it or leave it" :-( >> >> All I've been able to find out is that LTspice encrypted models are >> behavioral internally. >> > >They are, mostly. That is the reason why you can simulate switchers so >blazingly fast. This does come with pitfalls and (minor) risks but it >sure beats non-behavioral sims that take hours.I've been at this simulation stuff so long, I can recall simulations taking DAYS! But today's simulators (and CPU's) are so much faster... it's rare for a complex simulation, at device-level, to take more than 20-30 minutes. Patience is a virtue ;-) ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●June 26, 20132013-06-26
Jim Thompson wrote:> On Wed, 26 Jun 2013 10:54:54 -0700, Joerg <invalid@invalid.invalid> > wrote: > >> Jim Thompson wrote:[...]>>> I posted the problem on the LTspice list, but was basically told, >>> "LTspice, love it or leave it" :-( >>> >>> All I've been able to find out is that LTspice encrypted models are >>> behavioral internally. >>> >> They are, mostly. That is the reason why you can simulate switchers so >> blazingly fast. This does come with pitfalls and (minor) risks but it >> sure beats non-behavioral sims that take hours. > > I've been at this simulation stuff so long, I can recall simulations > taking DAYS! >Same here. I still have the cloth-covered binders from Microsim. Got that in 1990, I think. Before that I used ECA224.> But today's simulators (and CPU's) are so much faster... it's rare for > a complex simulation, at device-level, to take more than 20-30 > minutes. > > Patience is a virtue ;-) >Yeah, in the winter it's ok. But in July/August times it has happened that too much simulating brought the office temps from 85F to over 90F. -- Regards, Joerg http://www.analogconsultants.com/
