On Monday, September 25, 2023 at 10:37:25 PM UTC+5:30, John Larkin wrote:> Does anyone know anything about the effects of negaive-voltage > zenering the gate of a SiC power fet? > > Specifically, I'm designing a gate driver for the Cree C2M0280120D and > I'm wondering about what might happen in the rare case that I zener > the gate by a mA or so. The intent is to drive it -5 to +15, but the > -5 could be more in some pathological case. > > I'll get some from stock later and test some, but that's necessarily > short-term. I have seen long-term changes in some Gan parts from > abusing the gate a bit. > > googling hasn't helped.Please check out: https://www.powerelectronicsnews.com/how-to-select-the-right-gate-driver-for-your-sic-mosfet/ Also if you use the search string "SiC FET gate driver" on Google, a list of semiconductor device manufacturers(notably Infinieon, TI etc.,) is shown, which have whole sets of gate driver ICs for both SiC and GaN power FETs.
SiC fet gate damage
Started by ●September 25, 2023
Reply by ●September 27, 20232023-09-27
Reply by ●September 27, 20232023-09-27
On Tue, 26 Sep 2023 23:55:26 -0700 (PDT), amal banerjee <dakupoto@gmail.com> wrote:>On Monday, September 25, 2023 at 10:37:25?PM UTC+5:30, John Larkin wrote: >> Does anyone know anything about the effects of negaive-voltage >> zenering the gate of a SiC power fet? >> >> Specifically, I'm designing a gate driver for the Cree C2M0280120D and >> I'm wondering about what might happen in the rare case that I zener >> the gate by a mA or so. The intent is to drive it -5 to +15, but the >> -5 could be more in some pathological case. >> >> I'll get some from stock later and test some, but that's necessarily >> short-term. I have seen long-term changes in some Gan parts from >> abusing the gate a bit. >> >> googling hasn't helped. >Please check out: >https://www.powerelectronicsnews.com/how-to-select-the-right-gate-driver-for-your-sic-mosfet/ >Also if you use the search string "SiC FET gate driver" on Google, a list of semiconductor device >manufacturers(notably Infinieon, TI etc.,) is shown, which have whole sets of gate driver ICs for both >SiC and GaN power FETs. >One market for SiC fets is as high power IGBT replacements, where speed and especially insertion delay don't much matter. Those gate drivers are super slow, sometimes hundreds of ns delay. I want speed. The UCC21520 is pretty fast, both prop delay and edge rates into a modest-sized SiC fet. I could go faster with a home-made driver, but shouldn't need to go to that much trouble to save a few ns. One problem with SiC fets is that, compared to silicon mosfets, they have high internal gate resistances. Swinging negative on the gate drive slams them through their threshold voltage and helps them turn off faster. They don't need negative swing otherwise. GaN is great to drive. The EPC parts can be driven unipolar from a cheap TinyLogic cmos gate. That in turn can make a good SiC gate drive. Fast and complex. The volume markets for GaN and SiC are power and RF.
Reply by ●September 27, 20232023-09-27
On Monday, September 25, 2023 at 1:07:25 PM UTC-4, John Larkin wrote:> Does anyone know anything about the effects of negaive-voltage > zenering the gate of a SiC power fet? > > Specifically, I'm designing a gate driver for the Cree C2M0280120D and > I'm wondering about what might happen in the rare case that I zener > the gate by a mA or so. The intent is to drive it -5 to +15, but the > -5 could be more in some pathological case. > > I'll get some from stock later and test some, but that's necessarily > short-term. I have seen long-term changes in some Gan parts from > abusing the gate a bit. > > googling hasn't helped.Use another SiC to clamp that gate drive to a safe level.
Reply by ●September 27, 20232023-09-27
On Monday, September 25, 2023 at 1:07:25 PM UTC-4, John Larkin wrote:> Does anyone know anything about the effects of negaive-voltage > zenering the gate of a SiC power fet? > > Specifically, I'm designing a gate driver for the Cree C2M0280120D and > I'm wondering about what might happen in the rare case that I zener > the gate by a mA or so. The intent is to drive it -5 to +15, but the > -5 could be more in some pathological case. > > I'll get some from stock later and test some, but that's necessarily > short-term. I have seen long-term changes in some Gan parts from > abusing the gate a bit. > > googling hasn't helped.What does your gate driver look like? Maybe you just need better decoupling.
Reply by ●September 27, 20232023-09-27
On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs <bloggs.fredbloggs.fred@gmail.com> wrote:>On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote: >> Does anyone know anything about the effects of negaive-voltage >> zenering the gate of a SiC power fet? >> >> Specifically, I'm designing a gate driver for the Cree C2M0280120D and >> I'm wondering about what might happen in the rare case that I zener >> the gate by a mA or so. The intent is to drive it -5 to +15, but the >> -5 could be more in some pathological case. >> >> I'll get some from stock later and test some, but that's necessarily >> short-term. I have seen long-term changes in some Gan parts from >> abusing the gate a bit. >> >> googling hasn't helped. > >What does your gate driver look like? Maybe you just need better decoupling.This looks pretty good: https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1 If I change one dc/dc converter, I can make the -10 into -24, which makes things nicer. R1+R2 can get bigger, which helps when they have to go from 5 to 500 volts across them.
Reply by ●September 27, 20232023-09-27
On 27/09/2023 15:55, John Larkin wrote:> On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs > <bloggs.fredbloggs.fred@gmail.com> wrote: > >> On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote: >>> Does anyone know anything about the effects of negaive-voltage >>> zenering the gate of a SiC power fet? >>> >>> Specifically, I'm designing a gate driver for the Cree C2M0280120D and >>> I'm wondering about what might happen in the rare case that I zener >>> the gate by a mA or so. The intent is to drive it -5 to +15, but the >>> -5 could be more in some pathological case. >>> >>> I'll get some from stock later and test some, but that's necessarily >>> short-term. I have seen long-term changes in some Gan parts from >>> abusing the gate a bit. >>> >>> googling hasn't helped. >> >> What does your gate driver look like? Maybe you just need better decoupling. > > This looks pretty good: > > https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1 > > If I change one dc/dc converter, I can make the -10 into -24, which > makes things nicer. R1+R2 can get bigger, which helps when they have > to go from 5 to 500 volts across them. > > > >Or use BSS126 / LND150 as pulldowns? piglet
Reply by ●September 27, 20232023-09-27
On Wednesday, September 27, 2023 at 10:56:15 AM UTC-4, John Larkin wrote:> On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs > <bloggs.fred...@gmail.com> wrote: > >On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote: > >> Does anyone know anything about the effects of negaive-voltage > >> zenering the gate of a SiC power fet? > >> > >> Specifically, I'm designing a gate driver for the Cree C2M0280120D and > >> I'm wondering about what might happen in the rare case that I zener > >> the gate by a mA or so. The intent is to drive it -5 to +15, but the > >> -5 could be more in some pathological case. > >> > >> I'll get some from stock later and test some, but that's necessarily > >> short-term. I have seen long-term changes in some Gan parts from > >> abusing the gate a bit. > >> > >> googling hasn't helped. > > > >What does your gate driver look like? Maybe you just need better decoupling. > This looks pretty good: > > https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1 > > If I change one dc/dc converter, I can make the -10 into -24, which > makes things nicer. R1+R2 can get bigger, which helps when they have > to go from 5 to 500 volts across them.Generally speaking, larger resistance makes for more damping irrespective of amplitudes, and you can go through the time constant modeling jazz, but pulling to a lower voltage via a resistor speeds up the fall time. That UCC5120 is powerful. I'm surprised the 4040 can take the abuse. Have no idea how much gate charge those SiC's take though.
Reply by ●September 27, 20232023-09-27
On 27/09/2023 17:27, Fred Bloggs wrote:> On Wednesday, September 27, 2023 at 10:56:15 AM UTC-4, John Larkin wrote: >> On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs >> <bloggs.fred...@gmail.com> wrote: >>> On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote: >>>> Does anyone know anything about the effects of negaive-voltage >>>> zenering the gate of a SiC power fet? >>>> >>>> Specifically, I'm designing a gate driver for the Cree C2M0280120D and >>>> I'm wondering about what might happen in the rare case that I zener >>>> the gate by a mA or so. The intent is to drive it -5 to +15, but the >>>> -5 could be more in some pathological case. >>>> >>>> I'll get some from stock later and test some, but that's necessarily >>>> short-term. I have seen long-term changes in some Gan parts from >>>> abusing the gate a bit. >>>> >>>> googling hasn't helped. >>> >>> What does your gate driver look like? Maybe you just need better decoupling. >> This looks pretty good: >> >> https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1 >> >> If I change one dc/dc converter, I can make the -10 into -24, which >> makes things nicer. R1+R2 can get bigger, which helps when they have >> to go from 5 to 500 volts across them. > > Generally speaking, larger resistance makes for more damping irrespective of amplitudes, and you can go through the time constant modeling jazz, but pulling to a lower voltage via a resistor speeds up the fall time. > > That UCC5120 is powerful. I'm surprised the 4040 can take the abuse. Have no idea how much gate charge those SiC's take though.What (?little) abuse there might be will most likely be borne by the 1uF rather than the LM4040? piglet
Reply by ●September 27, 20232023-09-27
On Wed, 27 Sep 2023 16:43:38 +0100, Piglet <erichpwagner@hotmail.com> wrote:>On 27/09/2023 15:55, John Larkin wrote: >> On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs >> <bloggs.fredbloggs.fred@gmail.com> wrote: >> >>> On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote: >>>> Does anyone know anything about the effects of negaive-voltage >>>> zenering the gate of a SiC power fet? >>>> >>>> Specifically, I'm designing a gate driver for the Cree C2M0280120D and >>>> I'm wondering about what might happen in the rare case that I zener >>>> the gate by a mA or so. The intent is to drive it -5 to +15, but the >>>> -5 could be more in some pathological case. >>>> >>>> I'll get some from stock later and test some, but that's necessarily >>>> short-term. I have seen long-term changes in some Gan parts from >>>> abusing the gate a bit. >>>> >>>> googling hasn't helped. >>> >>> What does your gate driver look like? Maybe you just need better decoupling. >> >> This looks pretty good: >> >> https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1 >> >> If I change one dc/dc converter, I can make the -10 into -24, which >> makes things nicer. R1+R2 can get bigger, which helps when they have >> to go from 5 to 500 volts across them. >> >> >> >> > >Or use BSS126 / LND150 as pulldowns? > >pigletYes, I use LND150 a lot, but two resistors is easy with no dynamic concerns. The Cree fet has pA DC gate currents over its specified gate voltage range. pA drain current, too, at zero gate bias! So I only need 60 uA to keep the 4040 alive.
Reply by ●September 27, 20232023-09-27
On Wed, 27 Sep 2023 09:27:08 -0700 (PDT), Fred Bloggs <bloggs.fredbloggs.fred@gmail.com> wrote:>On Wednesday, September 27, 2023 at 10:56:15?AM UTC-4, John Larkin wrote: >> On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs >> <bloggs.fred...@gmail.com> wrote: >> >On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote: >> >> Does anyone know anything about the effects of negaive-voltage >> >> zenering the gate of a SiC power fet? >> >> >> >> Specifically, I'm designing a gate driver for the Cree C2M0280120D and >> >> I'm wondering about what might happen in the rare case that I zener >> >> the gate by a mA or so. The intent is to drive it -5 to +15, but the >> >> -5 could be more in some pathological case. >> >> >> >> I'll get some from stock later and test some, but that's necessarily >> >> short-term. I have seen long-term changes in some Gan parts from >> >> abusing the gate a bit. >> >> >> >> googling hasn't helped. >> > >> >What does your gate driver look like? Maybe you just need better decoupling. >> This looks pretty good: >> >> https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1 >> >> If I change one dc/dc converter, I can make the -10 into -24, which >> makes things nicer. R1+R2 can get bigger, which helps when they have >> to go from 5 to 500 volts across them. > >Generally speaking, larger resistance makes for more damping irrespective of amplitudes, and you can go through the time constant modeling jazz, but pulling to a lower voltage via a resistor speeds up the fall time.Fall time comes from the amps of drive from the TI chip. The resistive pulldown can be a hundred uA or so.> >That UCC5120 is powerful. I'm surprised the 4040 can take the abuse. Have no idea how much gate charge those SiC's take though.The 4040 will only see the tiny DC bias current.
