>On Tuesday, September 26, 2023 at 9:53:44?AM UTC-7, John Larkin wrote:
>> On Tue, 26 Sep 2023 09:15:13 -0700, boB <b...@K7IQ.com> wrote:
>>
>> >On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <j...@997PotHill.com>
>> >wrote:
>> >
>> >>Does anyone know anything about the effects of negaive-voltage
>> >>zenering the gate of a SiC power fet?
>> >>
>> >>Specifically, I'm designing a gate driver for the Cree C2M0280120D and
>> >>I'm wondering about what might happen in the rare case that I zener
>> >>the gate by a mA or so. The intent is to drive it -5 to +15, but the
>> >>-5 could be more in some pathological case.
>> >>
>> >>I'll get some from stock later and test some, but that's necessarily
>> >>short-term. I have seen long-term changes in some Gan parts from
>> >>abusing the gate a bit.
>> >>
>> >>googling hasn't helped.
>> >
>> >
>> >I have experience with Rohm SiC FETs. These were -4V maximum negative
>> >voltage for those gen 3 (I think) parts.
>> >
>> >They do NOT like being over-biased negatively. I think everybody's
>> >SiC FETs don't like too much negative voltage.
>> >
>> >I remember that they start acting very strangely when too much
>> >negative voltage is applied. Even for very short times.
>> >
>> >My solution was to use miller clamps. Whatever you do, you need to
>> >check very closely what that Vgs is doing.
>> >
>> >boB
>> >
>> Right. I want to run the Cree gates at +15 and -5, and the upper fet
>> source pulses to +500, so I have to be careful that there is no case
>> where I over-voltage the gate in either direction. I want speed, and
>> zeners have a lot of capacitance, so a simple dual zener clamp is not
>> for consideration.
>>
>> SiC fets are hard to drive but otherwise great.
>
>A non-simple zener clamp would bias the zeners and use switch diodes
>to those (the switch diode having presumably lower capacitance).
>Switch diodes have low cost, both money and capacitance.
The series LM4040 is paralleled with a capacitor, so its capacitance
doesn't matter.
Reply by whit3rd●September 27, 20232023-09-27
On Tuesday, September 26, 2023 at 9:53:44 AM UTC-7, John Larkin wrote:
> On Tue, 26 Sep 2023 09:15:13 -0700, boB <b...@K7IQ.com> wrote:
>
> >On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <j...@997PotHill.com>
> >wrote:
> >
> >>Does anyone know anything about the effects of negaive-voltage
> >>zenering the gate of a SiC power fet?
> >>
> >>Specifically, I'm designing a gate driver for the Cree C2M0280120D and
> >>I'm wondering about what might happen in the rare case that I zener
> >>the gate by a mA or so. The intent is to drive it -5 to +15, but the
> >>-5 could be more in some pathological case.
> >>
> >>I'll get some from stock later and test some, but that's necessarily
> >>short-term. I have seen long-term changes in some Gan parts from
> >>abusing the gate a bit.
> >>
> >>googling hasn't helped.
> >
> >
> >I have experience with Rohm SiC FETs. These were -4V maximum negative
> >voltage for those gen 3 (I think) parts.
> >
> >They do NOT like being over-biased negatively. I think everybody's
> >SiC FETs don't like too much negative voltage.
> >
> >I remember that they start acting very strangely when too much
> >negative voltage is applied. Even for very short times.
> >
> >My solution was to use miller clamps. Whatever you do, you need to
> >check very closely what that Vgs is doing.
> >
> >boB
> >
> Right. I want to run the Cree gates at +15 and -5, and the upper fet
> source pulses to +500, so I have to be careful that there is no case
> where I over-voltage the gate in either direction. I want speed, and
> zeners have a lot of capacitance, so a simple dual zener clamp is not
> for consideration.
>
> SiC fets are hard to drive but otherwise great.
A non-simple zener clamp would bias the zeners and use switch diodes
to those (the switch diode having presumably lower capacitance).
Switch diodes have low cost, both money and capacitance.
Reply by John Larkin●September 27, 20232023-09-27
On Wed, 27 Sep 2023 09:27:08 -0700 (PDT), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:
>On Wednesday, September 27, 2023 at 10:56:15?AM UTC-4, John Larkin wrote:
>> On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs
>> <bloggs.fred...@gmail.com> wrote:
>> >On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
>> >> Does anyone know anything about the effects of negaive-voltage
>> >> zenering the gate of a SiC power fet?
>> >>
>> >> Specifically, I'm designing a gate driver for the Cree C2M0280120D and
>> >> I'm wondering about what might happen in the rare case that I zener
>> >> the gate by a mA or so. The intent is to drive it -5 to +15, but the
>> >> -5 could be more in some pathological case.
>> >>
>> >> I'll get some from stock later and test some, but that's necessarily
>> >> short-term. I have seen long-term changes in some Gan parts from
>> >> abusing the gate a bit.
>> >>
>> >> googling hasn't helped.
>> >
>> >What does your gate driver look like? Maybe you just need better decoupling.
>> This looks pretty good:
>>
>> https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1
>>
>> If I change one dc/dc converter, I can make the -10 into -24, which
>> makes things nicer. R1+R2 can get bigger, which helps when they have
>> to go from 5 to 500 volts across them.
>
>Generally speaking, larger resistance makes for more damping irrespective of amplitudes, and you can go through the time constant modeling jazz, but pulling to a lower voltage via a resistor speeds up the fall time.
Fall time comes from the amps of drive from the TI chip. The resistive
pulldown can be a hundred uA or so.
>
>That UCC5120 is powerful. I'm surprised the 4040 can take the abuse. Have no idea how much gate charge those SiC's take though.
The 4040 will only see the tiny DC bias current.
Reply by John Larkin●September 27, 20232023-09-27
On Wed, 27 Sep 2023 16:43:38 +0100, Piglet <erichpwagner@hotmail.com>
wrote:
>On 27/09/2023 15:55, John Larkin wrote:
>> On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs
>> <bloggs.fredbloggs.fred@gmail.com> wrote:
>>
>>> On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
>>>> Does anyone know anything about the effects of negaive-voltage
>>>> zenering the gate of a SiC power fet?
>>>>
>>>> Specifically, I'm designing a gate driver for the Cree C2M0280120D and
>>>> I'm wondering about what might happen in the rare case that I zener
>>>> the gate by a mA or so. The intent is to drive it -5 to +15, but the
>>>> -5 could be more in some pathological case.
>>>>
>>>> I'll get some from stock later and test some, but that's necessarily
>>>> short-term. I have seen long-term changes in some Gan parts from
>>>> abusing the gate a bit.
>>>>
>>>> googling hasn't helped.
>>>
>>> What does your gate driver look like? Maybe you just need better decoupling.
>>
>> This looks pretty good:
>>
>> https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1
>>
>> If I change one dc/dc converter, I can make the -10 into -24, which
>> makes things nicer. R1+R2 can get bigger, which helps when they have
>> to go from 5 to 500 volts across them.
>>
>>
>>
>>
>
>Or use BSS126 / LND150 as pulldowns?
>
>piglet
Yes, I use LND150 a lot, but two resistors is easy with no dynamic
concerns.
The Cree fet has pA DC gate currents over its specified gate voltage
range. pA drain current, too, at zero gate bias! So I only need 60 uA
to keep the 4040 alive.
Reply by Piglet●September 27, 20232023-09-27
On 27/09/2023 17:27, Fred Bloggs wrote:
> On Wednesday, September 27, 2023 at 10:56:15 AM UTC-4, John Larkin wrote:
>> On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs
>> <bloggs.fred...@gmail.com> wrote:
>>> On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
>>>> Does anyone know anything about the effects of negaive-voltage
>>>> zenering the gate of a SiC power fet?
>>>>
>>>> Specifically, I'm designing a gate driver for the Cree C2M0280120D and
>>>> I'm wondering about what might happen in the rare case that I zener
>>>> the gate by a mA or so. The intent is to drive it -5 to +15, but the
>>>> -5 could be more in some pathological case.
>>>>
>>>> I'll get some from stock later and test some, but that's necessarily
>>>> short-term. I have seen long-term changes in some Gan parts from
>>>> abusing the gate a bit.
>>>>
>>>> googling hasn't helped.
>>>
>>> What does your gate driver look like? Maybe you just need better decoupling.
>> This looks pretty good:
>>
>> https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1
>>
>> If I change one dc/dc converter, I can make the -10 into -24, which
>> makes things nicer. R1+R2 can get bigger, which helps when they have
>> to go from 5 to 500 volts across them.
>
> Generally speaking, larger resistance makes for more damping irrespective of amplitudes, and you can go through the time constant modeling jazz, but pulling to a lower voltage via a resistor speeds up the fall time.
>
> That UCC5120 is powerful. I'm surprised the 4040 can take the abuse. Have no idea how much gate charge those SiC's take though.
What (?little) abuse there might be will most likely be borne by the 1uF
rather than the LM4040?
piglet
Reply by Fred Bloggs●September 27, 20232023-09-27
On Wednesday, September 27, 2023 at 10:56:15 AM UTC-4, John Larkin wrote:
> On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs
> <bloggs.fred...@gmail.com> wrote:
> >On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
> >> Does anyone know anything about the effects of negaive-voltage
> >> zenering the gate of a SiC power fet?
> >>
> >> Specifically, I'm designing a gate driver for the Cree C2M0280120D and
> >> I'm wondering about what might happen in the rare case that I zener
> >> the gate by a mA or so. The intent is to drive it -5 to +15, but the
> >> -5 could be more in some pathological case.
> >>
> >> I'll get some from stock later and test some, but that's necessarily
> >> short-term. I have seen long-term changes in some Gan parts from
> >> abusing the gate a bit.
> >>
> >> googling hasn't helped.
> >
> >What does your gate driver look like? Maybe you just need better decoupling.
> This looks pretty good:
>
> https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1
>
> If I change one dc/dc converter, I can make the -10 into -24, which
> makes things nicer. R1+R2 can get bigger, which helps when they have
> to go from 5 to 500 volts across them.
Generally speaking, larger resistance makes for more damping irrespective of amplitudes, and you can go through the time constant modeling jazz, but pulling to a lower voltage via a resistor speeds up the fall time.
That UCC5120 is powerful. I'm surprised the 4040 can take the abuse. Have no idea how much gate charge those SiC's take though.
Reply by Piglet●September 27, 20232023-09-27
On 27/09/2023 15:55, John Larkin wrote:
> On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs
> <bloggs.fredbloggs.fred@gmail.com> wrote:
>
>> On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
>>> Does anyone know anything about the effects of negaive-voltage
>>> zenering the gate of a SiC power fet?
>>>
>>> Specifically, I'm designing a gate driver for the Cree C2M0280120D and
>>> I'm wondering about what might happen in the rare case that I zener
>>> the gate by a mA or so. The intent is to drive it -5 to +15, but the
>>> -5 could be more in some pathological case.
>>>
>>> I'll get some from stock later and test some, but that's necessarily
>>> short-term. I have seen long-term changes in some Gan parts from
>>> abusing the gate a bit.
>>>
>>> googling hasn't helped.
>>
>> What does your gate driver look like? Maybe you just need better decoupling.
>
> This looks pretty good:
>
> https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1
>
> If I change one dc/dc converter, I can make the -10 into -24, which
> makes things nicer. R1+R2 can get bigger, which helps when they have
> to go from 5 to 500 volts across them.
>
>
>
>
Or use BSS126 / LND150 as pulldowns?
piglet
Reply by John Larkin●September 27, 20232023-09-27
On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:
>On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
>> Does anyone know anything about the effects of negaive-voltage
>> zenering the gate of a SiC power fet?
>>
>> Specifically, I'm designing a gate driver for the Cree C2M0280120D and
>> I'm wondering about what might happen in the rare case that I zener
>> the gate by a mA or so. The intent is to drive it -5 to +15, but the
>> -5 could be more in some pathological case.
>>
>> I'll get some from stock later and test some, but that's necessarily
>> short-term. I have seen long-term changes in some Gan parts from
>> abusing the gate a bit.
>>
>> googling hasn't helped.
>
>What does your gate driver look like? Maybe you just need better decoupling.
On Monday, September 25, 2023 at 1:07:25 PM UTC-4, John Larkin wrote:
> Does anyone know anything about the effects of negaive-voltage
> zenering the gate of a SiC power fet?
>
> Specifically, I'm designing a gate driver for the Cree C2M0280120D and
> I'm wondering about what might happen in the rare case that I zener
> the gate by a mA or so. The intent is to drive it -5 to +15, but the
> -5 could be more in some pathological case.
>
> I'll get some from stock later and test some, but that's necessarily
> short-term. I have seen long-term changes in some Gan parts from
> abusing the gate a bit.
>
> googling hasn't helped.
What does your gate driver look like? Maybe you just need better decoupling.
Reply by Fred Bloggs●September 27, 20232023-09-27
On Monday, September 25, 2023 at 1:07:25 PM UTC-4, John Larkin wrote:
> Does anyone know anything about the effects of negaive-voltage
> zenering the gate of a SiC power fet?
>
> Specifically, I'm designing a gate driver for the Cree C2M0280120D and
> I'm wondering about what might happen in the rare case that I zener
> the gate by a mA or so. The intent is to drive it -5 to +15, but the
> -5 could be more in some pathological case.
>
> I'll get some from stock later and test some, but that's necessarily
> short-term. I have seen long-term changes in some Gan parts from
> abusing the gate a bit.
>
> googling hasn't helped.
Use another SiC to clamp that gate drive to a safe level.