Does anyone know anything about the effects of negaive-voltage zenering the gate of a SiC power fet? Specifically, I'm designing a gate driver for the Cree C2M0280120D and I'm wondering about what might happen in the rare case that I zener the gate by a mA or so. The intent is to drive it -5 to +15, but the -5 could be more in some pathological case. I'll get some from stock later and test some, but that's necessarily short-term. I have seen long-term changes in some Gan parts from abusing the gate a bit. googling hasn't helped.
SiC fet gate damage
Started by ●September 25, 2023
Reply by ●September 25, 20232023-09-25
John Larkin <jl@997PotHill.com> wrote:> Does anyone know anything about the effects of negaive-voltage > zenering the gate of a SiC power fet? > > Specifically, I'm designing a gate driver for the Cree C2M0280120D and > I'm wondering about what might happen in the rare case that I zener > the gate by a mA or so. The intent is to drive it -5 to +15, but the > -5 could be more in some pathological case. > > I'll get some from stock later and test some, but that's necessarily > short-term. I have seen long-term changes in some Gan parts from > abusing the gate a bit. > > googling hasn't helped. > >I have an app note from EPC that says that the gates are pretty delicate. Since the gate is in contact with the 2DEG, I’d expect it to be very vulnerable to hot-carrier damage. I’ll try to dig out the app note. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics
Reply by ●September 25, 20232023-09-25
Reply by ●September 25, 20232023-09-25
On Mon, 25 Sep 2023 20:02:38 -0000 (UTC), Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>John Larkin <jl@997PotHill.com> wrote: >> Does anyone know anything about the effects of negaive-voltage >> zenering the gate of a SiC power fet? >> >> Specifically, I'm designing a gate driver for the Cree C2M0280120D and >> I'm wondering about what might happen in the rare case that I zener >> the gate by a mA or so. The intent is to drive it -5 to +15, but the >> -5 could be more in some pathological case. >> >> I'll get some from stock later and test some, but that's necessarily >> short-term. I have seen long-term changes in some Gan parts from >> abusing the gate a bit. >> >> googling hasn't helped. >> >> > >I have an app note from EPC that says that the gates are pretty delicate. >Since the gate is in contact with the 2DEG, I�d expect it to be very >vulnerable to hot-carrier damage. > >I�ll try to dig out the app note. > >Cheers > >Phil HobbsI don't have a lot of these handy so I don't want to fry many. A quick test was to apply -v to the gate through 10K. Up to -30 volts, leakage was tiny, sub-uA probably. About -40, it started clipping. At around 1 mA, it died hard. I'm considering a UCC21520 half-bridge driver, but these SiC things like negative gate bias, -5 maybe, so I need to add some offset, but never too much. Series zener and some sort of pulldown is safe. The high side fet source will swing to +500!
Reply by ●September 25, 20232023-09-25
On Mon, 25 Sep 2023 20:02:38 -0000 (UTC), Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>John Larkin <jl@997PotHill.com> wrote: >> Does anyone know anything about the effects of negaive-voltage >> zenering the gate of a SiC power fet? >> >> Specifically, I'm designing a gate driver for the Cree C2M0280120D and >> I'm wondering about what might happen in the rare case that I zener >> the gate by a mA or so. The intent is to drive it -5 to +15, but the >> -5 could be more in some pathological case. >> >> I'll get some from stock later and test some, but that's necessarily >> short-term. I have seen long-term changes in some Gan parts from >> abusing the gate a bit. >> >> googling hasn't helped. >> >> > >I have an app note from EPC that says that the gates are pretty delicate. >Since the gate is in contact with the 2DEG, I�d expect it to be very >vulnerable to hot-carrier damage. > >I�ll try to dig out the app note. > >Cheers > >Phil HobbsThis should work: https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1 The LM4040 only needs 60 uA, and duty cycle will be low, so we probably won't fry R1+R2 when they have 500 volts across them. R1/R2 could be a bit bigger. I was thinking about a fancy depletion fet for the pulldown, but resistors should work. Those half-bridge drivers are amazing. That one has 5.7 KV isolation. Can that be one chip?
Reply by ●September 26, 20232023-09-26
On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <jl@997PotHill.com> wrote:>Does anyone know anything about the effects of negaive-voltage >zenering the gate of a SiC power fet? > >Specifically, I'm designing a gate driver for the Cree C2M0280120D and >I'm wondering about what might happen in the rare case that I zener >the gate by a mA or so. The intent is to drive it -5 to +15, but the >-5 could be more in some pathological case. > >I'll get some from stock later and test some, but that's necessarily >short-term. I have seen long-term changes in some Gan parts from >abusing the gate a bit. > >googling hasn't helped.I have experience with Rohm SiC FETs. These were -4V maximum negative voltage for those gen 3 (I think) parts. They do NOT like being over-biased negatively. I think everybody's SiC FETs don't like too much negative voltage. I remember that they start acting very strangely when too much negative voltage is applied. Even for very short times. My solution was to use miller clamps. Whatever you do, you need to check very closely what that Vgs is doing. boB
Reply by ●September 26, 20232023-09-26
On Tue, 26 Sep 2023 09:15:13 -0700, boB <boB@K7IQ.com> wrote:>On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <jl@997PotHill.com> >wrote: > >>Does anyone know anything about the effects of negaive-voltage >>zenering the gate of a SiC power fet? >> >>Specifically, I'm designing a gate driver for the Cree C2M0280120D and >>I'm wondering about what might happen in the rare case that I zener >>the gate by a mA or so. The intent is to drive it -5 to +15, but the >>-5 could be more in some pathological case. >> >>I'll get some from stock later and test some, but that's necessarily >>short-term. I have seen long-term changes in some Gan parts from >>abusing the gate a bit. >> >>googling hasn't helped. > > >I have experience with Rohm SiC FETs. These were -4V maximum negative >voltage for those gen 3 (I think) parts. > >They do NOT like being over-biased negatively. I think everybody's >SiC FETs don't like too much negative voltage. > >I remember that they start acting very strangely when too much >negative voltage is applied. Even for very short times. > >My solution was to use miller clamps. Whatever you do, you need to >check very closely what that Vgs is doing. > >boB >Right. I want to run the Cree gates at +15 and -5, and the upper fet source pulses to +500, so I have to be careful that there is no case where I over-voltage the gate in either direction. I want speed, and zeners have a lot of capacitance, so a simple dual zener clamp is not for consideration. SiC fets are hard to drive but otherwise great.
Reply by ●September 26, 20232023-09-26
tirsdag den 26. september 2023 kl. 18.53.44 UTC+2 skrev John Larkin:> On Tue, 26 Sep 2023 09:15:13 -0700, boB <b...@K7IQ.com> wrote: > > >On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <j...@997PotHill.com> > >wrote: > > > >>Does anyone know anything about the effects of negaive-voltage > >>zenering the gate of a SiC power fet? > >> > >>Specifically, I'm designing a gate driver for the Cree C2M0280120D and > >>I'm wondering about what might happen in the rare case that I zener > >>the gate by a mA or so. The intent is to drive it -5 to +15, but the > >>-5 could be more in some pathological case. > >> > >>I'll get some from stock later and test some, but that's necessarily > >>short-term. I have seen long-term changes in some Gan parts from > >>abusing the gate a bit. > >> > >>googling hasn't helped. > > > > > >I have experience with Rohm SiC FETs. These were -4V maximum negative > >voltage for those gen 3 (I think) parts. > > > >They do NOT like being over-biased negatively. I think everybody's > >SiC FETs don't like too much negative voltage. > > > >I remember that they start acting very strangely when too much > >negative voltage is applied. Even for very short times. > > > >My solution was to use miller clamps. Whatever you do, you need to > >check very closely what that Vgs is doing. > > > >boB > > > Right. I want to run the Cree gates at +15 and -5, and the upper fet > source pulses to +500, so I have to be careful that there is no case > where I over-voltage the gate in either direction. I want speed, and > zeners have a lot of capacitance, so a simple dual zener clamp is not > for consideration.plenty with <1pf and ~5Vbr , https://www.onsemi.com/products/discrete-power-modules/esd-protection-diodes
Reply by ●September 26, 20232023-09-26
On Tuesday, September 26, 2023 at 1:13:50 PM UTC-5, Lasse Langwadt Christensen wrote:> tirsdag den 26. september 2023 kl. 18.53.44 UTC+2 skrev John Larkin: > > On Tue, 26 Sep 2023 09:15:13 -0700, boB <b...@K7IQ.com> wrote: > > > > >On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <j...@997PotHill.com> > > >wrote: > > > > > >>Does anyone know anything about the effects of negaive-voltage > > >>zenering the gate of a SiC power fet? > > >> > > >>Specifically, I'm designing a gate driver for the Cree C2M0280120D and > > >>I'm wondering about what might happen in the rare case that I zener > > >>the gate by a mA or so. The intent is to drive it -5 to +15, but the > > >>-5 could be more in some pathological case. > > >> > > >>I'll get some from stock later and test some, but that's necessarily > > >>short-term. I have seen long-term changes in some Gan parts from > > >>abusing the gate a bit. > > >> > > >>googling hasn't helped. > > > > > > > > >I have experience with Rohm SiC FETs. These were -4V maximum negative > > >voltage for those gen 3 (I think) parts. > > > > > >They do NOT like being over-biased negatively. I think everybody's > > >SiC FETs don't like too much negative voltage. > > > > > >I remember that they start acting very strangely when too much > > >negative voltage is applied. Even for very short times. > > > > > >My solution was to use miller clamps. Whatever you do, you need to > > >check very closely what that Vgs is doing. > > > > > >boB > > > > > Right. I want to run the Cree gates at +15 and -5, and the upper fet > > source pulses to +500, so I have to be careful that there is no case > > where I over-voltage the gate in either direction. I want speed, and > > zeners have a lot of capacitance, so a simple dual zener clamp is not > > for consideration. > plenty with <1pf and ~5Vbr , https://www.onsemi.com/products/discrete-power-modules/esd-protection-diodesThanks, Lasse, for the great link. Much appreciated. John
Reply by ●September 26, 20232023-09-26
On Tue, 26 Sep 2023 11:13:45 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>tirsdag den 26. september 2023 kl. 18.53.44 UTC+2 skrev John Larkin: >> On Tue, 26 Sep 2023 09:15:13 -0700, boB <b...@K7IQ.com> wrote: >> >> >On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <j...@997PotHill.com> >> >wrote: >> > >> >>Does anyone know anything about the effects of negaive-voltage >> >>zenering the gate of a SiC power fet? >> >> >> >>Specifically, I'm designing a gate driver for the Cree C2M0280120D and >> >>I'm wondering about what might happen in the rare case that I zener >> >>the gate by a mA or so. The intent is to drive it -5 to +15, but the >> >>-5 could be more in some pathological case. >> >> >> >>I'll get some from stock later and test some, but that's necessarily >> >>short-term. I have seen long-term changes in some Gan parts from >> >>abusing the gate a bit. >> >> >> >>googling hasn't helped. >> > >> > >> >I have experience with Rohm SiC FETs. These were -4V maximum negative >> >voltage for those gen 3 (I think) parts. >> > >> >They do NOT like being over-biased negatively. I think everybody's >> >SiC FETs don't like too much negative voltage. >> > >> >I remember that they start acting very strangely when too much >> >negative voltage is applied. Even for very short times. >> > >> >My solution was to use miller clamps. Whatever you do, you need to >> >check very closely what that Vgs is doing. >> > >> >boB >> > >> Right. I want to run the Cree gates at +15 and -5, and the upper fet >> source pulses to +500, so I have to be careful that there is no case >> where I over-voltage the gate in either direction. I want speed, and >> zeners have a lot of capacitance, so a simple dual zener clamp is not >> for consideration. > >plenty with <1pf and ~5Vbr , https://www.onsemi.com/products/discrete-power-modules/esd-protection-diodes >The thing I posted above https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1 looks safe. I can make the -10 into -24, which helps.
