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Microcontroller decoupling, >1uF rules?

Started by Klaus Vestergaard Kragelund October 19, 2021
On 20/10/2021 04.37, jlarkin@highlandsniptechnology.com wrote:
> On Wed, 20 Oct 2021 01:40:15 +0200, Klaus Vestergaard Kragelund > <klauskvik@hotmail.com> wrote: > >> Hi >> >> Something that I have been coming back to a number of times: >> >> When placing capacitors for decoupling of a microcontroller datasheets >> often suggest a 1nF/100nF and maybe a number of them >> >> But it needs to be aligned to what is actually the load. >> >> Say I have a microcontroller running at 100MHz. Assumption (and that >> could be wrong), is that for the given technology the switching of the >> transistors are 10 times as fast, so 1ns >> >> If the micro runs at 100mA during active state (all peripherals and core >> running), and it then runs a SLEEP instruction, it immediately reduces >> the current from 100mA to 0 in 1ns, right? >> >> If it is operated at 3.3V, using standard 2.2uF cap: >> >> (Murata, 10V, X7R) >> >> GCM21BR71A225KA37K >> >> https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 >> >> Frequency content at 1ns is 350MHz, For the above capacitor the >> impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV >> transient voltage (plus a lot of ringing due to inductance not included) >> >> I would allow for a 100mV voltage transient during that load shift, so >> it seems this single 2.2uF cap would be enough >> >> >> A discussion of the topic here: >> >> https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from >> >> >> Specifically about the capacitors of today, with same package size plot >> comparison: >> >> https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html >> >> (figure 1) >> >> https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 >> > > That usual family of curves is mostly silly. > >> From that plot it makes no sense talking about a lot of different caps >> in parallel. One single 2.2uF rules? > > Except for vias. The usual capacitor VNA fixture doesn't model a PCB > very well. Simulations don't either. > >> >> Adding to this, I have a PCB with about 10.000 mm2 area, where I can >> place a VCC and GND plane. If uninterrupted 100um distance between the >> planes I get 5nF of very good HF capacitor with 0.1ohm impedance at >> 350MHz. Again, not need for smaller caps in the design >> >> On top of this the 100mA load in 1ns is probably a worst case situation. >> During normal operation the microcontroller is running, and not all >> transistors are switching at the same time >> >> Above constrained case does not take the switching capacitance of the >> microcontroller transistors into account. >> >> Any inputs to the above? >> >> Have anybody tried to measure the real life load of a microcontroller? >> >> Regards >> >> Klaus > > > We usually do a ground layer and various power pours on adjacent > layers, and seed that with 1 uF caps most anywhere. That always works > fine with uPs and FPGAs. > > I've TDR'd those structures and see no plane resonances. Sometimes a > tiny hint of edge reflections. Qs are low. > > Agree, the planes themselves are the best HF caps. > > Lots of big FPGAs have substantial (as in 1 uF) on-die capacitance, so > external bypassing is just for any slow stuff. I've tested some NXP > Arms that seem to have none. > > I'm doing some 10 GHz wideband precision analog stuff now, so I do use > a lot of 1 uF 0306 caps right at the IC pins with big copper ground > pours just outside, all on layer 1. > > >
The device I am looking at, just for example, is the STM32F750V8 https://www.st.com/resource/en/datasheet/stm32f750v8.pdf It actually has a seperate core voltage, so transients from the core switching is isolated with an internal LDO. The LDO seems to be decoupled with 2x 2.2uF. There is an option to run the core directly (page 28 of the datasheet), at 1.2V So it seems a instruction sleep won't be passed with the 1ns transient, but be smoothed out of the 2x2.2uF and the series regulator. As others suggested, then the direct loading of CPU IO pins are maybe more direct impact on the PDN system Regards Klaus
Klaus Vestergaard Kragelund wrote:
> Hi > > Something that I have been coming back to a number of times: > > When placing capacitors for decoupling of a microcontroller datasheets > often suggest a 1nF/100nF and maybe a number of them > > But it needs to be aligned to what is actually the load. > > Say I have a microcontroller running at 100MHz. Assumption (and that > could be wrong), is that for the given technology the switching of the > transistors are 10 times as fast, so 1ns > > If the micro runs at 100mA during active state (all peripherals and core > running), and it then runs a SLEEP instruction, it immediately reduces > the current from 100mA to 0 in 1ns, right? > > If it is operated at 3.3V, using standard 2.2uF cap: > > (Murata, 10V, X7R) > > GCM21BR71A225KA37K > > https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 > > > Frequency content at 1ns is 350MHz, For the above capacitor the > impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV > transient voltage (plus a lot of ringing due to inductance not included) > > I would allow for a 100mV voltage transient during that load shift, so > it seems this single 2.2uF cap would be enough > > > A discussion of the topic here: > > https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from > > > > Specifically about the capacitors of today, with same package size plot > comparison: > > https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html > > > (figure 1) > > https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 > > > From that plot it makes no sense talking about a lot of different caps > in parallel. One single 2.2uF rules? > > Adding to this, I have a PCB with about 10.000 mm2 area, where I can > place a VCC and GND plane. If uninterrupted 100um distance between the > planes I get 5nF of very good HF capacitor with 0.1ohm impedance at > 350MHz. Again, not need for smaller caps in the design > > On top of this the 100mA load in 1ns is probably a worst case situation. > During normal operation the microcontroller is running, and not all > transistors are switching at the same time > > Above constrained case does not take the switching capacitance of the > microcontroller transistors into account. > > Any inputs to the above? > > Have anybody tried to measure the real life load of a microcontroller? > > Regards > > Klaus
Supply network antiresonances (i.e. parallel resonances) do exist and can cause problems. The solution is to sprinkle some alpos around among the ceramics. They look like small resistances at the typical resonance frequencies, so they damp the antiresonances very effectively. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
On Thu, 21 Oct 2021 02:10:24 +0200, Klaus Vestergaard Kragelund
<klauskvik@hotmail.com> wrote:

>On 20/10/2021 04.37, jlarkin@highlandsniptechnology.com wrote: >> On Wed, 20 Oct 2021 01:40:15 +0200, Klaus Vestergaard Kragelund >> <klauskvik@hotmail.com> wrote: >> >>> Hi >>> >>> Something that I have been coming back to a number of times: >>> >>> When placing capacitors for decoupling of a microcontroller datasheets >>> often suggest a 1nF/100nF and maybe a number of them >>> >>> But it needs to be aligned to what is actually the load. >>> >>> Say I have a microcontroller running at 100MHz. Assumption (and that >>> could be wrong), is that for the given technology the switching of the >>> transistors are 10 times as fast, so 1ns >>> >>> If the micro runs at 100mA during active state (all peripherals and core >>> running), and it then runs a SLEEP instruction, it immediately reduces >>> the current from 100mA to 0 in 1ns, right? >>> >>> If it is operated at 3.3V, using standard 2.2uF cap: >>> >>> (Murata, 10V, X7R) >>> >>> GCM21BR71A225KA37K >>> >>> https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 >>> >>> Frequency content at 1ns is 350MHz, For the above capacitor the >>> impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV >>> transient voltage (plus a lot of ringing due to inductance not included) >>> >>> I would allow for a 100mV voltage transient during that load shift, so >>> it seems this single 2.2uF cap would be enough >>> >>> >>> A discussion of the topic here: >>> >>> https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from >>> >>> >>> Specifically about the capacitors of today, with same package size plot >>> comparison: >>> >>> https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html >>> >>> (figure 1) >>> >>> https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 >>> >> >> That usual family of curves is mostly silly. >> >>> From that plot it makes no sense talking about a lot of different caps >>> in parallel. One single 2.2uF rules? >> >> Except for vias. The usual capacitor VNA fixture doesn't model a PCB >> very well. Simulations don't either. >> >>> >>> Adding to this, I have a PCB with about 10.000 mm2 area, where I can >>> place a VCC and GND plane. If uninterrupted 100um distance between the >>> planes I get 5nF of very good HF capacitor with 0.1ohm impedance at >>> 350MHz. Again, not need for smaller caps in the design >>> >>> On top of this the 100mA load in 1ns is probably a worst case situation. >>> During normal operation the microcontroller is running, and not all >>> transistors are switching at the same time >>> >>> Above constrained case does not take the switching capacitance of the >>> microcontroller transistors into account. >>> >>> Any inputs to the above? >>> >>> Have anybody tried to measure the real life load of a microcontroller? >>> >>> Regards >>> >>> Klaus >> >> >> We usually do a ground layer and various power pours on adjacent >> layers, and seed that with 1 uF caps most anywhere. That always works >> fine with uPs and FPGAs. >> >> I've TDR'd those structures and see no plane resonances. Sometimes a >> tiny hint of edge reflections. Qs are low. >> >> Agree, the planes themselves are the best HF caps. >> >> Lots of big FPGAs have substantial (as in 1 uF) on-die capacitance, so >> external bypassing is just for any slow stuff. I've tested some NXP >> Arms that seem to have none. >> >> I'm doing some 10 GHz wideband precision analog stuff now, so I do use >> a lot of 1 uF 0306 caps right at the IC pins with big copper ground >> pours just outside, all on layer 1. >> >> >> > >The device I am looking at, just for example, is the STM32F750V8 > >https://www.st.com/resource/en/datasheet/stm32f750v8.pdf > >It actually has a seperate core voltage, so transients from the core >switching is isolated with an internal LDO. The LDO seems to be >decoupled with 2x 2.2uF. There is an option to run the core directly >(page 28 of the datasheet), at 1.2V
Those 2.2u caps seem to be external.
> >So it seems a instruction sleep won't be passed with the 1ns transient, >but be smoothed out of the 2x2.2uF and the series regulator. > >As others suggested, then the direct loading of CPU IO pins are maybe >more direct impact on the PDN system > >Regards > >Klaus
I wonder if it has any on-die power bypass capacitance. You could measure one and see. -- Father Brown's figure remained quite dark and still; but in that instant he had lost his head. His head was always most valuable when he had lost it.
On 21/10/2021 03.52, jlarkin@highlandsniptechnology.com wrote:
> On Thu, 21 Oct 2021 02:10:24 +0200, Klaus Vestergaard Kragelund > <klauskvik@hotmail.com> wrote: > >> On 20/10/2021 04.37, jlarkin@highlandsniptechnology.com wrote: >>> On Wed, 20 Oct 2021 01:40:15 +0200, Klaus Vestergaard Kragelund >>> <klauskvik@hotmail.com> wrote: >>> >>>> Hi >>>> >>>> Something that I have been coming back to a number of times: >>>> >>>> When placing capacitors for decoupling of a microcontroller datasheets >>>> often suggest a 1nF/100nF and maybe a number of them >>>> >>>> But it needs to be aligned to what is actually the load. >>>> >>>> Say I have a microcontroller running at 100MHz. Assumption (and that >>>> could be wrong), is that for the given technology the switching of the >>>> transistors are 10 times as fast, so 1ns >>>> >>>> If the micro runs at 100mA during active state (all peripherals and core >>>> running), and it then runs a SLEEP instruction, it immediately reduces >>>> the current from 100mA to 0 in 1ns, right? >>>> >>>> If it is operated at 3.3V, using standard 2.2uF cap: >>>> >>>> (Murata, 10V, X7R) >>>> >>>> GCM21BR71A225KA37K >>>> >>>> https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 >>>> >>>> Frequency content at 1ns is 350MHz, For the above capacitor the >>>> impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV >>>> transient voltage (plus a lot of ringing due to inductance not included) >>>> >>>> I would allow for a 100mV voltage transient during that load shift, so >>>> it seems this single 2.2uF cap would be enough >>>> >>>> >>>> A discussion of the topic here: >>>> >>>> https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from >>>> >>>> >>>> Specifically about the capacitors of today, with same package size plot >>>> comparison: >>>> >>>> https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html >>>> >>>> (figure 1) >>>> >>>> https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 >>>> >>> >>> That usual family of curves is mostly silly. >>> >>>> From that plot it makes no sense talking about a lot of different caps >>>> in parallel. One single 2.2uF rules? >>> >>> Except for vias. The usual capacitor VNA fixture doesn't model a PCB >>> very well. Simulations don't either. >>> >>>> >>>> Adding to this, I have a PCB with about 10.000 mm2 area, where I can >>>> place a VCC and GND plane. If uninterrupted 100um distance between the >>>> planes I get 5nF of very good HF capacitor with 0.1ohm impedance at >>>> 350MHz. Again, not need for smaller caps in the design >>>> >>>> On top of this the 100mA load in 1ns is probably a worst case situation. >>>> During normal operation the microcontroller is running, and not all >>>> transistors are switching at the same time >>>> >>>> Above constrained case does not take the switching capacitance of the >>>> microcontroller transistors into account. >>>> >>>> Any inputs to the above? >>>> >>>> Have anybody tried to measure the real life load of a microcontroller? >>>> >>>> Regards >>>> >>>> Klaus >>> >>> >>> We usually do a ground layer and various power pours on adjacent >>> layers, and seed that with 1 uF caps most anywhere. That always works >>> fine with uPs and FPGAs. >>> >>> I've TDR'd those structures and see no plane resonances. Sometimes a >>> tiny hint of edge reflections. Qs are low. >>> >>> Agree, the planes themselves are the best HF caps. >>> >>> Lots of big FPGAs have substantial (as in 1 uF) on-die capacitance, so >>> external bypassing is just for any slow stuff. I've tested some NXP >>> Arms that seem to have none. >>> >>> I'm doing some 10 GHz wideband precision analog stuff now, so I do use >>> a lot of 1 uF 0306 caps right at the IC pins with big copper ground >>> pours just outside, all on layer 1. >>> >>> >>> >> >> The device I am looking at, just for example, is the STM32F750V8 >> >> https://www.st.com/resource/en/datasheet/stm32f750v8.pdf >> >> It actually has a seperate core voltage, so transients from the core >> switching is isolated with an internal LDO. The LDO seems to be >> decoupled with 2x 2.2uF. There is an option to run the core directly >> (page 28 of the datasheet), at 1.2V > > Those 2.2u caps seem to be external. > >> >> So it seems a instruction sleep won't be passed with the 1ns transient, >> but be smoothed out of the 2x2.2uF and the series regulator. >> >> As others suggested, then the direct loading of CPU IO pins are maybe >> more direct impact on the PDN system >> >> Regards >> >> Klaus > > I wonder if it has any on-die power bypass capacitance. You could > measure one and see. >
For the small embedded controllers, they don't have embedded capacitors. I have seen the insides of one, only a chip
On 21/10/2021 02.54, Phil Hobbs wrote:
> Klaus Vestergaard Kragelund wrote: >> Hi >> >> Something that I have been coming back to a number of times: >> >> When placing capacitors for decoupling of a microcontroller datasheets >> often suggest a 1nF/100nF and maybe a number of them >> >> But it needs to be aligned to what is actually the load. >> >> Say I have a microcontroller running at 100MHz. Assumption (and that >> could be wrong), is that for the given technology the switching of the >> transistors are 10 times as fast, so 1ns >> >> If the micro runs at 100mA during active state (all peripherals and >> core running), and it then runs a SLEEP instruction, it immediately >> reduces the current from 100mA to 0 in 1ns, right? >> >> If it is operated at 3.3V, using standard 2.2uF cap: >> >> (Murata, 10V, X7R) >> >> GCM21BR71A225KA37K >> >> https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 >> >> >> Frequency content at 1ns is 350MHz, For the above capacitor the >> impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV >> transient voltage (plus a lot of ringing due to inductance not included) >> >> I would allow for a 100mV voltage transient during that load shift, so >> it seems this single 2.2uF cap would be enough >> >> >> A discussion of the topic here: >> >> https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from >> >> >> >> Specifically about the capacitors of today, with same package size >> plot comparison: >> >> https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html >> >> >> (figure 1) >> >> https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 >> >> >> &nbsp;From that plot it makes no sense talking about a lot of different >> caps in parallel. One single 2.2uF rules? >> >> Adding to this, I have a PCB with about 10.000 mm2 area, where I can >> place a VCC and GND plane. If uninterrupted 100um distance between the >> planes I get 5nF of very good HF capacitor with 0.1ohm impedance at >> 350MHz. Again, not need for smaller caps in the design >> >> On top of this the 100mA load in 1ns is probably a worst case >> situation. During normal operation the microcontroller is running, and >> not all transistors are switching at the same time >> >> Above constrained case does not take the switching capacitance of the >> microcontroller transistors into account. >> >> Any inputs to the above? >> >> Have anybody tried to measure the real life load of a microcontroller? >> >> Regards >> >> Klaus > > Supply network antiresonances (i.e. parallel resonances) do exist and > can cause problems.&nbsp; The solution is to sprinkle some alpos around among > the ceramics.&nbsp; They look like small resistances at the typical resonance > frequencies, so they damp the antiresonances very effectively. >
Bruce Archambeault has done a lot of work on this https://interferencetechnology.com/eliminating-the-myths-about-printed-circuit-board-powerground-plane-decoupling/ For applications below 500MHz, going from power oin directly to the plane with a via has best performance, and the capacitors can be spread out on the PCB if proper power planes are used
On Thu, 21 Oct 2021 17:36:24 +0200, Klaus Vestergaard Kragelund
<klauskvik@hotmail.com> wrote:

>On 21/10/2021 03.52, jlarkin@highlandsniptechnology.com wrote: >> On Thu, 21 Oct 2021 02:10:24 +0200, Klaus Vestergaard Kragelund >> <klauskvik@hotmail.com> wrote: >> >>> On 20/10/2021 04.37, jlarkin@highlandsniptechnology.com wrote: >>>> On Wed, 20 Oct 2021 01:40:15 +0200, Klaus Vestergaard Kragelund >>>> <klauskvik@hotmail.com> wrote: >>>> >>>>> Hi >>>>> >>>>> Something that I have been coming back to a number of times: >>>>> >>>>> When placing capacitors for decoupling of a microcontroller datasheets >>>>> often suggest a 1nF/100nF and maybe a number of them >>>>> >>>>> But it needs to be aligned to what is actually the load. >>>>> >>>>> Say I have a microcontroller running at 100MHz. Assumption (and that >>>>> could be wrong), is that for the given technology the switching of the >>>>> transistors are 10 times as fast, so 1ns >>>>> >>>>> If the micro runs at 100mA during active state (all peripherals and core >>>>> running), and it then runs a SLEEP instruction, it immediately reduces >>>>> the current from 100mA to 0 in 1ns, right? >>>>> >>>>> If it is operated at 3.3V, using standard 2.2uF cap: >>>>> >>>>> (Murata, 10V, X7R) >>>>> >>>>> GCM21BR71A225KA37K >>>>> >>>>> https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 >>>>> >>>>> Frequency content at 1ns is 350MHz, For the above capacitor the >>>>> impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV >>>>> transient voltage (plus a lot of ringing due to inductance not included) >>>>> >>>>> I would allow for a 100mV voltage transient during that load shift, so >>>>> it seems this single 2.2uF cap would be enough >>>>> >>>>> >>>>> A discussion of the topic here: >>>>> >>>>> https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from >>>>> >>>>> >>>>> Specifically about the capacitors of today, with same package size plot >>>>> comparison: >>>>> >>>>> https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html >>>>> >>>>> (figure 1) >>>>> >>>>> https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 >>>>> >>>> >>>> That usual family of curves is mostly silly. >>>> >>>>> From that plot it makes no sense talking about a lot of different caps >>>>> in parallel. One single 2.2uF rules? >>>> >>>> Except for vias. The usual capacitor VNA fixture doesn't model a PCB >>>> very well. Simulations don't either. >>>> >>>>> >>>>> Adding to this, I have a PCB with about 10.000 mm2 area, where I can >>>>> place a VCC and GND plane. If uninterrupted 100um distance between the >>>>> planes I get 5nF of very good HF capacitor with 0.1ohm impedance at >>>>> 350MHz. Again, not need for smaller caps in the design >>>>> >>>>> On top of this the 100mA load in 1ns is probably a worst case situation. >>>>> During normal operation the microcontroller is running, and not all >>>>> transistors are switching at the same time >>>>> >>>>> Above constrained case does not take the switching capacitance of the >>>>> microcontroller transistors into account. >>>>> >>>>> Any inputs to the above? >>>>> >>>>> Have anybody tried to measure the real life load of a microcontroller? >>>>> >>>>> Regards >>>>> >>>>> Klaus >>>> >>>> >>>> We usually do a ground layer and various power pours on adjacent >>>> layers, and seed that with 1 uF caps most anywhere. That always works >>>> fine with uPs and FPGAs. >>>> >>>> I've TDR'd those structures and see no plane resonances. Sometimes a >>>> tiny hint of edge reflections. Qs are low. >>>> >>>> Agree, the planes themselves are the best HF caps. >>>> >>>> Lots of big FPGAs have substantial (as in 1 uF) on-die capacitance, so >>>> external bypassing is just for any slow stuff. I've tested some NXP >>>> Arms that seem to have none. >>>> >>>> I'm doing some 10 GHz wideband precision analog stuff now, so I do use >>>> a lot of 1 uF 0306 caps right at the IC pins with big copper ground >>>> pours just outside, all on layer 1. >>>> >>>> >>>> >>> >>> The device I am looking at, just for example, is the STM32F750V8 >>> >>> https://www.st.com/resource/en/datasheet/stm32f750v8.pdf >>> >>> It actually has a seperate core voltage, so transients from the core >>> switching is isolated with an internal LDO. The LDO seems to be >>> decoupled with 2x 2.2uF. There is an option to run the core directly >>> (page 28 of the datasheet), at 1.2V >> >> Those 2.2u caps seem to be external. >> >>> >>> So it seems a instruction sleep won't be passed with the 1ns transient, >>> but be smoothed out of the 2x2.2uF and the series regulator. >>> >>> As others suggested, then the direct loading of CPU IO pins are maybe >>> more direct impact on the PDN system >>> >>> Regards >>> >>> Klaus >> >> I wonder if it has any on-die power bypass capacitance. You could >> measure one and see. >> > >For the small embedded controllers, they don't have embedded capacitors. >I have seen the insides of one, only a chip
The bigger Xilinx chips seem to have caps integrated into the monolithic die, so they wouldn't be visible. -- Father Brown's figure remained quite dark and still; but in that instant he had lost his head. His head was always most valuable when he had lost it.
On Thu, 21 Oct 2021 17:38:57 +0200, Klaus Vestergaard Kragelund
<klauskvik@hotmail.com> wrote:

>On 21/10/2021 02.54, Phil Hobbs wrote: >> Klaus Vestergaard Kragelund wrote: >>> Hi >>> >>> Something that I have been coming back to a number of times: >>> >>> When placing capacitors for decoupling of a microcontroller datasheets >>> often suggest a 1nF/100nF and maybe a number of them >>> >>> But it needs to be aligned to what is actually the load. >>> >>> Say I have a microcontroller running at 100MHz. Assumption (and that >>> could be wrong), is that for the given technology the switching of the >>> transistors are 10 times as fast, so 1ns >>> >>> If the micro runs at 100mA during active state (all peripherals and >>> core running), and it then runs a SLEEP instruction, it immediately >>> reduces the current from 100mA to 0 in 1ns, right? >>> >>> If it is operated at 3.3V, using standard 2.2uF cap: >>> >>> (Murata, 10V, X7R) >>> >>> GCM21BR71A225KA37K >>> >>> https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 >>> >>> >>> Frequency content at 1ns is 350MHz, For the above capacitor the >>> impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV >>> transient voltage (plus a lot of ringing due to inductance not included) >>> >>> I would allow for a 100mV voltage transient during that load shift, so >>> it seems this single 2.2uF cap would be enough >>> >>> >>> A discussion of the topic here: >>> >>> https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from >>> >>> >>> >>> Specifically about the capacitors of today, with same package size >>> plot comparison: >>> >>> https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html >>> >>> >>> (figure 1) >>> >>> https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 >>> >>> >>> &#2013266080;From that plot it makes no sense talking about a lot of different >>> caps in parallel. One single 2.2uF rules? >>> >>> Adding to this, I have a PCB with about 10.000 mm2 area, where I can >>> place a VCC and GND plane. If uninterrupted 100um distance between the >>> planes I get 5nF of very good HF capacitor with 0.1ohm impedance at >>> 350MHz. Again, not need for smaller caps in the design >>> >>> On top of this the 100mA load in 1ns is probably a worst case >>> situation. During normal operation the microcontroller is running, and >>> not all transistors are switching at the same time >>> >>> Above constrained case does not take the switching capacitance of the >>> microcontroller transistors into account. >>> >>> Any inputs to the above? >>> >>> Have anybody tried to measure the real life load of a microcontroller? >>> >>> Regards >>> >>> Klaus >> >> Supply network antiresonances (i.e. parallel resonances) do exist and >> can cause problems.&#2013266080; The solution is to sprinkle some alpos around among >> the ceramics.&#2013266080; They look like small resistances at the typical resonance >> frequencies, so they damp the antiresonances very effectively. >> >Bruce Archambeault has done a lot of work on this > >https://interferencetechnology.com/eliminating-the-myths-about-printed-circuit-board-powerground-plane-decoupling/ > >For applications below 500MHz, going from power oin directly to the >plane with a via has best performance, and the capacitors can be spread >out on the PCB if proper power planes are used
That's cool. Some serious real-world mythbusting. Just scatter a lot of 1u caps around the pours! -- Father Brown's figure remained quite dark and still; but in that instant he had lost his head. His head was always most valuable when he had lost it.
Jan Panteltje wrote:
> Klaus Vestergaard wrote: > >>Hi >> >>Something that I have been coming back to a number of times: >> >>When placing capacitors for decoupling of a microcontroller datasheets >>often suggest a 1nF/100nF and maybe a number of them > > I use 100 nF on my PICs 18F14K22 directly at the pins. > those run at 64 MHz > Never a problem > As to the dip in supply caused by switching modes those PICs > for example are good for: > VDD Supply Voltage > PIC18LF1XK22 1.8 -- 3.6 V FOSC < = 20 MHz > 2.7 -- 3.6 V FOSC < = 64 MHz 85&deg;C > 2.7 -- 3.6 V FOSC < = 48 MHz 125&deg;C > > So if you run from say 3.3 V a 600 mV dip should be no problem (in theory anyways) > Further down the road there is usually a bigger electrolytic capacitor, > so slow variations as due to mode switches as into sleep are no problem. > Other micros I know are very much the same. > Load variations on the processor pins by the rest of the circuit may > be several mA and probably more important and in that case your supply > caps and stabilization need to be able to handle that.
My audio circuits typically filter Vdd with a large capacitor in parallel with a 100 nF capacitor. See C1 and C2: https://crcomp.net/altoidsmixer/4.png VSLI uses a similar scheme. See C1, C2, C18 - C26: https://crcomp.net/mp3/vs1053.png Danke, -- Don, KB7RPU, https://www.qsl.net/kb7rpu There was a young lady named Bright Whose speed was far faster than light; She set out one day In a relative way And returned on the previous night.
On Thu, 21 Oct 2021 16:21:09 -0000 (UTC), "Don" <g@crcomp.net> wrote:

>Jan Panteltje wrote: >> Klaus Vestergaard wrote: >> >>>Hi >>> >>>Something that I have been coming back to a number of times: >>> >>>When placing capacitors for decoupling of a microcontroller datasheets >>>often suggest a 1nF/100nF and maybe a number of them >> >> I use 100 nF on my PICs 18F14K22 directly at the pins. >> those run at 64 MHz >> Never a problem >> As to the dip in supply caused by switching modes those PICs >> for example are good for: >> VDD Supply Voltage >> PIC18LF1XK22 1.8 -- 3.6 V FOSC < = 20 MHz >> 2.7 -- 3.6 V FOSC < = 64 MHz 85&#2013266096;C >> 2.7 -- 3.6 V FOSC < = 48 MHz 125&#2013266096;C >> >> So if you run from say 3.3 V a 600 mV dip should be no problem (in theory anyways) >> Further down the road there is usually a bigger electrolytic capacitor, >> so slow variations as due to mode switches as into sleep are no problem. >> Other micros I know are very much the same. >> Load variations on the processor pins by the rest of the circuit may >> be several mA and probably more important and in that case your supply >> caps and stabilization need to be able to handle that. > >My audio circuits typically filter Vdd with a large capacitor in >parallel with a 100 nF capacitor. See C1 and C2: > >https://crcomp.net/altoidsmixer/4.png > >VSLI uses a similar scheme. See C1, C2, C18 - C26: > >https://crcomp.net/mp3/vs1053.png > >Danke,
I knew a guy at Lockheed who didn't use any bypass caps on multilayer logic boards. His stuff worked too. -- Father Brown's figure remained quite dark and still; but in that instant he had lost his head. His head was always most valuable when he had lost it.
21.10.21 18:07, jlarkin@highlandsniptechnology.com wrote:
>On Thu, 21 Oct 2021 17:38:57 +0200, Klaus Vestergaard Kragelund ><klauskvik@hotmail.com> wrote: > >>On 21/10/2021 02.54, Phil Hobbs wrote: >>> Klaus Vestergaard Kragelund wrote: >>>> Hi >>>> >>>> Something that I have been coming back to a number of times: >>>> >>>> When placing capacitors for decoupling of a microcontroller datasheets >>>> often suggest a 1nF/100nF and maybe a number of them >>>> >>>> But it needs to be aligned to what is actually the load. >>>> >>>> Say I have a microcontroller running at 100MHz. Assumption (and that >>>> could be wrong), is that for the given technology the switching of the >>>> transistors are 10 times as fast, so 1ns >>>> >>>> If the micro runs at 100mA during active state (all peripherals and >>>> core running), and it then runs a SLEEP instruction, it immediately >>>> reduces the current from 100mA to 0 in 1ns, right? >>>> >>>> If it is operated at 3.3V, using standard 2.2uF cap: >>>> >>>> (Murata, 10V, X7R) >>>> >>>> GCM21BR71A225KA37K >>>> >>>> https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 >>>> >>>> >>>> Frequency content at 1ns is 350MHz, For the above capacitor the >>>> impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV >>>> transient voltage (plus a lot of ringing due to inductance not included) >>>> >>>> I would allow for a 100mV voltage transient during that load shift, so >>>> it seems this single 2.2uF cap would be enough >>>> >>>> >>>> A discussion of the topic here: >>>> >>>> https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from >>>> >>>> >>>> >>>> Specifically about the capacitors of today, with same package size >>>> plot comparison: >>>> >>>> https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html >>>> >>>> >>>> (figure 1) >>>> >>>> https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 >>>> >>>> >>>> &#2013266080;From that plot it makes no sense talking about a lot of different >>>> caps in parallel. One single 2.2uF rules? >>>> >>>> Adding to this, I have a PCB with about 10.000 mm2 area, where I can >>>> place a VCC and GND plane. If uninterrupted 100um distance between the >>>> planes I get 5nF of very good HF capacitor with 0.1ohm impedance at >>>> 350MHz. Again, not need for smaller caps in the design >>>> >>>> On top of this the 100mA load in 1ns is probably a worst case >>>> situation. During normal operation the microcontroller is running, and >>>> not all transistors are switching at the same time >>>> >>>> Above constrained case does not take the switching capacitance of the >>>> microcontroller transistors into account. >>>> >>>> Any inputs to the above? >>>> >>>> Have anybody tried to measure the real life load of a microcontroller? >>>> >>>> Regards >>>> >>>> Klaus >>> >>> Supply network antiresonances (i.e. parallel resonances) do exist and >>> can cause problems.&#2013266080; The solution is to sprinkle some alpos around among >>> the ceramics.&#2013266080; They look like small resistances at the typical resonance >>> frequencies, so they damp the antiresonances very effectively. >>> >>Bruce Archambeault has done a lot of work on this >> >>https://interferencetechnology.com/eliminating-the-myths-about-printed-circuit-board-powerground-plane-decoupling/ >> >>For applications below 500MHz, going from power oin directly to the >>plane with a via has best performance, and the capacitors can be spread >>out on the PCB if proper power planes are used > >That's cool. Some serious real-world mythbusting. > >Just scatter a lot of 1u caps around the pours!
Yes, and the often seen combinations of parallel 1nF/100nF is also debunked. Same value capacitor has less resonance problems, ie peaking
> >
-- Klaus