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Microcontroller decoupling, >1uF rules?

Started by Klaus Vestergaard Kragelund October 19, 2021
On Thu, 21 Oct 2021 22:35:06 +0200, Klaus Kragelund
<klauskvik@hotmail.com> wrote:

>21.10.21 18:07, jlarkin@highlandsniptechnology.com wrote: >>On Thu, 21 Oct 2021 17:38:57 +0200, Klaus Vestergaard Kragelund >><klauskvik@hotmail.com> wrote: >> >>>On 21/10/2021 02.54, Phil Hobbs wrote: >>>> Klaus Vestergaard Kragelund wrote: >>>>> Hi >>>>> >>>>> Something that I have been coming back to a number of times: >>>>> >>>>> When placing capacitors for decoupling of a microcontroller datasheets >>>>> often suggest a 1nF/100nF and maybe a number of them >>>>> >>>>> But it needs to be aligned to what is actually the load. >>>>> >>>>> Say I have a microcontroller running at 100MHz. Assumption (and that >>>>> could be wrong), is that for the given technology the switching of the >>>>> transistors are 10 times as fast, so 1ns >>>>> >>>>> If the micro runs at 100mA during active state (all peripherals and >>>>> core running), and it then runs a SLEEP instruction, it immediately >>>>> reduces the current from 100mA to 0 in 1ns, right? >>>>> >>>>> If it is operated at 3.3V, using standard 2.2uF cap: >>>>> >>>>> (Murata, 10V, X7R) >>>>> >>>>> GCM21BR71A225KA37K >>>>> >>>>> https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 >>>>> >>>>> >>>>> Frequency content at 1ns is 350MHz, For the above capacitor the >>>>> impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV >>>>> transient voltage (plus a lot of ringing due to inductance not included) >>>>> >>>>> I would allow for a 100mV voltage transient during that load shift, so >>>>> it seems this single 2.2uF cap would be enough >>>>> >>>>> >>>>> A discussion of the topic here: >>>>> >>>>> https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from >>>>> >>>>> >>>>> >>>>> Specifically about the capacitors of today, with same package size >>>>> plot comparison: >>>>> >>>>> https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html >>>>> >>>>> >>>>> (figure 1) >>>>> >>>>> https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 >>>>> >>>>> >>>>> rom that plot it makes no sense talking about a lot of different >>>>> caps in parallel. One single 2.2uF rules? >>>>> >>>>> Adding to this, I have a PCB with about 10.000 mm2 area, where I can >>>>> place a VCC and GND plane. If uninterrupted 100um distance between the >>>>> planes I get 5nF of very good HF capacitor with 0.1ohm impedance at >>>>> 350MHz. Again, not need for smaller caps in the design >>>>> >>>>> On top of this the 100mA load in 1ns is probably a worst case >>>>> situation. During normal operation the microcontroller is running, and >>>>> not all transistors are switching at the same time >>>>> >>>>> Above constrained case does not take the switching capacitance of the >>>>> microcontroller transistors into account. >>>>> >>>>> Any inputs to the above? >>>>> >>>>> Have anybody tried to measure the real life load of a microcontroller? >>>>> >>>>> Regards >>>>> >>>>> Klaus >>>> >>>> Supply network antiresonances (i.e. parallel resonances) do exist and >>>> can cause problems. The solution is to sprinkle some alpos around among >>>> the ceramics. They look like small resistances at the typical resonance >>>> frequencies, so they damp the antiresonances very effectively. >>>> >>>Bruce Archambeault has done a lot of work on this >>> >>>https://interferencetechnology.com/eliminating-the-myths-about-printed-circuit-board-powerground-plane-decoupling/ >>> >>>For applications below 500MHz, going from power oin directly to the >>>plane with a via has best performance, and the capacitors can be spread >>>out on the PCB if proper power planes are used >> >>That's cool. Some serious real-world mythbusting. >> >>Just scatter a lot of 1u caps around the pours! > >Yes, and the often seen combinations of parallel 1nF/100nF is also debunked. Same value capacitor has less resonance problems, ie peaking >> >>
The reason there are so many bypassing theories is that almost anything works. -- If a man will begin with certainties, he shall end with doubts, but if he will be content to begin with doubts he shall end in certainties. Francis Bacon
On Wednesday, October 20, 2021 at 11:42:45 AM UTC-4, anti...@math.uni.wroc.pl wrote:
> Klaus Vestergaard Kragelund <klau...@hotmail.com> wrote: > > If it is operated at 3.3V, using standard 2.2uF cap: > > > > (Murata, 10V, X7R) > > > > GCM21BR71A225KA37K > > > > https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 > > > > Frequency content at 1ns is 350MHz, For the above capacitor the > > impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV > > transient voltage (plus a lot of ringing due to inductance not included) > At that frequency inductance of leads and traces is quite significant. > So it matters where you want your transient. AFAICS insided chip it > is really to chip designer, all you can do is to get capacitor as close > to chip as possible. OTOH I would expect transiton to be slowed down > by internal filtering.
The problem with that thinking is that caps are very seldom connected to the chip by traces, rather by ground and power planes. I recall all manner of analysis that talked about the geometry of the three way connection of chip, cap and planes, mostly wrong analysis because it was never tested or even simulated other than in the mind.
> > I would allow for a 100mV voltage transient during that load shift, so > > it seems this single 2.2uF cap would be enough > Single cap per pair of power pins, otherwise inductance of traces > plays role. Since transitions are much slower than you assume > you may get away with single cap in purely digital circuit > (but you probably will exceed 100mV limit on transients).
That has been debunked. The caps are coupled to the power plane and provide bulk capacitance more so than being individual caps to the pins. A cap can be inches away before you see significant effects. This is because the power and ground planes act as transmission lines supplying the current required until the current wavefront reaches the cap and the cap provides current in the reflection. Transmission lines are not lumped inductors or capacitors and thinking of them as such produces wrong results. Most rules of thumb have never been tested and when they are tested turn out to be wrong or at least exaggerated.
> > A discussion of the topic here: > > > > https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from > > > > > > Specifically about the capacitors of today, with same package size plot > > comparison: > > > > https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html > > > > (figure 1) > > > > https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 > > > > From that plot it makes no sense talking about a lot of different caps > > in parallel. One single 2.2uF rules? > Well, it depends how much low frequency filtering is needed. Classic 0.1uF > is enough for high frequencies. Due to inductance you want capacitor > per power pins pair and it makes sense to use capacitors of the > same value. OTOH 2.2uF after 2.2uS with current 100mA will drop by > 100mV. So you probably want more low freqency filtering. Also, > it makes sense to add electrolytic (or RC) to dump resonances.
Do you analyzed transmission lines by treating them as lumped inductors??? Why would you treat the transmission line formed by the power/ground plane pair as a lumped inductor between the power pin on the chip and a decoupling cap? The power/ground plane pair is not just another cap connected to your PDS, it's the transmission line connecting everything together. -- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209