Hi Something that I have been coming back to a number of times: When placing capacitors for decoupling of a microcontroller datasheets often suggest a 1nF/100nF and maybe a number of them But it needs to be aligned to what is actually the load. Say I have a microcontroller running at 100MHz. Assumption (and that could be wrong), is that for the given technology the switching of the transistors are 10 times as fast, so 1ns If the micro runs at 100mA during active state (all peripherals and core running), and it then runs a SLEEP instruction, it immediately reduces the current from 100mA to 0 in 1ns, right? If it is operated at 3.3V, using standard 2.2uF cap: (Murata, 10V, X7R) GCM21BR71A225KA37K https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 Frequency content at 1ns is 350MHz, For the above capacitor the impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV transient voltage (plus a lot of ringing due to inductance not included) I would allow for a 100mV voltage transient during that load shift, so it seems this single 2.2uF cap would be enough A discussion of the topic here: https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from Specifically about the capacitors of today, with same package size plot comparison: https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html (figure 1) https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 From that plot it makes no sense talking about a lot of different caps in parallel. One single 2.2uF rules? Adding to this, I have a PCB with about 10.000 mm2 area, where I can place a VCC and GND plane. If uninterrupted 100um distance between the planes I get 5nF of very good HF capacitor with 0.1ohm impedance at 350MHz. Again, not need for smaller caps in the design On top of this the 100mA load in 1ns is probably a worst case situation. During normal operation the microcontroller is running, and not all transistors are switching at the same time Above constrained case does not take the switching capacitance of the microcontroller transistors into account. Any inputs to the above? Have anybody tried to measure the real life load of a microcontroller? Regards Klaus
Microcontroller decoupling, >1uF rules?
Started by ●October 19, 2021
Reply by ●October 19, 20212021-10-19
On 20/10/2021 01.40, Klaus Vestergaard Kragelund wrote:> Hi > > Something that I have been coming back to a number of times: > > When placing capacitors for decoupling of a microcontroller datasheets > often suggest a 1nF/100nF and maybe a number of them > > But it needs to be aligned to what is actually the load. > > Say I have a microcontroller running at 100MHz. Assumption (and that > could be wrong), is that for the given technology the switching of the > transistors are 10 times as fast, so 1ns > > If the micro runs at 100mA during active state (all peripherals and core > running), and it then runs a SLEEP instruction, it immediately reduces > the current from 100mA to 0 in 1ns, right? > > If it is operated at 3.3V, using standard 2.2uF cap: > > (Murata, 10V, X7R) > > GCM21BR71A225KA37K > > https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 > > > Frequency content at 1ns is 350MHz, For the above capacitor the > impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV > transient voltage (plus a lot of ringing due to inductance not included) > > I would allow for a 100mV voltage transient during that load shift, so > it seems this single 2.2uF cap would be enough > > > A discussion of the topic here: > > https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from > > > > Specifically about the capacitors of today, with same package size plot > comparison: > > https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html > > > (figure 1) > > https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 > > > From that plot it makes no sense talking about a lot of different caps > in parallel. One single 2.2uF rules? > > Adding to this, I have a PCB with about 10.000 mm2 area, where I can > place a VCC and GND plane. If uninterrupted 100um distance between the > planes I get 5nF of very good HF capacitor with 0.1ohm impedance at > 350MHz. Again, not need for smaller caps in the design > > On top of this the 100mA load in 1ns is probably a worst case situation. > During normal operation the microcontroller is running, and not all > transistors are switching at the same time > > Above constrained case does not take the switching capacitance of the > microcontroller transistors into account. > > Any inputs to the above? > > Have anybody tried to measure the real life load of a microcontroller? >One needs of course to be careful about plane resonance as shown in figure 2 of this publication: https://cecas.clemson.edu/cvel/pdf/ADVP02-424.pdf
Reply by ●October 19, 20212021-10-19
On 10/19/2021 7:40 PM, Klaus Vestergaard Kragelund wrote:> Hi > > Something that I have been coming back to a number of times: > > When placing capacitors for decoupling of a microcontroller datasheets > often suggest a 1nF/100nF and maybe a number of them > > But it needs to be aligned to what is actually the load. > > Say I have a microcontroller running at 100MHz. Assumption (and that > could be wrong), is that for the given technology the switching of the > transistors are 10 times as fast, so 1ns > > If the micro runs at 100mA during active state (all peripherals and core > running), and it then runs a SLEEP instruction, it immediately reduces > the current from 100mA to 0 in 1ns, right?Ahh, I dunno about that even on an 8 bit AVR the SLEEP instruction takes a full clock cycle to execute, and the program counter has to finish updating itself into the PC = PC + 1 state before the core clock is shut down and responsibility is handed off to the wake controller/watchdog timer.
Reply by ●October 19, 20212021-10-19
On 10/19/2021 7:43 PM, Klaus Vestergaard Kragelund wrote:> On 20/10/2021 01.40, Klaus Vestergaard Kragelund wrote: >> Hi >> >> Something that I have been coming back to a number of times: >> >> When placing capacitors for decoupling of a microcontroller datasheets >> often suggest a 1nF/100nF and maybe a number of them >> >> But it needs to be aligned to what is actually the load. >> >> Say I have a microcontroller running at 100MHz. Assumption (and that >> could be wrong), is that for the given technology the switching of the >> transistors are 10 times as fast, so 1ns >> >> If the micro runs at 100mA during active state (all peripherals and >> core running), and it then runs a SLEEP instruction, it immediately >> reduces the current from 100mA to 0 in 1ns, right?Also any microcontroller of significant complexity is going to have pipelined execution; even the AVR has 2 stage fetch/execute, and when it hits the SLEEP instruction you know with certainty a branch is going to occur later to an interrupt vector when it comes out so everything in the pipeline after it is junk and needs to be flushed. I think there need to be some housekeeping tasks done before it can just drop into sleep and how quickly it can do them depends on if it has special ability to identify the sleep instruction earlier in the pipeline than others, but I don't think anything can start moving with respect to shutting stuff down until the PC is updated and the pipeline flushed at minimum.
Reply by ●October 19, 20212021-10-19
On Wed, 20 Oct 2021 01:40:15 +0200, Klaus Vestergaard Kragelund <klauskvik@hotmail.com> wrote:>Hi > >Something that I have been coming back to a number of times: > >When placing capacitors for decoupling of a microcontroller datasheets >often suggest a 1nF/100nF and maybe a number of them > >But it needs to be aligned to what is actually the load. > >Say I have a microcontroller running at 100MHz. Assumption (and that >could be wrong), is that for the given technology the switching of the >transistors are 10 times as fast, so 1ns > >If the micro runs at 100mA during active state (all peripherals and core >running), and it then runs a SLEEP instruction, it immediately reduces >the current from 100mA to 0 in 1ns, right? > >If it is operated at 3.3V, using standard 2.2uF cap: > >(Murata, 10V, X7R) > >GCM21BR71A225KA37K > >https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 > >Frequency content at 1ns is 350MHz, For the above capacitor the >impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV >transient voltage (plus a lot of ringing due to inductance not included) > >I would allow for a 100mV voltage transient during that load shift, so >it seems this single 2.2uF cap would be enough > > >A discussion of the topic here: > >https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from > > >Specifically about the capacitors of today, with same package size plot >comparison: > >https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html > >(figure 1) > >https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 >That usual family of curves is mostly silly.> From that plot it makes no sense talking about a lot of different caps >in parallel. One single 2.2uF rules?Except for vias. The usual capacitor VNA fixture doesn't model a PCB very well. Simulations don't either.> >Adding to this, I have a PCB with about 10.000 mm2 area, where I can >place a VCC and GND plane. If uninterrupted 100um distance between the >planes I get 5nF of very good HF capacitor with 0.1ohm impedance at >350MHz. Again, not need for smaller caps in the design > >On top of this the 100mA load in 1ns is probably a worst case situation. >During normal operation the microcontroller is running, and not all >transistors are switching at the same time > >Above constrained case does not take the switching capacitance of the >microcontroller transistors into account. > >Any inputs to the above? > >Have anybody tried to measure the real life load of a microcontroller? > >Regards > >KlausWe usually do a ground layer and various power pours on adjacent layers, and seed that with 1 uF caps most anywhere. That always works fine with uPs and FPGAs. I've TDR'd those structures and see no plane resonances. Sometimes a tiny hint of edge reflections. Qs are low. Agree, the planes themselves are the best HF caps. Lots of big FPGAs have substantial (as in 1 uF) on-die capacitance, so external bypassing is just for any slow stuff. I've tested some NXP Arms that seem to have none. I'm doing some 10 GHz wideband precision analog stuff now, so I do use a lot of 1 uF 0306 caps right at the IC pins with big copper ground pours just outside, all on layer 1. -- Father Brown's figure remained quite dark and still; but in that instant he had lost his head. His head was always most valuable when he had lost it.
Reply by ●October 20, 20212021-10-20
On Tuesday, October 19, 2021 at 7:43:50 PM UTC-4, Klaus Kragelund wrote:> On 20/10/2021 01.40, Klaus Vestergaard Kragelund wrote: > > Hi > > > > Something that I have been coming back to a number of times: > > > > When placing capacitors for decoupling of a microcontroller datasheets > > often suggest a 1nF/100nF and maybe a number of them > > > > But it needs to be aligned to what is actually the load. > > > > Say I have a microcontroller running at 100MHz. Assumption (and that > > could be wrong), is that for the given technology the switching of the > > transistors are 10 times as fast, so 1ns > > > > If the micro runs at 100mA during active state (all peripherals and core > > running), and it then runs a SLEEP instruction, it immediately reduces > > the current from 100mA to 0 in 1ns, right? > > > > If it is operated at 3.3V, using standard 2.2uF cap: > > > > (Murata, 10V, X7R) > > > > GCM21BR71A225KA37K > > > > https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 > > > > > > Frequency content at 1ns is 350MHz, For the above capacitor the > > impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV > > transient voltage (plus a lot of ringing due to inductance not included) > > > > I would allow for a 100mV voltage transient during that load shift, so > > it seems this single 2.2uF cap would be enough > > > > > > A discussion of the topic here: > > > > https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from > > > > > > > > Specifically about the capacitors of today, with same package size plot > > comparison: > > > > https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html > > > > > > (figure 1) > > > > https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 > > > > > > From that plot it makes no sense talking about a lot of different caps > > in parallel. One single 2.2uF rules? > > > > Adding to this, I have a PCB with about 10.000 mm2 area, where I can > > place a VCC and GND plane. If uninterrupted 100um distance between the > > planes I get 5nF of very good HF capacitor with 0.1ohm impedance at > > 350MHz. Again, not need for smaller caps in the design > > > > On top of this the 100mA load in 1ns is probably a worst case situation. > > During normal operation the microcontroller is running, and not all > > transistors are switching at the same time > > > > Above constrained case does not take the switching capacitance of the > > microcontroller transistors into account. > > > > Any inputs to the above? > > > > Have anybody tried to measure the real life load of a microcontroller? > > > One needs of course to be careful about plane resonance as shown in > figure 2 of this publication: > > https://cecas.clemson.edu/cvel/pdf/ADVP02-424.pdfMany people try to simplify power distribution system design to a few simple rules of thumb like a single 0.1 uF cap for each power pin. This is not based on anything specific to your design or even the chip that is being decoupled, yet many follow such rules. As Lee Ritchey said, "No one ever got fired for using too many caps in a PDS". Your analysis is based on various assumptions you have made. The only way to actually know what is happening is to either get the decoupling information from the chip manufacturer or to build a test board and measure it yourself. Keep in mind that while the chip has internal currents that create fast spikes, the currents required to drive output signals can also produce significant current spikes on the power rails. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
Reply by ●October 20, 20212021-10-20
Klaus Vestergaard Kragelund <klauskvik@hotmail.com> wrote:> Hi > > Something that I have been coming back to a number of times: > > When placing capacitors for decoupling of a microcontroller datasheets > often suggest a 1nF/100nF and maybe a number of them > > But it needs to be aligned to what is actually the load. > > Say I have a microcontroller running at 100MHz. Assumption (and that > could be wrong), is that for the given technology the switching of the > transistors are 10 times as fast, so 1nsProcessor designer talk about "gate delay". For fast processors typical rules would have 12-20 gate dalays per clock. which means that during clock cycle signal has time to pass for say 20 gates. For slower ones (like your 100MHz case) more likely 20-50 (allowing pass trough more gates means that number of gates can be minimized, giving slower but smaller core). Also, effective delays are largely due to parasitice capacitance. So, transistors are likely to be much faster. They switch with limited speed because they are driven by slowed-down signal, but still I would expect closer to 0.3ns.> If the micro runs at 100mA during active state (all peripherals and core > running), and it then runs a SLEEP instruction, it immediately reduces > the current from 100mA to 0 in 1ns, right?No, for various reasons: 1) normal SLEEP does not stop clocks and keeps peripherials running. Only core is stopped. Various "deep sleep" variants are multi-clock. 2) during cycle transitions goes trough several layers of gates and signals need to propagate trough transmisson lines. So "stopping" need to propagate and it takes time. 3) Significant power (say 1/3 ot total core power) goes into clock lines. For sleep new clock transition is stopped, but at time when new transition should happen clock line is quiet (this is related to point 2). 4) There is a lot of internal parasitic decoupling.> If it is operated at 3.3V, using standard 2.2uF cap: > > (Murata, 10V, X7R) > > GCM21BR71A225KA37K > > https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 > > Frequency content at 1ns is 350MHz, For the above capacitor the > impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV > transient voltage (plus a lot of ringing due to inductance not included)At that frequency inductance of leads and traces is quite significant. So it matters where you want your transient. AFAICS insided chip it is really to chip designer, all you can do is to get capacitor as close to chip as possible. OTOH I would expect transiton to be slowed down by internal filtering.> I would allow for a 100mV voltage transient during that load shift, so > it seems this single 2.2uF cap would be enoughSingle cap per pair of power pins, otherwise inductance of traces plays role. Since transitions are much slower than you assume you may get away with single cap in purely digital circuit (but you probably will exceed 100mV limit on transients).> A discussion of the topic here: > > https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from > > > Specifically about the capacitors of today, with same package size plot > comparison: > > https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html > > (figure 1) > > https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 > > From that plot it makes no sense talking about a lot of different caps > in parallel. One single 2.2uF rules?Well, it depends how much low frequency filtering is needed. Classic 0.1uF is enough for high frequencies. Due to inductance you want capacitor per power pins pair and it makes sense to use capacitors of the same value. OTOH 2.2uF after 2.2uS with current 100mA will drop by 100mV. So you probably want more low freqency filtering. Also, it makes sense to add electrolytic (or RC) to dump resonances. -- Waldek Hebisch
Reply by ●October 20, 20212021-10-20
On Wed, 20 Oct 2021 15:42:39 +0000 (UTC), antispam@math.uni.wroc.pl wrote:>Klaus Vestergaard Kragelund <klauskvik@hotmail.com> wrote: >> Hi >> >> Something that I have been coming back to a number of times: >> >> When placing capacitors for decoupling of a microcontroller datasheets >> often suggest a 1nF/100nF and maybe a number of them >> >> But it needs to be aligned to what is actually the load. >> >> Say I have a microcontroller running at 100MHz. Assumption (and that >> could be wrong), is that for the given technology the switching of the >> transistors are 10 times as fast, so 1ns > >Processor designer talk about "gate delay". For fast processors >typical rules would have 12-20 gate dalays per clock. which means >that during clock cycle signal has time to pass for say 20 gates. >For slower ones (like your 100MHz case) more likely 20-50 (allowing >pass trough more gates means that number of gates can be minimized, >giving slower but smaller core). Also, effective delays are >largely due to parasitice capacitance. So, transistors are likely >to be much faster. They switch with limited speed because they >are driven by slowed-down signal, but still I would expect closer >to 0.3ns.In modern FPGAs, local equivalent gate delays are picoseconds. The big delays are wiring. SERDES blocks are fairly complex and clock at 10s of GHz.> >> If the micro runs at 100mA during active state (all peripherals and core >> running), and it then runs a SLEEP instruction, it immediately reduces >> the current from 100mA to 0 in 1ns, right? > >No, for various reasons: >1) normal SLEEP does not stop clocks and keeps peripherials > running. Only core is stopped. Various "deep sleep" > variants are multi-clock. >2) during cycle transitions goes trough several layers of gates > and signals need to propagate trough transmisson lines. > So "stopping" need to propagate and it takes time. >3) Significant power (say 1/3 ot total core power) goes into > clock lines. For sleep new clock transition is stopped, but > at time when new transition should happen clock line is > quiet (this is related to point 2). >4) There is a lot of internal parasitic decoupling. > >> If it is operated at 3.3V, using standard 2.2uF cap: >> >> (Murata, 10V, X7R) >> >> GCM21BR71A225KA37K >> >> https://www.murata.com/en-eu/api/pdfdownloadapi?cate=luCeramicCapacitorsSMD&partno=GCM21BR71A225KA37%23 >> >> Frequency content at 1ns is 350MHz, For the above capacitor the >> impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV >> transient voltage (plus a lot of ringing due to inductance not included) > >At that frequency inductance of leads and traces is quite significant. >So it matters where you want your transient. AFAICS insided chip it >is really to chip designer, all you can do is to get capacitor as close >to chip as possible. OTOH I would expect transiton to be slowed down >by internal filtering. > >> I would allow for a 100mV voltage transient during that load shift, so >> it seems this single 2.2uF cap would be enough > >Single cap per pair of power pins, otherwise inductance of traces >plays role. Since transitions are much slower than you assume >you may get away with single cap in purely digital circuit >(but you probably will exceed 100mV limit on transients). > >> A discussion of the topic here: >> >> https://electronics.stackexchange.com/questions/172447/where-did-the-value-of-0-1uf-for-bypass-capacitors-come-from >> >> >> Specifically about the capacitors of today, with same package size plot >> comparison: >> >> https://www.analog.com/en/analog-dialogue/articles/high-speed-printed-circuit-board-layout.html >> >> (figure 1) >> >> https://www.analog.com/-/media/images/analog-dialogue/en/volume-39/number-3/articles/high-speed-printed-circuit-board-layout/high-speed-printed-circuit-board-layout_fig01.gif?la=en&imgver=1 >> >> From that plot it makes no sense talking about a lot of different caps >> in parallel. One single 2.2uF rules? > >Well, it depends how much low frequency filtering is needed. Classic 0.1uF >is enough for high frequencies. Due to inductance you want capacitor >per power pins pair and it makes sense to use capacitors of the >same value. OTOH 2.2uF after 2.2uS with current 100mA will drop by >100mV. So you probably want more low freqency filtering. Also, >it makes sense to add electrolytic (or RC) to dump resonances.Tantalums have nice ESRs, to keep regulators happy. Polymers are better to provide surge currents. Our universal bypass is 1 uF 50v 0805, which we use on supply rails up to 24 volts. -- Father Brown's figure remained quite dark and still; but in that instant he had lost his head. His head was always most valuable when he had lost it.
Reply by ●October 20, 20212021-10-20
On 10/20/2021 11:42 AM, antispam@math.uni.wroc.pl wrote:> Klaus Vestergaard Kragelund <klauskvik@hotmail.com> wrote: >> Hi >> >> Something that I have been coming back to a number of times: >> >> When placing capacitors for decoupling of a microcontroller datasheets >> often suggest a 1nF/100nF and maybe a number of them >> >> But it needs to be aligned to what is actually the load. >> >> Say I have a microcontroller running at 100MHz. Assumption (and that >> could be wrong), is that for the given technology the switching of the >> transistors are 10 times as fast, so 1ns > > Processor designer talk about "gate delay". For fast processors > typical rules would have 12-20 gate dalays per clock. which means > that during clock cycle signal has time to pass for say 20 gates. > For slower ones (like your 100MHz case) more likely 20-50 (allowing > pass trough more gates means that number of gates can be minimized, > giving slower but smaller core). Also, effective delays are > largely due to parasitice capacitance. So, transistors are likely > to be much faster. They switch with limited speed because they > are driven by slowed-down signal, but still I would expect closer > to 0.3ns. > >> If the micro runs at 100mA during active state (all peripherals and core >> running), and it then runs a SLEEP instruction, it immediately reduces >> the current from 100mA to 0 in 1ns, right? > > No, for various reasons: > 1) normal SLEEP does not stop clocks and keeps peripherials > running. Only core is stopped. Various "deep sleep" > variants are multi-clock. > 2) during cycle transitions goes trough several layers of gates > and signals need to propagate trough transmisson lines. > So "stopping" need to propagate and it takes time. > 3) Significant power (say 1/3 ot total core power) goes into > clock lines. For sleep new clock transition is stopped, but > at time when new transition should happen clock line is > quiet (this is related to point 2). > 4) There is a lot of internal parasitic decoupling.I'd be surprised if "physical layer" stuff was the main bottleneck on how fast a processor can drop into deep sleep, there's usually executional house-keeping that needs to be performed like setting/resetting flags and flushing the pipeline. AFAIK even in processors with branch prediction/speculative execution all sleep instructions are somewhat the equivalent of incorrect speculation, you can't predict what's going to happen after that or what external or internal trigger will bring it back out.
Reply by ●October 20, 20212021-10-20
On a sunny day (Wed, 20 Oct 2021 01:40:15 +0200) it happened Klaus Vestergaard Kragelund <klauskvik@hotmail.com> wrote in <sknl0u$1bl9$1@gioia.aioe.org>:>Hi > >Something that I have been coming back to a number of times: > >When placing capacitors for decoupling of a microcontroller datasheets >often suggest a 1nF/100nF and maybe a number of themI use 100 nF on my PICs 18F14K22 directly at the pins. those run at 64 MHz Never a problem As to the dip in supply caused by switching modes those PICs for example are good for: VDD Supply Voltage PIC18LF1XK22 1.8 -- 3.6 V FOSC < = 20 MHz 2.7 -- 3.6 V FOSC < = 64 MHz 85�C 2.7 -- 3.6 V FOSC < = 48 MHz 125�C So if you run from say 3.3 V a 600 mV dip should be no problem (in theory anyways) Further down the road there is usually a bigger electrolytic capacitor, so slow variations as due to mode switches as into sleep are no problem. Other micros I know are very much the same. Load variations on the processor pins by the rest of the circuit may be several mA and probably more important and in that case your supply caps and stabilization need to be able to handle that.
