On 2021/10/14 7:37 p.m., whit3rd wrote:> On Thursday, October 14, 2021 at 11:29:54 AM UTC-7, John Robertson wrote: >> I am still working with a friend on a TTL level replacement for some >> chips on a pinball board and we have a nice FPGA (MAX 10 based) but it >> wants (of course) 3.3V I/O. >> >> I was thinking that SN74CBT16211C (24 x IO level shifter) and a TVS >> arrays like the D3V3X8U9LP3810-7 with a low Ohm (1 - 10R) Flame-Proof >> 1/8W or less resistor on the outside world interface would do for >> protection. >> >> Any other suggestions to ...protecting the SN74CBT16211C where it interfaces >> to switches, etc. in the 'real world' of a pinball game cabinet. > > Depending on how many 'switches' there are, the venerable MC1489 > tolerates lots of input volts and is a multiple-sourced jellybean. I"m > wary of diode-to-Vdd clamps, though, since that just puts trash currents into > your 3.3V regulator; the chip can survive, but will regulation suffer? > No need for a series resistor, that's built-in, and '1489 input clamping is to GND. >Actually the diode clamps are tied to the 5VDC Vcc, and there will be a 5.6V Transorb as well to take care of surges before the regulator is affected. My I/O are switches on the playfield and coin acceptor and self test switch, all are the most at risk of static shock from the player. Considering that there are around 20 I/O to protect I don't think a group of 1489s is going to fit as well as some TVS arrays and resistors that will blow open if any real current starts to flow. It does raise the problem of ground or power loops though if there is a surge on one of the lines. I'll talk that over with my cohort - we have options for ground and 5VDC tie points. Thanks, John :-#)# -- (Please post followups or tech inquiries to the USENET newsgroup) John's Jukes Ltd. MOVED to #7 - 3979 Marine Way, Burnaby, BC, Canada V5J 5E3 (604)872-5757 (Pinballs, Jukes, Video Games) www.flippers.com "Old pinballers never die, they just flip out."
Input protection for 3.3V FPGA in a TTL world...
Started by ●October 14, 2021
Reply by ●October 15, 20212021-10-15
Reply by ●October 15, 20212021-10-15
On a sunny day (Thu, 14 Oct 2021 23:05:16 -0700) it happened John Robertson <spam@flippers.com> wrote in <VPKdnVOaSuaCh_T8nZ2dnUU7-RXNnZ2d@giganews.com>:>On 2021/10/14 7:37 p.m., whit3rd wrote: >> On Thursday, October 14, 2021 at 11:29:54 AM UTC-7, John Robertson wrote: >>> I am still working with a friend on a TTL level replacement for some >>> chips on a pinball board and we have a nice FPGA (MAX 10 based) but it >>> wants (of course) 3.3V I/O. >>> >>> I was thinking that SN74CBT16211C (24 x IO level shifter) and a TVS >>> arrays like the D3V3X8U9LP3810-7 with a low Ohm (1 - 10R) Flame-Proof >>> 1/8W or less resistor on the outside world interface would do for >>> protection. >>> >>> Any other suggestions to ...protecting the SN74CBT16211C where it interfaces >>> to switches, etc. in the 'real world' of a pinball game cabinet. >> >> Depending on how many 'switches' there are, the venerable MC1489 >> tolerates lots of input volts and is a multiple-sourced jellybean. I"m >> wary of diode-to-Vdd clamps, though, since that just puts trash currents into >> your 3.3V regulator; the chip can survive, but will regulation suffer? >> No need for a series resistor, that's built-in, and '1489 input clamping is to GND. >> > >Actually the diode clamps are tied to the 5VDC Vcc, and there will be a >5.6V Transorb as well to take care of surges before the regulator is >affected. > >My I/O are switches on the playfield and coin acceptor and self test >switch, all are the most at risk of static shock from the player. >Considering that there are around 20 I/O to protect I don't think a >group of 1489s is going to fit as well as some TVS arrays and resistors >that will blow open if any real current starts to flow. > >It does raise the problem of ground or power loops though if there is a >surge on one of the lines. I'll talk that over with my cohort - we have >options for ground and 5VDC tie points.I had such a user interface problem long ago and used opto couplers.
Reply by ●October 15, 20212021-10-15
On Thu, 14 Oct 2021 18:28:30 -0700 (PDT), Anthony William Sloman <bill.sloman@ieee.org> wrote:>On Friday, October 15, 2021 at 7:21:36 AM UTC+11, John Larkin wrote: >> On Thu, 14 Oct 2021 21:16:03 +0100, piglet <erichp...@hotmail.com> >> wrote: >> >On 14/10/2021 8:32 pm, John Larkin wrote: >> >> >> >> For an input to the FPGA, you could use just a series resistor and let >> >> any overvoltage or spikes hit the ESD diodes. Debounce as needed. >> >> >> >> 10K or something. Paranoids could add a cap to ground, 1 nf or so. >> >> >> > >> >The MAX 10 datasheet has very specific input overvoltage specs, for >> >instance 4.27V for <4.3% of the time over 11.4 years, equally bizarrely >> >they specifiy the supply voltage to three decimal places. >> > >> >I think Intel really do not want the ESD diodes to be touched? >> > >> >piglet >> > >> What are they for? > >They protect the circuit from catastrophic and irreversible failure. There's no guarantee that the circuit will work to specification when there's current flowing through the protection diodes, and the one time I tried it, the integrated circuit didn't - and it took fairly careful measurements to show that it wasn't.Running current through the ESD diodes is a really bad idea. For one thin, you can get subtle weirdness like Bill mentioned. Even if operation doesn't appear to be affected, repeated overvoltage stress of the gates on the input buffers over time can lead to threshold shifts that might cause the system to become unreliable or stop working altogether. This could take a long time (months or years) to occur so you might not catch it in testing. If it's TTL it's not going very fast. Could you interpose open-drain drivers with pullups to 3.3V on the FPGA inputs, and proper level-shifters open-drain drivers with pullups to 5V on the outputs?
Reply by ●October 15, 20212021-10-15
On Fri, 15 Oct 2021 08:42:09 -0400, Steve Goldstein <sgoldHAM@alum.mit.edu> wrote:>On Thu, 14 Oct 2021 18:28:30 -0700 (PDT), Anthony William Sloman ><bill.sloman@ieee.org> wrote: > >>On Friday, October 15, 2021 at 7:21:36 AM UTC+11, John Larkin wrote: >>> On Thu, 14 Oct 2021 21:16:03 +0100, piglet <erichp...@hotmail.com> >>> wrote: >>> >On 14/10/2021 8:32 pm, John Larkin wrote: >>> >> >>> >> For an input to the FPGA, you could use just a series resistor and let >>> >> any overvoltage or spikes hit the ESD diodes. Debounce as needed. >>> >> >>> >> 10K or something. Paranoids could add a cap to ground, 1 nf or so. >>> >> >>> > >>> >The MAX 10 datasheet has very specific input overvoltage specs, for >>> >instance 4.27V for <4.3% of the time over 11.4 years, equally bizarrely >>> >they specifiy the supply voltage to three decimal places. >>> > >>> >I think Intel really do not want the ESD diodes to be touched? >>> > >>> >piglet >>> > >>> What are they for? >> >>They protect the circuit from catastrophic and irreversible failure. There's no guarantee that the circuit will work to specification when there's current flowing through the protection diodes, and the one time I tried it, the integrated circuit didn't - and it took fairly careful measurements to show that it wasn't. > >Running current through the ESD diodes is a really bad idea. For one >thin, you can get subtle weirdness like Bill mentioned.In analog circuits, yes. The hazard in digitals is SCR latchup, which hasn't been a problem in properly designed chips since 4000A cmos logic. Bill uses the ultimate strategy to avoid design risk: he doesn't design anything.> >Even if operation doesn't appear to be affected, repeated overvoltage >stress of the gates on the input buffers over time can lead to >threshold shifts that might cause the system to become unreliable or >stop working altogether. This could take a long time (months or >years) to occur so you might not catch it in testing.A sensible input pin rating reads like "4.2V max or 30 mA max, whichever ocurrs first." Overvoltage is not a hazard if it never happens. Threshold shifts are unlikely to happen at tenths of a volt past the rails. And they won't matter if the swing is rail-to-rail. And it's only a pinball machine. -- Father Brown's figure remained quite dark and still; but in that instant he had lost his head. His head was always most valuable when he had lost it.
Reply by ●October 15, 20212021-10-15
On 10/15/2021 17:00, jlarkin@highlandsniptechnology.com wrote:> On Fri, 15 Oct 2021 08:42:09 -0400, Steve Goldstein > <sgoldHAM@alum.mit.edu> wrote: > >> On Thu, 14 Oct 2021 18:28:30 -0700 (PDT), Anthony William Sloman >> <bill.sloman@ieee.org> wrote: >> >>> On Friday, October 15, 2021 at 7:21:36 AM UTC+11, John Larkin wrote: >>>> On Thu, 14 Oct 2021 21:16:03 +0100, piglet <erichp...@hotmail.com> >>>> wrote: >>>>> On 14/10/2021 8:32 pm, John Larkin wrote: >>>>>> >>>>>> For an input to the FPGA, you could use just a series resistor and let >>>>>> any overvoltage or spikes hit the ESD diodes. Debounce as needed. >>>>>> >>>>>> 10K or something. Paranoids could add a cap to ground, 1 nf or so. >>>>>> >>>>> >>>>> The MAX 10 datasheet has very specific input overvoltage specs, for >>>>> instance 4.27V for <4.3% of the time over 11.4 years, equally bizarrely >>>>> they specifiy the supply voltage to three decimal places. >>>>> >>>>> I think Intel really do not want the ESD diodes to be touched? >>>>> >>>>> piglet >>>>> >>>> What are they for? >>> >>> They protect the circuit from catastrophic and irreversible failure. There's no guarantee that the circuit will work to specification when there's current flowing through the protection diodes, and the one time I tried it, the integrated circuit didn't - and it took fairly careful measurements to show that it wasn't. >> >> Running current through the ESD diodes is a really bad idea. For one >> thin, you can get subtle weirdness like Bill mentioned. > > In analog circuits, yes. The hazard in digitals is SCR latchup, which > hasn't been a problem in properly designed chips since 4000A cmos > logic. >I have witnessed warnings about electric migration because of repetitive use of the input protection diodes, this at the time when 120nm were the norm. Never experienced it myself and frankly never believed it would matter much back then but as the sizes get tinier I might be scratching my head about that.
Reply by ●October 15, 20212021-10-15
On 10/15/2021 7:00 AM, jlarkin@highlandsniptechnology.com wrote:> And it's only a pinball machine.If it's someone's livelihood, then it's like saying "it's only a paycheck". A repair can be costly (in time) as the machine may be located "anywhere". Worse, if used by the public and it earns a reputation for being flakey, then the whole machine can be a writeoff -- this being considerably more costly as it's not generating revenue AND it's an equipment investment that has no value. I doubt John R would want his customers to decide his products are a cause of pain/loss for them -- even if he's just selling to home arcades! (if you bought it, you likely want to USE it -- or, have a shitload of space to spare to store refrigerator sized devices!)
Reply by ●October 15, 20212021-10-15
On 2021/10/15 5:42 a.m., Steve Goldstein wrote:> On Thu, 14 Oct 2021 18:28:30 -0700 (PDT), Anthony William Sloman > <bill.sloman@ieee.org> wrote: > >> On Friday, October 15, 2021 at 7:21:36 AM UTC+11, John Larkin wrote: >>> On Thu, 14 Oct 2021 21:16:03 +0100, piglet <erichp...@hotmail.com> >>> wrote: >>>> On 14/10/2021 8:32 pm, John Larkin wrote: >>>>> >>>>> For an input to the FPGA, you could use just a series resistor and let >>>>> any overvoltage or spikes hit the ESD diodes. Debounce as needed. >>>>> >>>>> 10K or something. Paranoids could add a cap to ground, 1 nf or so. >>>>> >>>> >>>> The MAX 10 datasheet has very specific input overvoltage specs, for >>>> instance 4.27V for <4.3% of the time over 11.4 years, equally bizarrely >>>> they specifiy the supply voltage to three decimal places. >>>> >>>> I think Intel really do not want the ESD diodes to be touched? >>>> >>>> piglet >>>> >>> What are they for? >> >> They protect the circuit from catastrophic and irreversible failure. There's no guarantee that the circuit will work to specification when there's current flowing through the protection diodes, and the one time I tried it, the integrated circuit didn't - and it took fairly careful measurements to show that it wasn't. > > Running current through the ESD diodes is a really bad idea. For one > thin, you can get subtle weirdness like Bill mentioned. > > Even if operation doesn't appear to be affected, repeated overvoltage > stress of the gates on the input buffers over time can lead to > threshold shifts that might cause the system to become unreliable or > stop working altogether. This could take a long time (months or > years) to occur so you might not catch it in testing. > > If it's TTL it's not going very fast. Could you interpose open-drain > drivers with pullups to 3.3V on the FPGA inputs, and proper > level-shifters open-drain drivers with pullups to 5V on the outputs? >My plan is to use level shifters - SN74CBT16211C - which are good to 7VDC, for interfacing to the TTL levels of a 6502 Data Bus. In most cases the TVS input protection is there in case of a short from lamp voltage (6.3VAC) of solenoids (24VDC). I am trying to protect the FPGA board from rare occurrences, or quite possibly the reason the original chip failed - due to perhaps an intermittent stray voltage outside of TTL limits. Trying to keep the board around 8.5 x 6cm or slightly larger. The dimensions are related to the three 40 pin devices this circuit is to replace and that sets the minimum size. This board will plug directly into the 3 IC sockets. Thanks, the input is all helpful! John :-#)# -- (Please post followups or tech inquiries to the USENET newsgroup) John's Jukes Ltd. MOVED to #7 - 3979 Marine Way, Burnaby, BC, Canada V5J 5E3 (604)872-5757 (Pinballs, Jukes, Video Games) www.flippers.com "Old pinballers never die, they just flip out."
Reply by ●October 15, 20212021-10-15
On 10/15/2021 19:36, John Robertson wrote:> On 2021/10/15 5:42 a.m., Steve Goldstein wrote: >> On Thu, 14 Oct 2021 18:28:30 -0700 (PDT), Anthony William Sloman >> <bill.sloman@ieee.org> wrote: >> >>> On Friday, October 15, 2021 at 7:21:36 AM UTC+11, John Larkin wrote: >>>> On Thu, 14 Oct 2021 21:16:03 +0100, piglet <erichp...@hotmail.com> >>>> wrote: >>>>> On 14/10/2021 8:32 pm, John Larkin wrote: >>>>>> >>>>>> For an input to the FPGA, you could use just a series resistor and >>>>>> let >>>>>> any overvoltage or spikes hit the ESD diodes. Debounce as needed. >>>>>> >>>>>> 10K or something. Paranoids could add a cap to ground, 1 nf or so. >>>>>> >>>>> >>>>> The MAX 10 datasheet has very specific input overvoltage specs, for >>>>> instance 4.27V for <4.3% of the time over 11.4 years, equally >>>>> bizarrely >>>>> they specifiy the supply voltage to three decimal places. >>>>> >>>>> I think Intel really do not want the ESD diodes to be touched? >>>>> >>>>> piglet >>>>> >>>> What are they for? >>> >>> They protect the circuit from catastrophic and irreversible failure. >>> There's no guarantee that the circuit will work to specification when >>> there's current flowing through the protection diodes, and the one >>> time I tried it, the integrated circuit didn't - and it took fairly >>> careful measurements to show that it wasn't. >> >> Running current through the ESD diodes is a really bad idea. For one >> thin, you can get subtle weirdness like Bill mentioned. >> >> Even if operation doesn't appear to be affected, repeated overvoltage >> stress of the gates on the input buffers over time can lead to >> threshold shifts that might cause the system to become unreliable or >> stop working altogether. This could take a long time (months or >> years) to occur so you might not catch it in testing. >> >> If it's TTL it's not going very fast. Could you interpose open-drain >> drivers with pullups to 3.3V on the FPGA inputs, and proper >> level-shifters open-drain drivers with pullups to 5V on the outputs? >> > > My plan is to use level shifters - SN74CBT16211C - which are good to > 7VDC, for interfacing to the TTL levels of a 6502 Data Bus. > > In most cases the TVS input protection is there in case of a short from > lamp voltage (6.3VAC) of solenoids (24VDC). I am trying to protect the > FPGA board from rare occurrences, or quite possibly the reason the > original chip failed - due to perhaps an intermittent stray voltage > outside of TTL limits. > > Trying to keep the board around 8.5 x 6cm or slightly larger. The > dimensions are related to the three 40 pin devices this circuit is to > replace and that sets the minimum size. This board will plug directly > into the 3 IC sockets. > > Thanks, the input is all helpful! > > John :-#)# >I have used 74lvxc3245 to buffer the (5V) ATA bus to a 3.3V processor, worked just fine. On a test unit for in-house use I also have a short ribbon cable which is constantly not quite so well connected, so far the buffer have survived the abuse this might subject them to. Perhaps worth looking at (have not looked at myself for years).
Reply by ●October 15, 20212021-10-15
On Fri, 15 Oct 2021 19:00:55 +0300, Dimiter_Popoff <dp@tgi-sci.com> wrote:>On 10/15/2021 17:00, jlarkin@highlandsniptechnology.com wrote: >> On Fri, 15 Oct 2021 08:42:09 -0400, Steve Goldstein >> <sgoldHAM@alum.mit.edu> wrote: >> >>> On Thu, 14 Oct 2021 18:28:30 -0700 (PDT), Anthony William Sloman >>> <bill.sloman@ieee.org> wrote: >>> >>>> On Friday, October 15, 2021 at 7:21:36 AM UTC+11, John Larkin wrote: >>>>> On Thu, 14 Oct 2021 21:16:03 +0100, piglet <erichp...@hotmail.com> >>>>> wrote: >>>>>> On 14/10/2021 8:32 pm, John Larkin wrote: >>>>>>> >>>>>>> For an input to the FPGA, you could use just a series resistor and let >>>>>>> any overvoltage or spikes hit the ESD diodes. Debounce as needed. >>>>>>> >>>>>>> 10K or something. Paranoids could add a cap to ground, 1 nf or so. >>>>>>> >>>>>> >>>>>> The MAX 10 datasheet has very specific input overvoltage specs, for >>>>>> instance 4.27V for <4.3% of the time over 11.4 years, equally bizarrely >>>>>> they specifiy the supply voltage to three decimal places. >>>>>> >>>>>> I think Intel really do not want the ESD diodes to be touched? >>>>>> >>>>>> piglet >>>>>> >>>>> What are they for? >>>> >>>> They protect the circuit from catastrophic and irreversible failure. There's no guarantee that the circuit will work to specification when there's current flowing through the protection diodes, and the one time I tried it, the integrated circuit didn't - and it took fairly careful measurements to show that it wasn't. >>> >>> Running current through the ESD diodes is a really bad idea. For one >>> thin, you can get subtle weirdness like Bill mentioned. >> >> In analog circuits, yes. The hazard in digitals is SCR latchup, which >> hasn't been a problem in properly designed chips since 4000A cmos >> logic. >> > >I have witnessed warnings about electric migration because of repetitive >use of the input protection diodes, this at the time when 120nm were >the norm. Never experienced it myself and frankly never believed it >would matter much back then but as the sizes get tinier I might be >scratching my head about that.Electromigration happens over time at extreme current densities. I doubt that a couple of hundred uA will damage the ESD diodes of an FPGA. -- If a man will begin with certainties, he shall end with doubts, but if he will be content to begin with doubts he shall end in certainties. Francis Bacon
Reply by ●October 15, 20212021-10-15
On 10/15/2021 20:11, John Larkin wrote:> On Fri, 15 Oct 2021 19:00:55 +0300, Dimiter_Popoff <dp@tgi-sci.com> > wrote: > >> On 10/15/2021 17:00, jlarkin@highlandsniptechnology.com wrote: >>> On Fri, 15 Oct 2021 08:42:09 -0400, Steve Goldstein >>> <sgoldHAM@alum.mit.edu> wrote: >>> >>>> On Thu, 14 Oct 2021 18:28:30 -0700 (PDT), Anthony William Sloman >>>> <bill.sloman@ieee.org> wrote: >>>> >>>>> On Friday, October 15, 2021 at 7:21:36 AM UTC+11, John Larkin wrote: >>>>>> On Thu, 14 Oct 2021 21:16:03 +0100, piglet <erichp...@hotmail.com> >>>>>> wrote: >>>>>>> On 14/10/2021 8:32 pm, John Larkin wrote: >>>>>>>> >>>>>>>> For an input to the FPGA, you could use just a series resistor and let >>>>>>>> any overvoltage or spikes hit the ESD diodes. Debounce as needed. >>>>>>>> >>>>>>>> 10K or something. Paranoids could add a cap to ground, 1 nf or so. >>>>>>>> >>>>>>> >>>>>>> The MAX 10 datasheet has very specific input overvoltage specs, for >>>>>>> instance 4.27V for <4.3% of the time over 11.4 years, equally bizarrely >>>>>>> they specifiy the supply voltage to three decimal places. >>>>>>> >>>>>>> I think Intel really do not want the ESD diodes to be touched? >>>>>>> >>>>>>> piglet >>>>>>> >>>>>> What are they for? >>>>> >>>>> They protect the circuit from catastrophic and irreversible failure. There's no guarantee that the circuit will work to specification when there's current flowing through the protection diodes, and the one time I tried it, the integrated circuit didn't - and it took fairly careful measurements to show that it wasn't. >>>> >>>> Running current through the ESD diodes is a really bad idea. For one >>>> thin, you can get subtle weirdness like Bill mentioned. >>> >>> In analog circuits, yes. The hazard in digitals is SCR latchup, which >>> hasn't been a problem in properly designed chips since 4000A cmos >>> logic. >>> >> >> I have witnessed warnings about electric migration because of repetitive >> use of the input protection diodes, this at the time when 120nm were >> the norm. Never experienced it myself and frankly never believed it >> would matter much back then but as the sizes get tinier I might be >> scratching my head about that. > > Electromigration happens over time at extreme current densities. I > doubt that a couple of hundred uA will damage the ESD diodes of an > FPGA. >I had the same attitude at the time (>10 years ago), but there were people who advocated it mattered. Can't remember who it was but they referred to someone having done some research on that. Happened on the si-list, people there usually know what they are talking about apart from being eager to sell you this or that tool.
