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Input protection for 3.3V FPGA in a TTL world...

Started by John Robertson October 14, 2021
> [snip] > Even if operation doesn't appear to be affected, repeated overvoltage > stress of the gates on the input buffers over time can lead to > threshold shifts that might cause the system to become unreliable or > stop working altogether. This could take a long time (months or > years) to occur so you might not catch it in testing. > [snip]
Ah (un)planned obsolescence - its not a bug; its a feature!
On Fri, 15 Oct 2021 20:19:50 +0300, Dimiter_Popoff <dp@tgi-sci.com>
wrote:

>On 10/15/2021 20:11, John Larkin wrote: >> On Fri, 15 Oct 2021 19:00:55 +0300, Dimiter_Popoff <dp@tgi-sci.com> >> wrote: >> >>> On 10/15/2021 17:00, jlarkin@highlandsniptechnology.com wrote: >>>> On Fri, 15 Oct 2021 08:42:09 -0400, Steve Goldstein >>>> <sgoldHAM@alum.mit.edu> wrote: >>>> >>>>> On Thu, 14 Oct 2021 18:28:30 -0700 (PDT), Anthony William Sloman >>>>> <bill.sloman@ieee.org> wrote: >>>>> >>>>>> On Friday, October 15, 2021 at 7:21:36 AM UTC+11, John Larkin wrote: >>>>>>> On Thu, 14 Oct 2021 21:16:03 +0100, piglet <erichp...@hotmail.com> >>>>>>> wrote: >>>>>>>> On 14/10/2021 8:32 pm, John Larkin wrote: >>>>>>>>> >>>>>>>>> For an input to the FPGA, you could use just a series resistor and let >>>>>>>>> any overvoltage or spikes hit the ESD diodes. Debounce as needed. >>>>>>>>> >>>>>>>>> 10K or something. Paranoids could add a cap to ground, 1 nf or so. >>>>>>>>> >>>>>>>> >>>>>>>> The MAX 10 datasheet has very specific input overvoltage specs, for >>>>>>>> instance 4.27V for <4.3% of the time over 11.4 years, equally bizarrely >>>>>>>> they specifiy the supply voltage to three decimal places. >>>>>>>> >>>>>>>> I think Intel really do not want the ESD diodes to be touched? >>>>>>>> >>>>>>>> piglet >>>>>>>> >>>>>>> What are they for? >>>>>> >>>>>> They protect the circuit from catastrophic and irreversible failure. There's no guarantee that the circuit will work to specification when there's current flowing through the protection diodes, and the one time I tried it, the integrated circuit didn't - and it took fairly careful measurements to show that it wasn't. >>>>> >>>>> Running current through the ESD diodes is a really bad idea. For one >>>>> thin, you can get subtle weirdness like Bill mentioned. >>>> >>>> In analog circuits, yes. The hazard in digitals is SCR latchup, which >>>> hasn't been a problem in properly designed chips since 4000A cmos >>>> logic. >>>> >>> >>> I have witnessed warnings about electric migration because of repetitive >>> use of the input protection diodes, this at the time when 120nm were >>> the norm. Never experienced it myself and frankly never believed it >>> would matter much back then but as the sizes get tinier I might be >>> scratching my head about that. >> >> Electromigration happens over time at extreme current densities. I >> doubt that a couple of hundred uA will damage the ESD diodes of an >> FPGA. >> > >I had the same attitude at the time (>10 years ago), but there were >people who advocated it mattered. Can't remember who it was but they >referred to someone having done some research on that. Happened on >the si-list, people there usually know what they are talking about >apart from being eager to sell you this or that tool.
I've seen analog chips go crazy with tiny esd diode currents. LM324 family parts were notorious. Old 4000 series logic would latch up and fry; that happened to me on a tugboat alarm system. Some mixed-signal parts, like DACs, could also latch up and short the supply with a tiny ESD current. Chip designers seem to forget about PNPN latchup now and then. I've used some ICs purely for their ESD diodes, to clamp the inputs of other ICs. Analog mux's in particular. I want a chip with V+, V-, and every other pin a schottky pair. -- If a man will begin with certainties, he shall end with doubts, but if he will be content to begin with doubts he shall end in certainties. Francis Bacon
fredag den 15. oktober 2021 kl. 19.49.16 UTC+2 skrev John Larkin:
> On Fri, 15 Oct 2021 20:19:50 +0300, Dimiter_Popoff <d...@tgi-sci.com> > wrote: > > >On 10/15/2021 20:11, John Larkin wrote: > >> On Fri, 15 Oct 2021 19:00:55 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >> wrote: > >> > >>> On 10/15/2021 17:00, jla...@highlandsniptechnology.com wrote: > >>>> On Fri, 15 Oct 2021 08:42:09 -0400, Steve Goldstein > >>>> <sgol...@alum.mit.edu> wrote: > >>>> > >>>>> On Thu, 14 Oct 2021 18:28:30 -0700 (PDT), Anthony William Sloman > >>>>> <bill....@ieee.org> wrote: > >>>>> > >>>>>> On Friday, October 15, 2021 at 7:21:36 AM UTC+11, John Larkin wrote: > >>>>>>> On Thu, 14 Oct 2021 21:16:03 +0100, piglet <erichp...@hotmail.com> > >>>>>>> wrote: > >>>>>>>> On 14/10/2021 8:32 pm, John Larkin wrote: > >>>>>>>>> > >>>>>>>>> For an input to the FPGA, you could use just a series resistor and let > >>>>>>>>> any overvoltage or spikes hit the ESD diodes. Debounce as needed. > >>>>>>>>> > >>>>>>>>> 10K or something. Paranoids could add a cap to ground, 1 nf or so. > >>>>>>>>> > >>>>>>>> > >>>>>>>> The MAX 10 datasheet has very specific input overvoltage specs, for > >>>>>>>> instance 4.27V for <4.3% of the time over 11.4 years, equally bizarrely > >>>>>>>> they specifiy the supply voltage to three decimal places. > >>>>>>>> > >>>>>>>> I think Intel really do not want the ESD diodes to be touched? > >>>>>>>> > >>>>>>>> piglet > >>>>>>>> > >>>>>>> What are they for? > >>>>>> > >>>>>> They protect the circuit from catastrophic and irreversible failure. There's no guarantee that the circuit will work to specification when there's current flowing through the protection diodes, and the one time I tried it, the integrated circuit didn't - and it took fairly careful measurements to show that it wasn't. > >>>>> > >>>>> Running current through the ESD diodes is a really bad idea. For one > >>>>> thin, you can get subtle weirdness like Bill mentioned. > >>>> > >>>> In analog circuits, yes. The hazard in digitals is SCR latchup, which > >>>> hasn't been a problem in properly designed chips since 4000A cmos > >>>> logic. > >>>> > >>> > >>> I have witnessed warnings about electric migration because of repetitive > >>> use of the input protection diodes, this at the time when 120nm were > >>> the norm. Never experienced it myself and frankly never believed it > >>> would matter much back then but as the sizes get tinier I might be > >>> scratching my head about that. > >> > >> Electromigration happens over time at extreme current densities. I > >> doubt that a couple of hundred uA will damage the ESD diodes of an > >> FPGA. > >> > > > >I had the same attitude at the time (>10 years ago), but there were > >people who advocated it mattered. Can't remember who it was but they > >referred to someone having done some research on that. Happened on > >the si-list, people there usually know what they are talking about > >apart from being eager to sell you this or that tool. > I've seen analog chips go crazy with tiny esd diode currents. LM324 > family parts were notorious. > > Old 4000 series logic would latch up and fry; that happened to me on a > tugboat alarm system. Some mixed-signal parts, like DACs, could also > latch up and short the supply with a tiny ESD current. > > Chip designers seem to forget about PNPN latchup now and then. > > I've used some ICs purely for their ESD diodes, to clamp the inputs of > other ICs. Analog mux's in particular. > > I want a chip with V+, V-, and every other pin a schottky pair.
you could use a diode bridge, that'll do two inputs else, will these do? https://www.st.com/resource/en/datasheet/da108s1.pdf https://www.ti.com/lit/ds/symlink/sn74s1051.pdf
fredag den 15. oktober 2021 kl. 19.11.40 UTC+2 skrev John Larkin:
> On Fri, 15 Oct 2021 19:00:55 +0300, Dimiter_Popoff <d...@tgi-sci.com> > wrote: > >On 10/15/2021 17:00, jla...@highlandsniptechnology.com wrote: > >> On Fri, 15 Oct 2021 08:42:09 -0400, Steve Goldstein > >> <sgol...@alum.mit.edu> wrote: > >> > >>> On Thu, 14 Oct 2021 18:28:30 -0700 (PDT), Anthony William Sloman > >>> <bill....@ieee.org> wrote: > >>> > >>>> On Friday, October 15, 2021 at 7:21:36 AM UTC+11, John Larkin wrote: > >>>>> On Thu, 14 Oct 2021 21:16:03 +0100, piglet <erichp...@hotmail.com> > >>>>> wrote: > >>>>>> On 14/10/2021 8:32 pm, John Larkin wrote: > >>>>>>> > >>>>>>> For an input to the FPGA, you could use just a series resistor and let > >>>>>>> any overvoltage or spikes hit the ESD diodes. Debounce as needed. > >>>>>>> > >>>>>>> 10K or something. Paranoids could add a cap to ground, 1 nf or so. > >>>>>>> > >>>>>> > >>>>>> The MAX 10 datasheet has very specific input overvoltage specs, for > >>>>>> instance 4.27V for <4.3% of the time over 11.4 years, equally bizarrely > >>>>>> they specifiy the supply voltage to three decimal places. > >>>>>> > >>>>>> I think Intel really do not want the ESD diodes to be touched? > >>>>>> > >>>>>> piglet > >>>>>> > >>>>> What are they for? > >>>> > >>>> They protect the circuit from catastrophic and irreversible failure. There's no guarantee that the circuit will work to specification when there's current flowing through the protection diodes, and the one time I tried it, the integrated circuit didn't - and it took fairly careful measurements to show that it wasn't. > >>> > >>> Running current through the ESD diodes is a really bad idea. For one > >>> thin, you can get subtle weirdness like Bill mentioned. > >> > >> In analog circuits, yes. The hazard in digitals is SCR latchup, which > >> hasn't been a problem in properly designed chips since 4000A cmos > >> logic. > >> > > > >I have witnessed warnings about electric migration because of repetitive > >use of the input protection diodes, this at the time when 120nm were > >the norm. Never experienced it myself and frankly never believed it > >would matter much back then but as the sizes get tinier I might be > >scratching my head about that. > Electromigration happens over time at extreme current densities. I > doubt that a couple of hundred uA will damage the ESD diodes of an > FPGA.
Xilinx usually spec (atleast for 3.3V capable inputs) that as long as the current is limited to +/-25mA all is good
On Friday, October 15, 2021 at 10:49:16 AM UTC-7, John Larkin wrote:

[on clamping to an acceptable input range]

> I want a chip with V+, V-, and every other pin a schottky pair.
That's only part of what is needed, though: you want the V+ connection to sink current, but a simple connection to a low-impedance source won't always act as a sink. And you want a V- that sources current, but (for classical ECL, at -5.2VDC) some V- candidates aren't ground, and only sink current, won't source reliably. So, maybe connect a PNP base to (V-) + 0.7V, collector to GND, and run some of those diodes to the emitter. Then an NPN base to (V+) - 0.7V, collector to GND, and run the rest of the diodes to THAT emitter. Should be an easier task to drive the base current, not the full surge, and a probe on those emitters will tell you if there's spikes arriving.
On Fri, 15 Oct 2021 11:29:53 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>fredag den 15. oktober 2021 kl. 19.49.16 UTC+2 skrev John Larkin: >> On Fri, 15 Oct 2021 20:19:50 +0300, Dimiter_Popoff <d...@tgi-sci.com> >> wrote: >> >> >On 10/15/2021 20:11, John Larkin wrote: >> >> On Fri, 15 Oct 2021 19:00:55 +0300, Dimiter_Popoff <d...@tgi-sci.com> >> >> wrote: >> >> >> >>> On 10/15/2021 17:00, jla...@highlandsniptechnology.com wrote: >> >>>> On Fri, 15 Oct 2021 08:42:09 -0400, Steve Goldstein >> >>>> <sgol...@alum.mit.edu> wrote: >> >>>> >> >>>>> On Thu, 14 Oct 2021 18:28:30 -0700 (PDT), Anthony William Sloman >> >>>>> <bill....@ieee.org> wrote: >> >>>>> >> >>>>>> On Friday, October 15, 2021 at 7:21:36 AM UTC+11, John Larkin wrote: >> >>>>>>> On Thu, 14 Oct 2021 21:16:03 +0100, piglet <erichp...@hotmail.com> >> >>>>>>> wrote: >> >>>>>>>> On 14/10/2021 8:32 pm, John Larkin wrote: >> >>>>>>>>> >> >>>>>>>>> For an input to the FPGA, you could use just a series resistor and let >> >>>>>>>>> any overvoltage or spikes hit the ESD diodes. Debounce as needed. >> >>>>>>>>> >> >>>>>>>>> 10K or something. Paranoids could add a cap to ground, 1 nf or so. >> >>>>>>>>> >> >>>>>>>> >> >>>>>>>> The MAX 10 datasheet has very specific input overvoltage specs, for >> >>>>>>>> instance 4.27V for <4.3% of the time over 11.4 years, equally bizarrely >> >>>>>>>> they specifiy the supply voltage to three decimal places. >> >>>>>>>> >> >>>>>>>> I think Intel really do not want the ESD diodes to be touched? >> >>>>>>>> >> >>>>>>>> piglet >> >>>>>>>> >> >>>>>>> What are they for? >> >>>>>> >> >>>>>> They protect the circuit from catastrophic and irreversible failure. There's no guarantee that the circuit will work to specification when there's current flowing through the protection diodes, and the one time I tried it, the integrated circuit didn't - and it took fairly careful measurements to show that it wasn't. >> >>>>> >> >>>>> Running current through the ESD diodes is a really bad idea. For one >> >>>>> thin, you can get subtle weirdness like Bill mentioned. >> >>>> >> >>>> In analog circuits, yes. The hazard in digitals is SCR latchup, which >> >>>> hasn't been a problem in properly designed chips since 4000A cmos >> >>>> logic. >> >>>> >> >>> >> >>> I have witnessed warnings about electric migration because of repetitive >> >>> use of the input protection diodes, this at the time when 120nm were >> >>> the norm. Never experienced it myself and frankly never believed it >> >>> would matter much back then but as the sizes get tinier I might be >> >>> scratching my head about that. >> >> >> >> Electromigration happens over time at extreme current densities. I >> >> doubt that a couple of hundred uA will damage the ESD diodes of an >> >> FPGA. >> >> >> > >> >I had the same attitude at the time (>10 years ago), but there were >> >people who advocated it mattered. Can't remember who it was but they >> >referred to someone having done some research on that. Happened on >> >the si-list, people there usually know what they are talking about >> >apart from being eager to sell you this or that tool. >> I've seen analog chips go crazy with tiny esd diode currents. LM324 >> family parts were notorious. >> >> Old 4000 series logic would latch up and fry; that happened to me on a >> tugboat alarm system. Some mixed-signal parts, like DACs, could also >> latch up and short the supply with a tiny ESD current. >> >> Chip designers seem to forget about PNPN latchup now and then. >> >> I've used some ICs purely for their ESD diodes, to clamp the inputs of >> other ICs. Analog mux's in particular. >> >> I want a chip with V+, V-, and every other pin a schottky pair. > >you could use a diode bridge, that'll do two inputs > >else, will these do? > >https://www.st.com/resource/en/datasheet/da108s1.pdf >https://www.ti.com/lit/ds/symlink/sn74s1051.pdf
That second one is perfect. The OP could uses series r-packs and those clamps to go into his FPGA. Maybe use a digital debouncer. -- If a man will begin with certainties, he shall end with doubts, but if he will be content to begin with doubts he shall end in certainties. Francis Bacon
On 10/15/2021 20:49, John Larkin wrote:
> On Fri, 15 Oct 2021 20:19:50 +0300, Dimiter_Popoff <dp@tgi-sci.com> > wrote: > >> On 10/15/2021 20:11, John Larkin wrote: >>> On Fri, 15 Oct 2021 19:00:55 +0300, Dimiter_Popoff <dp@tgi-sci.com> >>> wrote: >>> >>>> On 10/15/2021 17:00, jlarkin@highlandsniptechnology.com wrote: >>>>> On Fri, 15 Oct 2021 08:42:09 -0400, Steve Goldstein >>>>> <sgoldHAM@alum.mit.edu> wrote: >>>>> >>>>>> On Thu, 14 Oct 2021 18:28:30 -0700 (PDT), Anthony William Sloman >>>>>> <bill.sloman@ieee.org> wrote: >>>>>> >>>>>>> On Friday, October 15, 2021 at 7:21:36 AM UTC+11, John Larkin wrote: >>>>>>>> On Thu, 14 Oct 2021 21:16:03 +0100, piglet <erichp...@hotmail.com> >>>>>>>> wrote: >>>>>>>>> On 14/10/2021 8:32 pm, John Larkin wrote: >>>>>>>>>> >>>>>>>>>> For an input to the FPGA, you could use just a series resistor and let >>>>>>>>>> any overvoltage or spikes hit the ESD diodes. Debounce as needed. >>>>>>>>>> >>>>>>>>>> 10K or something. Paranoids could add a cap to ground, 1 nf or so. >>>>>>>>>> >>>>>>>>> >>>>>>>>> The MAX 10 datasheet has very specific input overvoltage specs, for >>>>>>>>> instance 4.27V for <4.3% of the time over 11.4 years, equally bizarrely >>>>>>>>> they specifiy the supply voltage to three decimal places. >>>>>>>>> >>>>>>>>> I think Intel really do not want the ESD diodes to be touched? >>>>>>>>> >>>>>>>>> piglet >>>>>>>>> >>>>>>>> What are they for? >>>>>>> >>>>>>> They protect the circuit from catastrophic and irreversible failure. There's no guarantee that the circuit will work to specification when there's current flowing through the protection diodes, and the one time I tried it, the integrated circuit didn't - and it took fairly careful measurements to show that it wasn't. >>>>>> >>>>>> Running current through the ESD diodes is a really bad idea. For one >>>>>> thin, you can get subtle weirdness like Bill mentioned. >>>>> >>>>> In analog circuits, yes. The hazard in digitals is SCR latchup, which >>>>> hasn't been a problem in properly designed chips since 4000A cmos >>>>> logic. >>>>> >>>> >>>> I have witnessed warnings about electric migration because of repetitive >>>> use of the input protection diodes, this at the time when 120nm were >>>> the norm. Never experienced it myself and frankly never believed it >>>> would matter much back then but as the sizes get tinier I might be >>>> scratching my head about that. >>> >>> Electromigration happens over time at extreme current densities. I >>> doubt that a couple of hundred uA will damage the ESD diodes of an >>> FPGA. >>> >> >> I had the same attitude at the time (>10 years ago), but there were >> people who advocated it mattered. Can't remember who it was but they >> referred to someone having done some research on that. Happened on >> the si-list, people there usually know what they are talking about >> apart from being eager to sell you this or that tool. > > I've seen analog chips go crazy with tiny esd diode currents. LM324 > family parts were notorious.
I've had that, too - with an ADC, ADS7830 - some current from one of the analog inputs to something negative to the ADC's V- was confusing it (a few LSB error for all other inputs IIRC). Must have been no more than 2-3mA; got it down to 1/4 uA to get rid of the problem (still relies on the protection diode, just less current).
> > Old 4000 series logic would latch up and fry; that happened to me on a > tugboat alarm system. Some mixed-signal parts, like DACs, could also > latch up and short the supply with a tiny ESD current. > > Chip designers seem to forget about PNPN latchup now and then. > > I've used some ICs purely for their ESD diodes, to clamp the inputs of > other ICs. Analog mux's in particular. > > I want a chip with V+, V-, and every other pin a schottky pair. > >
Well these diodes add input capacitance so they have to be careful. But perhaps they happen to be negligent, too, who knows.
On Friday, 15 October 2021 at 19:47:37 UTC+1, Dimiter Popoff wrote:
> On 10/15/2021 20:49, John Larkin wrote: > > On Fri, 15 Oct 2021 20:19:50 +0300, Dimiter_Popoff <d...@tgi-sci.com> > > wrote: > > > >> On 10/15/2021 20:11, John Larkin wrote: > >>> On Fri, 15 Oct 2021 19:00:55 +0300, Dimiter_Popoff <d...@tgi-sci.com> > >>> wrote: > >>> > >>>> On 10/15/2021 17:00, jla...@highlandsniptechnology.com wrote: > >>>>> On Fri, 15 Oct 2021 08:42:09 -0400, Steve Goldstein > >>>>> <sgol...@alum.mit.edu> wrote: > >>>>> > >>>>>> On Thu, 14 Oct 2021 18:28:30 -0700 (PDT), Anthony William Sloman > >>>>>> <bill....@ieee.org> wrote: > >>>>>> > >>>>>>> On Friday, October 15, 2021 at 7:21:36 AM UTC+11, John Larkin wrote: > >>>>>>>> On Thu, 14 Oct 2021 21:16:03 +0100, piglet <erichp...@hotmail.com> > >>>>>>>> wrote: > >>>>>>>>> On 14/10/2021 8:32 pm, John Larkin wrote: > >>>>>>>>>> > >>>>>>>>>> For an input to the FPGA, you could use just a series resistor and let > >>>>>>>>>> any overvoltage or spikes hit the ESD diodes. Debounce as needed. > >>>>>>>>>> > >>>>>>>>>> 10K or something. Paranoids could add a cap to ground, 1 nf or so. > >>>>>>>>>> > >>>>>>>>> > >>>>>>>>> The MAX 10 datasheet has very specific input overvoltage specs, for > >>>>>>>>> instance 4.27V for <4.3% of the time over 11.4 years, equally bizarrely > >>>>>>>>> they specifiy the supply voltage to three decimal places. > >>>>>>>>> > >>>>>>>>> I think Intel really do not want the ESD diodes to be touched? > >>>>>>>>> > >>>>>>>>> piglet > >>>>>>>>> > >>>>>>>> What are they for? > >>>>>>> > >>>>>>> They protect the circuit from catastrophic and irreversible failure. There's no guarantee that the circuit will work to specification when there's current flowing through the protection diodes, and the one time I tried it, the integrated circuit didn't - and it took fairly careful measurements to show that it wasn't. > >>>>>> > >>>>>> Running current through the ESD diodes is a really bad idea. For one > >>>>>> thin, you can get subtle weirdness like Bill mentioned. > >>>>> > >>>>> In analog circuits, yes. The hazard in digitals is SCR latchup, which > >>>>> hasn't been a problem in properly designed chips since 4000A cmos > >>>>> logic. > >>>>> > >>>> > >>>> I have witnessed warnings about electric migration because of repetitive > >>>> use of the input protection diodes, this at the time when 120nm were > >>>> the norm. Never experienced it myself and frankly never believed it > >>>> would matter much back then but as the sizes get tinier I might be > >>>> scratching my head about that. > >>> > >>> Electromigration happens over time at extreme current densities. I > >>> doubt that a couple of hundred uA will damage the ESD diodes of an > >>> FPGA. > >>> > >> > >> I had the same attitude at the time (>10 years ago), but there were > >> people who advocated it mattered. Can't remember who it was but they > >> referred to someone having done some research on that. Happened on > >> the si-list, people there usually know what they are talking about > >> apart from being eager to sell you this or that tool. > > > > I've seen analog chips go crazy with tiny esd diode currents. LM324 > > family parts were notorious. > I've had that, too - with an ADC, ADS7830 - some current from one of > the analog inputs to something negative to the ADC's V- was confusing > it (a few LSB error for all other inputs IIRC). Must have been no more > than 2-3mA; got it down to 1/4 uA to get rid of the problem (still > relies on the protection diode, just less current). > > > > Old 4000 series logic would latch up and fry; that happened to me on a > > tugboat alarm system. Some mixed-signal parts, like DACs, could also > > latch up and short the supply with a tiny ESD current. > > > > Chip designers seem to forget about PNPN latchup now and then. > > > > I've used some ICs purely for their ESD diodes, to clamp the inputs of > > other ICs. Analog mux's in particular. > > > > I want a chip with V+, V-, and every other pin a schottky pair. > > > > > Well these diodes add input capacitance so they have to be careful. > But perhaps they happen to be negligent, too, who knows.
It might seem extravagant, but a BAV99W on each input with series resistance before and after the diode pair works well. One end of the BAV99W to ground and the other end to a dedicated ESD supply set to about 0.5V below the supply voltage of the device to be protected which consists of a TL431 running at its minimum current and a decoupling capacitor across it large enough to ensure it is stable regardless of manufacturer. 10uF ceramic is normally fine. I've used this arrangement in automotive products that have shipped in very large numbers and they have given effective protection. The mid-point of a BAV99 has very low capacitance - around 1pF if the series pair is biased at 3V. They are very robust and incredibly cheap in high volumes. The W package is easier to fit close to dense connectors than the SOT23 version. John
On Fri, 15 Oct 2021 11:38:21 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

>On Friday, October 15, 2021 at 10:49:16 AM UTC-7, John Larkin wrote: > >[on clamping to an acceptable input range] > >> I want a chip with V+, V-, and every other pin a schottky pair. > >That's only part of what is needed, though: you want the V+ connection to sink current, but >a simple connection to a low-impedance source won't always act as a sink. >And you want a V- that sources current, but (for classical ECL, at -5.2VDC) >some V- candidates aren't ground, and only sink current, won't source reliably. > >So, maybe connect a PNP base to (V-) + 0.7V, collector to GND, and run some of those diodes >to the emitter. Then an NPN base to (V+) - 0.7V, collector to GND, and run the rest >of the diodes to THAT emitter. Should be an easier task to drive the base current, >not the full surge, and a probe on those emitters will tell you if there's spikes arriving.
Why not a series resistor to limit current, then schottky diode pairs to ground and FPGA i/o bank supply? -- If a man will begin with certainties, he shall end with doubts, but if he will be content to begin with doubts he shall end in certainties. Francis Bacon
On Friday, October 15, 2021 at 12:34:21 PM UTC-7, John Larkin wrote:
> On Fri, 15 Oct 2021 11:38:21 -0700 (PDT), whit3rd <whi...@gmail.com> > wrote: > >On Friday, October 15, 2021 at 10:49:16 AM UTC-7, John Larkin wrote: > > > >[on clamping to an acceptable input range] > > > >> I want a chip with V+, V-, and every other pin a schottky pair. > > > >That's only part of what is needed, though: you want the V+ connection to sink current, but > >a simple connection to a low-impedance source won't always act as a sink.
...
> >So, maybe connect a PNP base to (V-) + 0.7V, collector to GND, and run some of those diodes > >to the emitter.
> Why not a series resistor to limit current, then schottky diode pairs > to ground and FPGA i/o bank supply?
A series resistor only limits current when you know the applied voltage; the purpose of protection favors a big 'acceptable' range of input voltages, thus a big range of currents is to be expected. Do you want that range pushed into the FPGA supply? Input resistor and diode pair is the MC1489 input circuit, good for +/- 20V indefinitely.