Forums

Input protection for 3.3V FPGA in a TTL world...

Started by John Robertson October 14, 2021
On Fri, 15 Oct 2021 15:40:32 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

>On Friday, October 15, 2021 at 12:34:21 PM UTC-7, John Larkin wrote: >> On Fri, 15 Oct 2021 11:38:21 -0700 (PDT), whit3rd <whi...@gmail.com> >> wrote: >> >On Friday, October 15, 2021 at 10:49:16 AM UTC-7, John Larkin wrote: >> > >> >[on clamping to an acceptable input range] >> > >> >> I want a chip with V+, V-, and every other pin a schottky pair. >> > >> >That's only part of what is needed, though: you want the V+ connection to sink current, but >> >a simple connection to a low-impedance source won't always act as a sink. >... >> >So, maybe connect a PNP base to (V-) + 0.7V, collector to GND, and run some of those diodes >> >to the emitter. > >> Why not a series resistor to limit current, then schottky diode pairs >> to ground and FPGA i/o bank supply? > >A series resistor only limits current when you know the applied voltage; the >purpose of protection favors a big 'acceptable' range of input voltages, >thus a big range of currents is to be expected. Do you want that range >pushed into the FPGA supply? > >Input resistor and diode pair is the MC1489 input circuit, good for +/- 20V indefinitely.
I think the requested range was "TTL". I'll check the thread title to make sure. -- If a man will begin with certainties, he shall end with doubts, but if he will be content to begin with doubts he shall end in certainties. Francis Bacon
l&oslash;rdag den 16. oktober 2021 kl. 00.50.07 UTC+2 skrev John Larkin:
> On Fri, 15 Oct 2021 15:40:32 -0700 (PDT), whit3rd <whi...@gmail.com> > wrote: > > >On Friday, October 15, 2021 at 12:34:21 PM UTC-7, John Larkin wrote: > >> On Fri, 15 Oct 2021 11:38:21 -0700 (PDT), whit3rd <whi...@gmail.com> > >> wrote: > >> >On Friday, October 15, 2021 at 10:49:16 AM UTC-7, John Larkin wrote: > >> > > >> >[on clamping to an acceptable input range] > >> > > >> >> I want a chip with V+, V-, and every other pin a schottky pair. > >> > > >> >That's only part of what is needed, though: you want the V+ connection to sink current, but > >> >a simple connection to a low-impedance source won't always act as a sink. > >... > >> >So, maybe connect a PNP base to (V-) + 0.7V, collector to GND, and run some of those diodes > >> >to the emitter. > > > >> Why not a series resistor to limit current, then schottky diode pairs > >> to ground and FPGA i/o bank supply? > > > >A series resistor only limits current when you know the applied voltage; the > >purpose of protection favors a big 'acceptable' range of input voltages, > >thus a big range of currents is to be expected. Do you want that range > >pushed into the FPGA supply? > > > >Input resistor and diode pair is the MC1489 input circuit, good for +/- 20V indefinitely. > I think the requested range was "TTL". I'll check the thread title to > make sure.
yeh and for real 5V TTL to 3.3V CMOS you probably wouldn't need anything since the TTL Voh is quite wimpy
On Friday, October 15, 2021 at 4:27:01 PM UTC-7, lang...@fonz.dk wrote:

> yeh and for real 5V TTL to 3.3V CMOS you probably wouldn't need anything since the TTL Voh is quite wimpy
This is about an old machine, possibly with existing retrofits, getting another retrofit, with circa 50 signals to handle. If some past modification used a few 74ACT family chips, those could source more than just wimpy currents at over 3.3V; 24 mA per pin, 25 pins, comes to over half an amp. There's more than one kind of TTL family chip, and output/input variation is huge. If you buffer everything through an OC buffer, with pullup to 3.3V, TTL drive to 3.3V logic doesn't have any incompatibility at all.
On Friday, October 15, 2021 at 10:12:08 PM UTC-7, whit3rd wrote:
> On Friday, October 15, 2021 at 4:27:01 PM UTC-7, lang...@fonz.dk wrote: > > > yeh and for real 5V TTL to 3.3V CMOS you probably wouldn't need anything since the TTL Voh is quite wimpy > This is about an old machine, possibly with existing retrofits, getting another retrofit, > with circa 50 signals to handle. > > If some past modification used a few 74ACT family chips, those could source more than just wimpy currents > at over 3.3V; 24 mA per pin, 25 pins, comes to over half an amp. There's more than one kind of TTL > family chip, and output/input variation is huge.
Oops; I slipped a decimal place. 24 mA per pin, 25 pins, is six amps, of course.
> If you buffer everything through an OC buffer, with pullup to 3.3V, TTL drive to 3.3V logic doesn't have > any incompatibility at all.
On Friday, October 15, 2021 at 4:27:01 PM UTC-7, lang...@fonz.dk wrote:

> yeh and for real 5V TTL to 3.3V CMOS you probably wouldn't need anything since the TTL Voh is quite wimpy
This is about an old machine, with past modifications, though... If someone plugged in a few 74ACT family chips, those could source more than just wimpy currents at over 3.3V; 24 mA per pin, 25 pins, comes to over half an amp.
l&oslash;rdag den 16. oktober 2021 kl. 07.32.01 UTC+2 skrev whit3rd:
> On Friday, October 15, 2021 at 4:27:01 PM UTC-7, lang...@fonz.dk wrote: > > > yeh and for real 5V TTL to 3.3V CMOS you probably wouldn't need anything since the TTL Voh is quite wimpy > This is about an old machine, with past modifications, though... > > If someone plugged in a few 74ACT family chips, those could source more than just wimpy currents > at over 3.3V; 24 mA per pin, 25 pins, comes to over half an amp.
correct, then you'd want atleast a few hundred Ohm in series
On Fri, 15 Oct 2021 22:15:11 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

>On Friday, October 15, 2021 at 10:12:08 PM UTC-7, whit3rd wrote: >> On Friday, October 15, 2021 at 4:27:01 PM UTC-7, lang...@fonz.dk wrote: >> >> > yeh and for real 5V TTL to 3.3V CMOS you probably wouldn't need anything since the TTL Voh is quite wimpy >> This is about an old machine, possibly with existing retrofits, getting another retrofit, >> with circa 50 signals to handle. >> >> If some past modification used a few 74ACT family chips, those could source more than just wimpy currents >> at over 3.3V; 24 mA per pin, 25 pins, comes to over half an amp. There's more than one kind of TTL >> family chip, and output/input variation is huge. > >Oops; I slipped a decimal place. 24 mA per pin, 25 pins, is six amps, of course.
Of course not. -- Father Brown's figure remained quite dark and still; but in that instant he had lost his head. His head was always most valuable when he had lost it.
On Friday, October 15, 2021 at 12:36:21 PM UTC-4, John Robertson wrote:
> On 2021/10/15 5:42 a.m., Steve Goldstein wrote: > > On Thu, 14 Oct 2021 18:28:30 -0700 (PDT), Anthony William Sloman > > <bill....@ieee.org> wrote: > > > >> On Friday, October 15, 2021 at 7:21:36 AM UTC+11, John Larkin wrote: > >>> On Thu, 14 Oct 2021 21:16:03 +0100, piglet <erichp...@hotmail.com> > >>> wrote: > >>>> On 14/10/2021 8:32 pm, John Larkin wrote: > >>>>> > >>>>> For an input to the FPGA, you could use just a series resistor and let > >>>>> any overvoltage or spikes hit the ESD diodes. Debounce as needed. > >>>>> > >>>>> 10K or something. Paranoids could add a cap to ground, 1 nf or so. > >>>>> > >>>> > >>>> The MAX 10 datasheet has very specific input overvoltage specs, for > >>>> instance 4.27V for <4.3% of the time over 11.4 years, equally bizarrely > >>>> they specifiy the supply voltage to three decimal places. > >>>> > >>>> I think Intel really do not want the ESD diodes to be touched? > >>>> > >>>> piglet > >>>> > >>> What are they for? > >> > >> They protect the circuit from catastrophic and irreversible failure. There's no guarantee that the circuit will work to specification when there's current flowing through the protection diodes, and the one time I tried it, the integrated circuit didn't - and it took fairly careful measurements to show that it wasn't. > > > > Running current through the ESD diodes is a really bad idea. For one > > thin, you can get subtle weirdness like Bill mentioned. > > > > Even if operation doesn't appear to be affected, repeated overvoltage > > stress of the gates on the input buffers over time can lead to > > threshold shifts that might cause the system to become unreliable or > > stop working altogether. This could take a long time (months or > > years) to occur so you might not catch it in testing. > > > > If it's TTL it's not going very fast. Could you interpose open-drain > > drivers with pullups to 3.3V on the FPGA inputs, and proper > > level-shifters open-drain drivers with pullups to 5V on the outputs? > > > My plan is to use level shifters - SN74CBT16211C - which are good to > 7VDC, for interfacing to the TTL levels of a 6502 Data Bus. > > In most cases the TVS input protection is there in case of a short from > lamp voltage (6.3VAC) of solenoids (24VDC). I am trying to protect the > FPGA board from rare occurrences, or quite possibly the reason the > original chip failed - due to perhaps an intermittent stray voltage > outside of TTL limits. > > Trying to keep the board around 8.5 x 6cm or slightly larger. The > dimensions are related to the three 40 pin devices this circuit is to > replace and that sets the minimum size. This board will plug directly > into the 3 IC sockets. > > Thanks, the input is all helpful!
Don't know if this thread is still active or if I caught all the details of requirements. I use the SN74CBT3384A part for interfacing 3.3 volt CMOS FPGA I/Os to 5 volt circuits. This part uses CMOS FETs to inherently limit the signal on the 3.3V side to about 3.0 volts, give or take. To protect this part against the real world would only require something like a zener diode and a series resistor on each lead. The parts have 10 switches which are bidirectional, so for 20 I/Os you need two devices. They come in many packages and are less than a dollar. https://www.ti.com/lit/gpn/sn74cbt3384a I've used either this switch or a similar device on boards I've made many of. Unfortunately I had a computer fail and can't get to my data at the moment. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209